1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
32 #include "pipe/p_state.h"
33 #include "compiler/shader_enums.h"
34 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 /* user-clip-plane components, up to 8x vec4's: */
64 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
68 * For consts needed to pass internal values to shader which may or may not
69 * be required, rather than allocating worst-case const space, we scan the
70 * shader and allocate consts as-needed:
72 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
75 * + Image dimensions: needed to calculate pixel offset, but only for
76 * images that have a image_store intrinsic
78 struct ir3_driver_const_layout
{
80 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
81 uint32_t count
; /* number of consts allocated */
82 /* one const allocated per SSBO which has get_buffer_size,
83 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
86 uint32_t off
[PIPE_MAX_SHADER_BUFFERS
];
90 uint32_t mask
; /* bitmask of images that have image_store */
91 uint32_t count
; /* number of consts allocated */
92 /* three const allocated per image which has image_store:
93 * + cpp (bytes per pixel)
95 * + array_pitch (z pitch)
97 uint32_t off
[PIPE_MAX_SHADER_IMAGES
];
101 /* Configuration key used to identify a shader variant.. different
102 * shader variants can be used to implement features not supported
103 * in hw (two sided color), binning-pass vertex shader, etc.
105 struct ir3_shader_key
{
109 * Combined Vertex/Fragment shader parameters:
111 unsigned ucp_enables
: 8;
113 /* do we need to check {v,f}saturate_{s,t,r}? */
114 unsigned has_per_samp
: 1;
117 * Vertex shader variant parameters:
119 unsigned binning_pass
: 1;
120 unsigned vclamp_color
: 1;
123 * Fragment shader variant parameters:
125 unsigned color_two_side
: 1;
126 unsigned half_precision
: 1;
127 /* used when shader needs to handle flat varyings (a4xx)
128 * for front/back color inputs to frag shader:
130 unsigned rasterflat
: 1;
131 unsigned fclamp_color
: 1;
136 /* bitmask of sampler which needs coords clamped for vertex
139 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
141 /* bitmask of sampler which needs coords clamped for frag
144 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
146 /* bitmask of ms shifts */
147 uint32_t vsamples
, fsamples
;
149 /* bitmask of samplers which need astc srgb workaround: */
150 uint16_t vastc_srgb
, fastc_srgb
;
154 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
156 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
157 if (a
->has_per_samp
|| b
->has_per_samp
)
158 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
159 return a
->global
== b
->global
;
162 /* will the two keys produce different lowering for a fragment shader? */
164 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
166 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
167 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
168 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
169 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
170 (last_key
->fsamples
!= key
->fsamples
) ||
171 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
175 if (last_key
->fclamp_color
!= key
->fclamp_color
)
178 if (last_key
->color_two_side
!= key
->color_two_side
)
181 if (last_key
->half_precision
!= key
->half_precision
)
184 if (last_key
->rasterflat
!= key
->rasterflat
)
187 if (last_key
->ucp_enables
!= key
->ucp_enables
)
193 /* will the two keys produce different lowering for a vertex shader? */
195 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
197 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
198 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
199 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
200 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
201 (last_key
->vsamples
!= key
->vsamples
) ||
202 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
206 if (last_key
->vclamp_color
!= key
->vclamp_color
)
209 if (last_key
->ucp_enables
!= key
->ucp_enables
)
215 struct ir3_shader_variant
{
218 /* variant id (for debug) */
221 struct ir3_shader_key key
;
223 struct ir3_driver_const_layout const_layout
;
224 struct ir3_info info
;
227 /* the instructions length is in units of instruction groups
228 * (4 instructions for a3xx, 16 instructions for a4xx.. each
229 * instruction is 2 dwords):
233 /* the constants length is in units of vec4's, and is the sum of
234 * the uniforms and the built-in compiler constants
238 /* number of uniforms (in vec4), not including built-in compiler
241 unsigned num_uniforms
;
246 * + Let the frag shader determine the position/compmask for the
247 * varyings, since it is the place where we know if the varying
248 * is actually used, and if so, which components are used. So
249 * what the hw calls "outloc" is taken from the "inloc" of the
251 * + From the vert shader, we only need the output regid
254 /* for frag shader, pos_regid holds the frag_vcoord, ie. what is passed
255 * to bary.f instructions
258 bool frag_coord
, frag_face
, color0_mrt
;
260 /* NOTE: for input/outputs, slot is:
261 * gl_vert_attrib - for VS inputs
262 * gl_varying_slot - for VS output / FS input
263 * gl_frag_result - for FS output
266 /* varyings/outputs: */
267 unsigned outputs_count
;
271 } outputs
[16 + 2]; /* +POSITION +PSIZE */
272 bool writes_pos
, writes_psize
;
274 /* attributes (VS) / varyings (FS):
275 * Note that sysval's should come *after* normal inputs.
277 unsigned inputs_count
;
283 /* location of input (ie. offset passed to bary.f, etc). This
284 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
285 * have the OUTLOCn value offset by 8, presumably to account
286 * for gl_Position/gl_PointSize)
289 /* vertex shader specific: */
290 bool sysval
: 1; /* slot is a gl_system_value */
291 /* fragment shader specific: */
292 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
293 bool rasterflat
: 1; /* special handling for emit->rasterflat */
294 enum glsl_interp_mode interpolate
;
295 } inputs
[16 + 2]; /* +POSITION +FACE */
297 /* sum of input components (scalar). For frag shaders, it only counts
298 * the varying inputs:
302 /* For frag shaders, the total number of inputs (not scalar,
303 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
307 /* do we have one or more texture sample instructions: */
310 /* do we have one or more SSBO instructions: */
313 /* do we have kill instructions: */
316 /* Layout of constant registers, each section (in vec4). Pointer size
317 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
318 * UBO and stream-out consts.
321 /* user const start at zero */
323 /* NOTE that a3xx might need a section for SSBO addresses too */
326 unsigned driver_param
;
331 unsigned immediates_count
;
336 /* for astc srgb workaround, the number/base of additional
337 * alpha tex states we need, and index of original tex states
340 unsigned base
, count
;
341 unsigned orig_idx
[16];
344 /* shader variants form a linked list: */
345 struct ir3_shader_variant
*next
;
347 /* replicated here to avoid passing extra ptrs everywhere: */
349 struct ir3_shader
*shader
;
352 typedef struct nir_shader nir_shader
;
357 /* shader id (for debug): */
359 uint32_t variant_count
;
361 /* so we know when we can disable TGSI related hacks: */
364 struct ir3_compiler
*compiler
;
367 struct pipe_stream_output_info stream_output
;
369 struct ir3_shader_variant
*variants
;
372 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
374 struct ir3_shader
* ir3_shader_create(struct ir3_compiler
*compiler
,
375 const struct pipe_shader_state
*cso
, enum shader_t type
,
376 struct pipe_debug_callback
*debug
);
378 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
379 const struct pipe_compute_state
*cso
,
380 struct pipe_debug_callback
*debug
);
381 void ir3_shader_destroy(struct ir3_shader
*shader
);
382 struct ir3_shader_variant
* ir3_shader_variant(struct ir3_shader
*shader
,
383 struct ir3_shader_key key
, struct pipe_debug_callback
*debug
);
384 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
385 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
387 struct fd_ringbuffer
;
389 void ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
390 struct fd_context
*ctx
, const struct pipe_draw_info
*info
);
391 void ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
392 struct fd_context
*ctx
);
393 void ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
394 struct fd_context
*ctx
, const struct pipe_grid_info
*info
);
397 ir3_glsl_type_size(const struct glsl_type
*type
);
399 static inline const char *
400 ir3_shader_stage(struct ir3_shader
*shader
)
402 switch (shader
->type
) {
403 case SHADER_VERTEX
: return "VERT";
404 case SHADER_FRAGMENT
: return "FRAG";
405 case SHADER_COMPUTE
: return "CL";
407 unreachable("invalid type");
416 #include "pipe/p_shader_tokens.h"
419 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
423 for (j
= 0; j
< so
->outputs_count
; j
++)
424 if (so
->outputs
[j
].slot
== slot
)
427 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
428 * in the vertex shader.. but the fragment shader doesn't know this
429 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
430 * at link time if there is no matching OUT.BCOLOR[n], we must map
431 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
432 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
434 if (slot
== VARYING_SLOT_BFC0
) {
435 slot
= VARYING_SLOT_COL0
;
436 } else if (slot
== VARYING_SLOT_BFC1
) {
437 slot
= VARYING_SLOT_COL1
;
438 } else if (slot
== VARYING_SLOT_COL0
) {
439 slot
= VARYING_SLOT_BFC0
;
440 } else if (slot
== VARYING_SLOT_COL1
) {
441 slot
= VARYING_SLOT_BFC1
;
446 for (j
= 0; j
< so
->outputs_count
; j
++)
447 if (so
->outputs
[j
].slot
== slot
)
456 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
458 while (++i
< so
->inputs_count
)
459 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
464 struct ir3_shader_linkage
{
475 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
479 debug_assert(i
< ARRAY_SIZE(l
->var
));
481 l
->var
[i
].regid
= regid
;
482 l
->var
[i
].compmask
= compmask
;
484 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
488 ir3_link_shaders(struct ir3_shader_linkage
*l
,
489 const struct ir3_shader_variant
*vs
,
490 const struct ir3_shader_variant
*fs
)
494 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
495 j
= ir3_next_varying(fs
, j
);
497 if (j
>= fs
->inputs_count
)
500 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
503 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
505 ir3_link_add(l
, vs
->outputs
[k
].regid
,
506 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
510 static inline uint32_t
511 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
514 for (j
= 0; j
< so
->outputs_count
; j
++)
515 if (so
->outputs
[j
].slot
== slot
)
516 return so
->outputs
[j
].regid
;
520 static inline uint32_t
521 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
524 for (j
= 0; j
< so
->inputs_count
; j
++)
525 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
526 return so
->inputs
[j
].regid
;
530 /* calculate register footprint in terms of half-regs (ie. one full
531 * reg counts as two half-regs).
533 static inline uint32_t
534 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
536 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
539 #endif /* IR3_SHADER_H_ */