2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
39 /* driver param indices: */
40 enum ir3_driver_param
{
41 /* compute shader driver params: */
42 IR3_DP_NUM_WORK_GROUPS_X
= 0,
43 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
44 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
45 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
46 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
47 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
48 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
49 * glDispatchComputeIndirect() needs to load these from
50 * the info->indirect buffer. Keep that in mind when/if
51 * adding any addition CS driver params.
53 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
55 /* vertex shader driver params: */
56 IR3_DP_VTXID_BASE
= 0,
57 IR3_DP_VTXCNT_MAX
= 1,
58 /* user-clip-plane components, up to 8x vec4's: */
62 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
66 * For consts needed to pass internal values to shader which may or may not
67 * be required, rather than allocating worst-case const space, we scan the
68 * shader and allocate consts as-needed:
70 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
73 * + Image dimensions: needed to calculate pixel offset, but only for
74 * images that have a image_store intrinsic
76 struct ir3_driver_const_layout
{
78 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
79 uint32_t count
; /* number of consts allocated */
80 /* one const allocated per SSBO which has get_buffer_size,
81 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
84 uint32_t off
[PIPE_MAX_SHADER_BUFFERS
];
88 uint32_t mask
; /* bitmask of images that have image_store */
89 uint32_t count
; /* number of consts allocated */
90 /* three const allocated per image which has image_store:
91 * + cpp (bytes per pixel)
93 * + array_pitch (z pitch)
95 uint32_t off
[PIPE_MAX_SHADER_IMAGES
];
99 /* Configuration key used to identify a shader variant.. different
100 * shader variants can be used to implement features not supported
101 * in hw (two sided color), binning-pass vertex shader, etc.
103 struct ir3_shader_key
{
107 * Combined Vertex/Fragment shader parameters:
109 unsigned ucp_enables
: 8;
111 /* do we need to check {v,f}saturate_{s,t,r}? */
112 unsigned has_per_samp
: 1;
115 * Vertex shader variant parameters:
117 unsigned binning_pass
: 1;
118 unsigned vclamp_color
: 1;
121 * Fragment shader variant parameters:
123 unsigned color_two_side
: 1;
124 unsigned half_precision
: 1;
125 /* used when shader needs to handle flat varyings (a4xx)
126 * for front/back color inputs to frag shader:
128 unsigned rasterflat
: 1;
129 unsigned fclamp_color
: 1;
134 /* bitmask of sampler which needs coords clamped for vertex
137 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
139 /* bitmask of sampler which needs coords clamped for frag
142 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
144 /* bitmask of ms shifts */
145 uint32_t vsamples
, fsamples
;
147 /* bitmask of samplers which need astc srgb workaround: */
148 uint16_t vastc_srgb
, fastc_srgb
;
152 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
154 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
155 if (a
->has_per_samp
|| b
->has_per_samp
)
156 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
157 return a
->global
== b
->global
;
160 /* will the two keys produce different lowering for a fragment shader? */
162 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
164 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
165 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
166 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
167 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
168 (last_key
->fsamples
!= key
->fsamples
) ||
169 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
173 if (last_key
->fclamp_color
!= key
->fclamp_color
)
176 if (last_key
->color_two_side
!= key
->color_two_side
)
179 if (last_key
->half_precision
!= key
->half_precision
)
182 if (last_key
->rasterflat
!= key
->rasterflat
)
185 if (last_key
->ucp_enables
!= key
->ucp_enables
)
191 /* will the two keys produce different lowering for a vertex shader? */
193 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
195 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
196 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
197 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
198 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
199 (last_key
->vsamples
!= key
->vsamples
) ||
200 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
204 if (last_key
->vclamp_color
!= key
->vclamp_color
)
207 if (last_key
->ucp_enables
!= key
->ucp_enables
)
213 struct ir3_shader_variant
{
216 /* variant id (for debug) */
219 struct ir3_shader_key key
;
221 struct ir3_driver_const_layout const_layout
;
222 struct ir3_info info
;
225 /* the instructions length is in units of instruction groups
226 * (4 instructions for a3xx, 16 instructions for a4xx.. each
227 * instruction is 2 dwords):
231 /* the constants length is in units of vec4's, and is the sum of
232 * the uniforms and the built-in compiler constants
236 /* number of uniforms (in vec4), not including built-in compiler
239 unsigned num_uniforms
;
244 * + Let the frag shader determine the position/compmask for the
245 * varyings, since it is the place where we know if the varying
246 * is actually used, and if so, which components are used. So
247 * what the hw calls "outloc" is taken from the "inloc" of the
249 * + From the vert shader, we only need the output regid
252 bool frag_coord
, frag_face
, color0_mrt
;
254 /* NOTE: for input/outputs, slot is:
255 * gl_vert_attrib - for VS inputs
256 * gl_varying_slot - for VS output / FS input
257 * gl_frag_result - for FS output
260 /* varyings/outputs: */
261 unsigned outputs_count
;
265 } outputs
[16 + 2]; /* +POSITION +PSIZE */
266 bool writes_pos
, writes_psize
;
268 /* attributes (VS) / varyings (FS):
269 * Note that sysval's should come *after* normal inputs.
271 unsigned inputs_count
;
277 /* location of input (ie. offset passed to bary.f, etc). This
278 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
279 * have the OUTLOCn value offset by 8, presumably to account
280 * for gl_Position/gl_PointSize)
283 /* vertex shader specific: */
284 bool sysval
: 1; /* slot is a gl_system_value */
285 /* fragment shader specific: */
286 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
287 bool rasterflat
: 1; /* special handling for emit->rasterflat */
288 enum glsl_interp_mode interpolate
;
289 } inputs
[16 + 2]; /* +POSITION +FACE */
291 /* sum of input components (scalar). For frag shaders, it only counts
292 * the varying inputs:
296 /* For frag shaders, the total number of inputs (not scalar,
297 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
301 /* do we have one or more texture sample instructions: */
304 /* do we have one or more SSBO instructions: */
307 /* do we have kill instructions: */
310 /* Layout of constant registers, each section (in vec4). Pointer size
311 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
312 * UBO and stream-out consts.
315 /* user const start at zero */
317 /* NOTE that a3xx might need a section for SSBO addresses too */
320 unsigned driver_param
;
325 unsigned immediates_count
;
326 unsigned immediates_size
;
331 /* for astc srgb workaround, the number/base of additional
332 * alpha tex states we need, and index of original tex states
335 unsigned base
, count
;
336 unsigned orig_idx
[16];
339 /* shader variants form a linked list: */
340 struct ir3_shader_variant
*next
;
342 /* replicated here to avoid passing extra ptrs everywhere: */
344 struct ir3_shader
*shader
;
350 /* shader id (for debug): */
352 uint32_t variant_count
;
354 /* so we know when we can disable TGSI related hacks: */
357 struct ir3_compiler
*compiler
;
359 struct nir_shader
*nir
;
360 struct pipe_stream_output_info stream_output
;
362 struct ir3_shader_variant
*variants
;
365 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
367 struct ir3_shader
* ir3_shader_create(struct ir3_compiler
*compiler
,
368 const struct pipe_shader_state
*cso
, enum shader_t type
,
369 struct pipe_debug_callback
*debug
);
371 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
372 const struct pipe_compute_state
*cso
,
373 struct pipe_debug_callback
*debug
);
374 void ir3_shader_destroy(struct ir3_shader
*shader
);
375 struct ir3_shader_variant
* ir3_shader_variant(struct ir3_shader
*shader
,
376 struct ir3_shader_key key
, struct pipe_debug_callback
*debug
);
377 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
378 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
380 struct fd_ringbuffer
;
382 void ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
383 struct fd_context
*ctx
, const struct pipe_draw_info
*info
);
384 void ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
385 struct fd_context
*ctx
);
386 void ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
387 struct fd_context
*ctx
, const struct pipe_grid_info
*info
);
390 ir3_glsl_type_size(const struct glsl_type
*type
);
392 static inline const char *
393 ir3_shader_stage(struct ir3_shader
*shader
)
395 switch (shader
->type
) {
396 case SHADER_VERTEX
: return "VERT";
397 case SHADER_FRAGMENT
: return "FRAG";
398 case SHADER_COMPUTE
: return "CL";
400 unreachable("invalid type");
409 #include "pipe/p_shader_tokens.h"
412 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
416 for (j
= 0; j
< so
->outputs_count
; j
++)
417 if (so
->outputs
[j
].slot
== slot
)
420 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
421 * in the vertex shader.. but the fragment shader doesn't know this
422 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
423 * at link time if there is no matching OUT.BCOLOR[n], we must map
424 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
425 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
427 if (slot
== VARYING_SLOT_BFC0
) {
428 slot
= VARYING_SLOT_COL0
;
429 } else if (slot
== VARYING_SLOT_BFC1
) {
430 slot
= VARYING_SLOT_COL1
;
431 } else if (slot
== VARYING_SLOT_COL0
) {
432 slot
= VARYING_SLOT_BFC0
;
433 } else if (slot
== VARYING_SLOT_COL1
) {
434 slot
= VARYING_SLOT_BFC1
;
439 for (j
= 0; j
< so
->outputs_count
; j
++)
440 if (so
->outputs
[j
].slot
== slot
)
449 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
451 while (++i
< so
->inputs_count
)
452 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
457 struct ir3_shader_linkage
{
468 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
472 debug_assert(i
< ARRAY_SIZE(l
->var
));
474 l
->var
[i
].regid
= regid
;
475 l
->var
[i
].compmask
= compmask
;
477 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
481 ir3_link_shaders(struct ir3_shader_linkage
*l
,
482 const struct ir3_shader_variant
*vs
,
483 const struct ir3_shader_variant
*fs
)
487 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
488 j
= ir3_next_varying(fs
, j
);
490 if (j
>= fs
->inputs_count
)
493 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
496 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
498 ir3_link_add(l
, vs
->outputs
[k
].regid
,
499 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
503 static inline uint32_t
504 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
507 for (j
= 0; j
< so
->outputs_count
; j
++)
508 if (so
->outputs
[j
].slot
== slot
)
509 return so
->outputs
[j
].regid
;
513 static inline uint32_t
514 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
517 for (j
= 0; j
< so
->inputs_count
; j
++)
518 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
519 return so
->inputs
[j
].regid
;
523 /* calculate register footprint in terms of half-regs (ie. one full
524 * reg counts as two half-regs).
526 static inline uint32_t
527 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
529 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
532 #endif /* IR3_SHADER_H_ */