src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "compiler/shader_enums.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37 #include "disasm.h"
  38
  39 /* driver param indices: */
  40 enum ir3_driver_param {
  41         IR3_DP_VTXID_BASE = 0,
  42         IR3_DP_VTXCNT_MAX = 1,
  43         /* user-clip-plane components, up to 8x vec4's: */
  44         IR3_DP_UCP0_X     = 4,
  45         /* .... */
  46         IR3_DP_UCP7_W     = 35,
  47         IR3_DP_COUNT      = 36   /* must be aligned to vec4 */
  48 };
  49
  50 /* Layout of constant registers:
  51  *
  52  *    num_uniform * vec4  -  user consts
  53  *    4 * vec4            -  UBO addresses
  54  *    if (vertex shader) {
  55  *        N * vec4        -  driver params (IR3_DP_*)
  56  *        1 * vec4        -  stream-out addresses
  57  *    }
  58  *
  59  * TODO this could be made more dynamic, to at least skip sections
  60  * that we don't need..
  61  */
  62 #define IR3_UBOS_OFF         0  /* UBOs after user consts */
  63 #define IR3_DRIVER_PARAM_OFF 4  /* driver params after UBOs */
  64 #define IR3_TFBOS_OFF       (IR3_DRIVER_PARAM_OFF + IR3_DP_COUNT/4)
  65
  66 /* Configuration key used to identify a shader variant.. different
  67  * shader variants can be used to implement features not supported
  68  * in hw (two sided color), binning-pass vertex shader, etc.
  69  */
  70 struct ir3_shader_key {
  71         union {
  72                 struct {
  73                         /*
  74                          * Combined Vertex/Fragment shader parameters:
  75                          */
  76                         unsigned ucp_enables : 8;
  77
  78                         /* do we need to check {v,f}saturate_{s,t,r}? */
  79                         unsigned has_per_samp : 1;
  80
  81                         /*
  82                          * Vertex shader variant parameters:
  83                          */
  84                         unsigned binning_pass : 1;
  85                         unsigned vclamp_color : 1;
  86
  87                         /*
  88                          * Fragment shader variant parameters:
  89                          */
  90                         unsigned color_two_side : 1;
  91                         unsigned half_precision : 1;
  92                         /* used when shader needs to handle flat varyings (a4xx)
  93                          * for front/back color inputs to frag shader:
  94                          */
  95                         unsigned rasterflat : 1;
  96                         unsigned fclamp_color : 1;
  97                 };
  98                 uint32_t global;
  99         };
 100
 101         /* bitmask of sampler which needs coords clamped for vertex
 102          * shader:
 103          */
 104         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
 105
 106         /* bitmask of sampler which needs coords clamped for frag
 107          * shader:
 108          */
 109         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 110
 111         /* bitmask of samplers which need astc srgb workaround: */
 112         uint16_t vastc_srgb, fastc_srgb;
 113 };
 114
 115 static inline bool
 116 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 117 {
 118         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 119         if (a->has_per_samp || b->has_per_samp)
 120                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 121         return a->global == b->global;
 122 }
 123
 124 struct ir3_shader_variant {
 125         struct fd_bo *bo;
 126
 127         /* variant id (for debug) */
 128         uint32_t id;
 129
 130         struct ir3_shader_key key;
 131
 132         struct ir3_info info;
 133         struct ir3 *ir;
 134
 135         /* the instructions length is in units of instruction groups
 136          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 137          * instruction is 2 dwords):
 138          */
 139         unsigned instrlen;
 140
 141         /* the constants length is in units of vec4's, and is the sum of
 142          * the uniforms and the built-in compiler constants
 143          */
 144         unsigned constlen;
 145
 146         /* About Linkage:
 147          *   + Let the frag shader determine the position/compmask for the
 148          *     varyings, since it is the place where we know if the varying
 149          *     is actually used, and if so, which components are used.  So
 150          *     what the hw calls "outloc" is taken from the "inloc" of the
 151          *     frag shader.
 152          *   + From the vert shader, we only need the output regid
 153          */
 154
 155         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 156          * to bary.f instructions
 157          */
 158         uint8_t pos_regid;
 159         bool frag_coord, frag_face, color0_mrt;
 160
 161         /* NOTE: for input/outputs, slot is:
 162          *   gl_vert_attrib  - for VS inputs
 163          *   gl_varying_slot - for VS output / FS input
 164          *   gl_frag_result  - for FS output
 165          */
 166
 167         /* varyings/outputs: */
 168         unsigned outputs_count;
 169         struct {
 170                 uint8_t slot;
 171                 uint8_t regid;
 172         } outputs[16 + 2];  /* +POSITION +PSIZE */
 173         bool writes_pos, writes_psize;
 174
 175         /* attributes (VS) / varyings (FS):
 176          * Note that sysval's should come *after* normal inputs.
 177          */
 178         unsigned inputs_count;
 179         struct {
 180                 uint8_t slot;
 181                 uint8_t regid;
 182                 uint8_t compmask;
 183                 uint8_t ncomp;
 184                 /* location of input (ie. offset passed to bary.f, etc).  This
 185                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 186                  * have the OUTLOCn value offset by 8, presumably to account
 187                  * for gl_Position/gl_PointSize)
 188                  */
 189                 uint8_t inloc;
 190                 /* vertex shader specific: */
 191                 bool    sysval     : 1;   /* slot is a gl_system_value */
 192                 /* fragment shader specific: */
 193                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 194                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 195                 enum glsl_interp_mode interpolate;
 196         } inputs[16 + 2];  /* +POSITION +FACE */
 197
 198         /* sum of input components (scalar).  For frag shaders, it only counts
 199          * the varying inputs:
 200          */
 201         unsigned total_in;
 202
 203         /* For frag shaders, the total number of inputs (not scalar,
 204          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 205          */
 206         unsigned varying_in;
 207
 208         /* do we have one or more texture sample instructions: */
 209         bool has_samp;
 210
 211         /* do we have kill instructions: */
 212         bool has_kill;
 213
 214         /* const reg # of first immediate, ie. 1 == c1
 215          * (not regid, because TGSI thinks in terms of vec4 registers,
 216          * not scalar registers)
 217          */
 218         unsigned first_driver_param;
 219         unsigned first_immediate;
 220         unsigned immediates_count;
 221         struct {
 222                 uint32_t val[4];
 223         } immediates[64];
 224
 225         /* for astc srgb workaround, the number/base of additional
 226          * alpha tex states we need, and index of original tex states
 227          */
 228         struct {
 229                 unsigned base, count;
 230                 unsigned orig_idx[16];
 231         } astc_srgb;
 232
 233         /* shader variants form a linked list: */
 234         struct ir3_shader_variant *next;
 235
 236         /* replicated here to avoid passing extra ptrs everywhere: */
 237         enum shader_t type;
 238         struct ir3_shader *shader;
 239 };
 240
 241 typedef struct nir_shader nir_shader;
 242
 243 struct ir3_shader {
 244         enum shader_t type;
 245
 246         /* shader id (for debug): */
 247         uint32_t id;
 248         uint32_t variant_count;
 249
 250         /* so we know when we can disable TGSI related hacks: */
 251         bool from_tgsi;
 252
 253         struct ir3_compiler *compiler;
 254
 255         nir_shader *nir;
 256         struct pipe_stream_output_info stream_output;
 257
 258         struct ir3_shader_variant *variants;
 259 };
 260
 261 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 262
 263 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 264                 const struct pipe_shader_state *cso, enum shader_t type,
 265                 struct pipe_debug_callback *debug);
 266 void ir3_shader_destroy(struct ir3_shader *shader);
 267 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 268                 struct ir3_shader_key key, struct pipe_debug_callback *debug);
 269 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 270 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 271
 272 struct fd_ringbuffer;
 273 struct fd_context;
 274 void ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 275                 struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t dirty);
 276
 277 static inline const char *
 278 ir3_shader_stage(struct ir3_shader *shader)
 279 {
 280         switch (shader->type) {
 281         case SHADER_VERTEX:     return "VERT";
 282         case SHADER_FRAGMENT:   return "FRAG";
 283         case SHADER_COMPUTE:    return "CL";
 284         default:
 285                 unreachable("invalid type");
 286                 return NULL;
 287         }
 288 }
 289
 290 /*
 291  * Helper/util:
 292  */
 293
 294 #include "pipe/p_shader_tokens.h"
 295
 296 static inline int
 297 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 298 {
 299         int j;
 300
 301         for (j = 0; j < so->outputs_count; j++)
 302                 if (so->outputs[j].slot == slot)
 303                         return j;
 304
 305         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 306          * in the vertex shader.. but the fragment shader doesn't know this
 307          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 308          * at link time if there is no matching OUT.BCOLOR[n], we must map
 309          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 310          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 311          */
 312         if (slot == VARYING_SLOT_BFC0) {
 313                 slot = VARYING_SLOT_COL0;
 314         } else if (slot == VARYING_SLOT_BFC1) {
 315                 slot = VARYING_SLOT_COL1;
 316         } else if (slot == VARYING_SLOT_COL0) {
 317                 slot = VARYING_SLOT_BFC0;
 318         } else if (slot == VARYING_SLOT_COL1) {
 319                 slot = VARYING_SLOT_BFC1;
 320         } else {
 321                 return 0;
 322         }
 323
 324         for (j = 0; j < so->outputs_count; j++)
 325                 if (so->outputs[j].slot == slot)
 326                         return j;
 327
 328         debug_assert(0);
 329
 330         return 0;
 331 }
 332
 333 static inline int
 334 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 335 {
 336         while (++i < so->inputs_count)
 337                 if (so->inputs[i].compmask && so->inputs[i].bary)
 338                         break;
 339         return i;
 340 }
 341
 342 struct ir3_shader_linkage {
 343         uint8_t max_loc;
 344         uint8_t cnt;
 345         struct {
 346                 uint8_t regid;
 347                 uint8_t compmask;
 348                 uint8_t loc;
 349         } var[16];
 350 };
 351
 352 static inline void
 353 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 354 {
 355         int i = l->cnt++;
 356
 357         debug_assert(i < ARRAY_SIZE(l->var));
 358
 359         l->var[i].regid    = regid;
 360         l->var[i].compmask = compmask;
 361         l->var[i].loc      = loc;
 362         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 363 }
 364
 365 static inline void
 366 ir3_link_shaders(struct ir3_shader_linkage *l,
 367                 const struct ir3_shader_variant *vs,
 368                 const struct ir3_shader_variant *fs)
 369 {
 370         int j = -1, k;
 371
 372         while (l->cnt < ARRAY_SIZE(l->var)) {
 373                 j = ir3_next_varying(fs, j);
 374
 375                 if (j >= fs->inputs_count)
 376                         break;
 377
 378                 if (fs->inputs[j].inloc >= fs->total_in)
 379                         continue;
 380
 381                 k = ir3_find_output(vs, fs->inputs[j].slot);
 382
 383                 ir3_link_add(l, vs->outputs[k].regid,
 384                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 385         }
 386 }
 387
 388 static inline uint32_t
 389 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 390 {
 391         int j;
 392         for (j = 0; j < so->outputs_count; j++)
 393                 if (so->outputs[j].slot == slot)
 394                         return so->outputs[j].regid;
 395         return regid(63, 0);
 396 }
 397
 398 #endif /* IR3_SHADER_H_ */