src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "compiler/shader_enums.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37 #include "disasm.h"
  38
  39 struct glsl_type;
  40
  41 /* driver param indices: */
  42 enum ir3_driver_param {
  43         /* compute shader driver params: */
  44         IR3_DP_NUM_WORK_GROUPS_X = 0,
  45         IR3_DP_NUM_WORK_GROUPS_Y = 1,
  46         IR3_DP_NUM_WORK_GROUPS_Z = 2,
  47         IR3_DP_CS_COUNT   = 4,   /* must be aligned to vec4 */
  48
  49         /* vertex shader driver params: */
  50         IR3_DP_VTXID_BASE = 0,
  51         IR3_DP_VTXCNT_MAX = 1,
  52         /* user-clip-plane components, up to 8x vec4's: */
  53         IR3_DP_UCP0_X     = 4,
  54         /* .... */
  55         IR3_DP_UCP7_W     = 35,
  56         IR3_DP_VS_COUNT   = 36   /* must be aligned to vec4 */
  57 };
  58
  59 /**
  60  * For consts needed to pass internal values to shader which may or may not
  61  * be required, rather than allocating worst-case const space, we scan the
  62  * shader and allocate consts as-needed:
  63  *
  64  *   + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
  65  *     for a given SSBO
  66  */
  67 struct ir3_driver_const_layout {
  68         struct {
  69                 uint32_t mask;  /* bitmask of SSBOs that have get_buffer_size */
  70                 uint32_t count; /* number of consts allocated */
  71                 /* one const allocated per SSBO which has get_buffer_size,
  72                  * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
  73                  * consts:
  74                  */
  75                 uint32_t off[PIPE_MAX_SHADER_BUFFERS];
  76         } ssbo_size;
  77 };
  78
  79 /* Configuration key used to identify a shader variant.. different
  80  * shader variants can be used to implement features not supported
  81  * in hw (two sided color), binning-pass vertex shader, etc.
  82  */
  83 struct ir3_shader_key {
  84         union {
  85                 struct {
  86                         /*
  87                          * Combined Vertex/Fragment shader parameters:
  88                          */
  89                         unsigned ucp_enables : 8;
  90
  91                         /* do we need to check {v,f}saturate_{s,t,r}? */
  92                         unsigned has_per_samp : 1;
  93
  94                         /*
  95                          * Vertex shader variant parameters:
  96                          */
  97                         unsigned binning_pass : 1;
  98                         unsigned vclamp_color : 1;
  99
 100                         /*
 101                          * Fragment shader variant parameters:
 102                          */
 103                         unsigned color_two_side : 1;
 104                         unsigned half_precision : 1;
 105                         /* used when shader needs to handle flat varyings (a4xx)
 106                          * for front/back color inputs to frag shader:
 107                          */
 108                         unsigned rasterflat : 1;
 109                         unsigned fclamp_color : 1;
 110                 };
 111                 uint32_t global;
 112         };
 113
 114         /* bitmask of sampler which needs coords clamped for vertex
 115          * shader:
 116          */
 117         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
 118
 119         /* bitmask of sampler which needs coords clamped for frag
 120          * shader:
 121          */
 122         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 123
 124         /* bitmask of samplers which need astc srgb workaround: */
 125         uint16_t vastc_srgb, fastc_srgb;
 126 };
 127
 128 static inline bool
 129 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 130 {
 131         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 132         if (a->has_per_samp || b->has_per_samp)
 133                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 134         return a->global == b->global;
 135 }
 136
 137 /* will the two keys produce different lowering for a fragment shader? */
 138 static inline bool
 139 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 140 {
 141         if (last_key->has_per_samp || key->has_per_samp) {
 142                 if ((last_key->fsaturate_s != key->fsaturate_s) ||
 143                                 (last_key->fsaturate_t != key->fsaturate_t) ||
 144                                 (last_key->fsaturate_r != key->fsaturate_r) ||
 145                                 (last_key->fastc_srgb != key->fastc_srgb))
 146                         return true;
 147         }
 148
 149         if (last_key->fclamp_color != key->fclamp_color)
 150                 return true;
 151
 152         if (last_key->color_two_side != key->color_two_side)
 153                 return true;
 154
 155         if (last_key->half_precision != key->half_precision)
 156                 return true;
 157
 158         if (last_key->rasterflat != key->rasterflat)
 159                 return true;
 160
 161         if (last_key->ucp_enables != key->ucp_enables)
 162                 return true;
 163
 164         return false;
 165 }
 166
 167 /* will the two keys produce different lowering for a vertex shader? */
 168 static inline bool
 169 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 170 {
 171         if (last_key->has_per_samp || key->has_per_samp) {
 172                 if ((last_key->vsaturate_s != key->vsaturate_s) ||
 173                                 (last_key->vsaturate_t != key->vsaturate_t) ||
 174                                 (last_key->vsaturate_r != key->vsaturate_r) ||
 175                                 (last_key->vastc_srgb != key->vastc_srgb))
 176                         return true;
 177         }
 178
 179         if (last_key->vclamp_color != key->vclamp_color)
 180                 return true;
 181
 182         if (last_key->ucp_enables != key->ucp_enables)
 183                 return true;
 184
 185         return false;
 186 }
 187
 188 struct ir3_shader_variant {
 189         struct fd_bo *bo;
 190
 191         /* variant id (for debug) */
 192         uint32_t id;
 193
 194         struct ir3_shader_key key;
 195
 196         struct ir3_driver_const_layout const_layout;
 197         struct ir3_info info;
 198         struct ir3 *ir;
 199
 200         /* the instructions length is in units of instruction groups
 201          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 202          * instruction is 2 dwords):
 203          */
 204         unsigned instrlen;
 205
 206         /* the constants length is in units of vec4's, and is the sum of
 207          * the uniforms and the built-in compiler constants
 208          */
 209         unsigned constlen;
 210
 211         /* number of uniforms (in vec4), not including built-in compiler
 212          * constants, etc.
 213          */
 214         unsigned num_uniforms;
 215
 216         unsigned num_ubos;
 217
 218         /* About Linkage:
 219          *   + Let the frag shader determine the position/compmask for the
 220          *     varyings, since it is the place where we know if the varying
 221          *     is actually used, and if so, which components are used.  So
 222          *     what the hw calls "outloc" is taken from the "inloc" of the
 223          *     frag shader.
 224          *   + From the vert shader, we only need the output regid
 225          */
 226
 227         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 228          * to bary.f instructions
 229          */
 230         uint8_t pos_regid;
 231         bool frag_coord, frag_face, color0_mrt;
 232
 233         /* NOTE: for input/outputs, slot is:
 234          *   gl_vert_attrib  - for VS inputs
 235          *   gl_varying_slot - for VS output / FS input
 236          *   gl_frag_result  - for FS output
 237          */
 238
 239         /* varyings/outputs: */
 240         unsigned outputs_count;
 241         struct {
 242                 uint8_t slot;
 243                 uint8_t regid;
 244         } outputs[16 + 2];  /* +POSITION +PSIZE */
 245         bool writes_pos, writes_psize;
 246
 247         /* attributes (VS) / varyings (FS):
 248          * Note that sysval's should come *after* normal inputs.
 249          */
 250         unsigned inputs_count;
 251         struct {
 252                 uint8_t slot;
 253                 uint8_t regid;
 254                 uint8_t compmask;
 255                 uint8_t ncomp;
 256                 /* location of input (ie. offset passed to bary.f, etc).  This
 257                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 258                  * have the OUTLOCn value offset by 8, presumably to account
 259                  * for gl_Position/gl_PointSize)
 260                  */
 261                 uint8_t inloc;
 262                 /* vertex shader specific: */
 263                 bool    sysval     : 1;   /* slot is a gl_system_value */
 264                 /* fragment shader specific: */
 265                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 266                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 267                 enum glsl_interp_mode interpolate;
 268         } inputs[16 + 2];  /* +POSITION +FACE */
 269
 270         /* sum of input components (scalar).  For frag shaders, it only counts
 271          * the varying inputs:
 272          */
 273         unsigned total_in;
 274
 275         /* For frag shaders, the total number of inputs (not scalar,
 276          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 277          */
 278         unsigned varying_in;
 279
 280         /* do we have one or more texture sample instructions: */
 281         bool has_samp;
 282
 283         /* do we have one or more SSBO instructions: */
 284         bool has_ssbo;
 285
 286         /* do we have kill instructions: */
 287         bool has_kill;
 288
 289         /* Layout of constant registers, each section (in vec4). Pointer size
 290          * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
 291          * UBO and stream-out consts.
 292          */
 293         struct {
 294                 /* user const start at zero */
 295                 unsigned ubo;
 296                 /* NOTE that a3xx might need a section for SSBO addresses too */
 297                 unsigned ssbo_sizes;
 298                 unsigned driver_param;
 299                 unsigned tfbo;
 300                 unsigned immediate;
 301         } constbase;
 302
 303         unsigned immediates_count;
 304         struct {
 305                 uint32_t val[4];
 306         } immediates[64];
 307
 308         /* for astc srgb workaround, the number/base of additional
 309          * alpha tex states we need, and index of original tex states
 310          */
 311         struct {
 312                 unsigned base, count;
 313                 unsigned orig_idx[16];
 314         } astc_srgb;
 315
 316         /* shader variants form a linked list: */
 317         struct ir3_shader_variant *next;
 318
 319         /* replicated here to avoid passing extra ptrs everywhere: */
 320         enum shader_t type;
 321         struct ir3_shader *shader;
 322 };
 323
 324 typedef struct nir_shader nir_shader;
 325
 326 struct ir3_shader {
 327         enum shader_t type;
 328
 329         /* shader id (for debug): */
 330         uint32_t id;
 331         uint32_t variant_count;
 332
 333         /* so we know when we can disable TGSI related hacks: */
 334         bool from_tgsi;
 335
 336         struct ir3_compiler *compiler;
 337
 338         nir_shader *nir;
 339         struct pipe_stream_output_info stream_output;
 340
 341         struct ir3_shader_variant *variants;
 342 };
 343
 344 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 345
 346 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 347                 const struct pipe_shader_state *cso, enum shader_t type,
 348                 struct pipe_debug_callback *debug);
 349 struct ir3_shader *
 350 ir3_shader_create_compute(struct ir3_compiler *compiler,
 351                 const struct pipe_compute_state *cso,
 352                 struct pipe_debug_callback *debug);
 353 void ir3_shader_destroy(struct ir3_shader *shader);
 354 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 355                 struct ir3_shader_key key, struct pipe_debug_callback *debug);
 356 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 357 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 358
 359 struct fd_ringbuffer;
 360 struct fd_context;
 361 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 362                 struct fd_context *ctx, const struct pipe_draw_info *info);
 363 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 364                 struct fd_context *ctx);
 365 void ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 366                 struct fd_context *ctx, const struct pipe_grid_info *info);
 367
 368 int
 369 ir3_glsl_type_size(const struct glsl_type *type);
 370
 371 static inline const char *
 372 ir3_shader_stage(struct ir3_shader *shader)
 373 {
 374         switch (shader->type) {
 375         case SHADER_VERTEX:     return "VERT";
 376         case SHADER_FRAGMENT:   return "FRAG";
 377         case SHADER_COMPUTE:    return "CL";
 378         default:
 379                 unreachable("invalid type");
 380                 return NULL;
 381         }
 382 }
 383
 384 /*
 385  * Helper/util:
 386  */
 387
 388 #include "pipe/p_shader_tokens.h"
 389
 390 static inline int
 391 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 392 {
 393         int j;
 394
 395         for (j = 0; j < so->outputs_count; j++)
 396                 if (so->outputs[j].slot == slot)
 397                         return j;
 398
 399         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 400          * in the vertex shader.. but the fragment shader doesn't know this
 401          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 402          * at link time if there is no matching OUT.BCOLOR[n], we must map
 403          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 404          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 405          */
 406         if (slot == VARYING_SLOT_BFC0) {
 407                 slot = VARYING_SLOT_COL0;
 408         } else if (slot == VARYING_SLOT_BFC1) {
 409                 slot = VARYING_SLOT_COL1;
 410         } else if (slot == VARYING_SLOT_COL0) {
 411                 slot = VARYING_SLOT_BFC0;
 412         } else if (slot == VARYING_SLOT_COL1) {
 413                 slot = VARYING_SLOT_BFC1;
 414         } else {
 415                 return 0;
 416         }
 417
 418         for (j = 0; j < so->outputs_count; j++)
 419                 if (so->outputs[j].slot == slot)
 420                         return j;
 421
 422         debug_assert(0);
 423
 424         return 0;
 425 }
 426
 427 static inline int
 428 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 429 {
 430         while (++i < so->inputs_count)
 431                 if (so->inputs[i].compmask && so->inputs[i].bary)
 432                         break;
 433         return i;
 434 }
 435
 436 struct ir3_shader_linkage {
 437         uint8_t max_loc;
 438         uint8_t cnt;
 439         struct {
 440                 uint8_t regid;
 441                 uint8_t compmask;
 442                 uint8_t loc;
 443         } var[32];
 444 };
 445
 446 static inline void
 447 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 448 {
 449         int i = l->cnt++;
 450
 451         debug_assert(i < ARRAY_SIZE(l->var));
 452
 453         l->var[i].regid    = regid;
 454         l->var[i].compmask = compmask;
 455         l->var[i].loc      = loc;
 456         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 457 }
 458
 459 static inline void
 460 ir3_link_shaders(struct ir3_shader_linkage *l,
 461                 const struct ir3_shader_variant *vs,
 462                 const struct ir3_shader_variant *fs)
 463 {
 464         int j = -1, k;
 465
 466         while (l->cnt < ARRAY_SIZE(l->var)) {
 467                 j = ir3_next_varying(fs, j);
 468
 469                 if (j >= fs->inputs_count)
 470                         break;
 471
 472                 if (fs->inputs[j].inloc >= fs->total_in)
 473                         continue;
 474
 475                 k = ir3_find_output(vs, fs->inputs[j].slot);
 476
 477                 ir3_link_add(l, vs->outputs[k].regid,
 478                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 479         }
 480 }
 481
 482 static inline uint32_t
 483 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 484 {
 485         int j;
 486         for (j = 0; j < so->outputs_count; j++)
 487                 if (so->outputs[j].slot == slot)
 488                         return so->outputs[j].regid;
 489         return regid(63, 0);
 490 }
 491
 492 static inline uint32_t
 493 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
 494 {
 495         int j;
 496         for (j = 0; j < so->inputs_count; j++)
 497                 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
 498                         return so->inputs[j].regid;
 499         return regid(63, 0);
 500 }
 501
 502 #endif /* IR3_SHADER_H_ */