2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "pipe/p_state.h"
33 #include "compiler/shader_enums.h"
34 #include "util/bitscan.h"
40 /* driver param indices: */
41 enum ir3_driver_param
{
42 /* compute shader driver params: */
43 IR3_DP_NUM_WORK_GROUPS_X
= 0,
44 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
45 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
46 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
47 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
48 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
49 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
50 * glDispatchComputeIndirect() needs to load these from
51 * the info->indirect buffer. Keep that in mind when/if
52 * adding any addition CS driver params.
54 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
56 /* vertex shader driver params: */
57 IR3_DP_VTXID_BASE
= 0,
58 IR3_DP_VTXCNT_MAX
= 1,
59 /* user-clip-plane components, up to 8x vec4's: */
63 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
66 #define IR3_MAX_SO_BUFFERS 4
67 #define IR3_MAX_SO_OUTPUTS 64
70 * For consts needed to pass internal values to shader which may or may not
71 * be required, rather than allocating worst-case const space, we scan the
72 * shader and allocate consts as-needed:
74 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
77 * + Image dimensions: needed to calculate pixel offset, but only for
78 * images that have a image_store intrinsic
80 struct ir3_driver_const_layout
{
82 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
83 uint32_t count
; /* number of consts allocated */
84 /* one const allocated per SSBO which has get_buffer_size,
85 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
88 uint32_t off
[PIPE_MAX_SHADER_BUFFERS
];
92 uint32_t mask
; /* bitmask of images that have image_store */
93 uint32_t count
; /* number of consts allocated */
94 /* three const allocated per image which has image_store:
95 * + cpp (bytes per pixel)
97 * + array_pitch (z pitch)
99 uint32_t off
[PIPE_MAX_SHADER_IMAGES
];
104 * A single output for vertex transform feedback.
106 struct ir3_stream_output
{
107 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
108 unsigned start_component
:2; /** 0 to 3 */
109 unsigned num_components
:3; /** 1 to 4 */
110 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
111 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
112 unsigned stream
:2; /**< 0 to 3 */
116 * Stream output for vertex transform feedback.
118 struct ir3_stream_output_info
{
119 unsigned num_outputs
;
120 /** stride for an entire vertex for each buffer in dwords */
121 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
124 * Array of stream outputs, in the order they are to be written in.
125 * Selected components are tightly packed into the output buffer.
127 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
130 /* Configuration key used to identify a shader variant.. different
131 * shader variants can be used to implement features not supported
132 * in hw (two sided color), binning-pass vertex shader, etc.
134 struct ir3_shader_key
{
138 * Combined Vertex/Fragment shader parameters:
140 unsigned ucp_enables
: 8;
142 /* do we need to check {v,f}saturate_{s,t,r}? */
143 unsigned has_per_samp
: 1;
146 * Vertex shader variant parameters:
148 unsigned vclamp_color
: 1;
151 * Fragment shader variant parameters:
153 unsigned color_two_side
: 1;
154 unsigned half_precision
: 1;
155 /* used when shader needs to handle flat varyings (a4xx)
156 * for front/back color inputs to frag shader:
158 unsigned rasterflat
: 1;
159 unsigned fclamp_color
: 1;
164 /* bitmask of sampler which needs coords clamped for vertex
167 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
169 /* bitmask of sampler which needs coords clamped for frag
172 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
174 /* bitmask of ms shifts */
175 uint32_t vsamples
, fsamples
;
177 /* bitmask of samplers which need astc srgb workaround: */
178 uint16_t vastc_srgb
, fastc_srgb
;
182 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
184 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
185 if (a
->has_per_samp
|| b
->has_per_samp
)
186 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
187 return a
->global
== b
->global
;
190 /* will the two keys produce different lowering for a fragment shader? */
192 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
194 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
195 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
196 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
197 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
198 (last_key
->fsamples
!= key
->fsamples
) ||
199 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
203 if (last_key
->fclamp_color
!= key
->fclamp_color
)
206 if (last_key
->color_two_side
!= key
->color_two_side
)
209 if (last_key
->half_precision
!= key
->half_precision
)
212 if (last_key
->rasterflat
!= key
->rasterflat
)
215 if (last_key
->ucp_enables
!= key
->ucp_enables
)
221 /* will the two keys produce different lowering for a vertex shader? */
223 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
225 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
226 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
227 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
228 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
229 (last_key
->vsamples
!= key
->vsamples
) ||
230 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
234 if (last_key
->vclamp_color
!= key
->vclamp_color
)
237 if (last_key
->ucp_enables
!= key
->ucp_enables
)
243 struct ir3_shader_variant
{
246 /* variant id (for debug) */
249 struct ir3_shader_key key
;
251 /* vertex shaders can have an extra version for hwbinning pass,
252 * which is pointed to by so->binning:
255 struct ir3_shader_variant
*binning
;
257 struct ir3_driver_const_layout const_layout
;
258 struct ir3_info info
;
261 /* the instructions length is in units of instruction groups
262 * (4 instructions for a3xx, 16 instructions for a4xx.. each
263 * instruction is 2 dwords):
267 /* the constants length is in units of vec4's, and is the sum of
268 * the uniforms and the built-in compiler constants
272 /* number of uniforms (in vec4), not including built-in compiler
275 unsigned num_uniforms
;
280 * + Let the frag shader determine the position/compmask for the
281 * varyings, since it is the place where we know if the varying
282 * is actually used, and if so, which components are used. So
283 * what the hw calls "outloc" is taken from the "inloc" of the
285 * + From the vert shader, we only need the output regid
288 bool frag_coord
, frag_face
, color0_mrt
;
290 /* NOTE: for input/outputs, slot is:
291 * gl_vert_attrib - for VS inputs
292 * gl_varying_slot - for VS output / FS input
293 * gl_frag_result - for FS output
296 /* varyings/outputs: */
297 unsigned outputs_count
;
301 } outputs
[16 + 2]; /* +POSITION +PSIZE */
302 bool writes_pos
, writes_psize
;
304 /* attributes (VS) / varyings (FS):
305 * Note that sysval's should come *after* normal inputs.
307 unsigned inputs_count
;
313 /* location of input (ie. offset passed to bary.f, etc). This
314 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
315 * have the OUTLOCn value offset by 8, presumably to account
316 * for gl_Position/gl_PointSize)
319 /* vertex shader specific: */
320 bool sysval
: 1; /* slot is a gl_system_value */
321 /* fragment shader specific: */
322 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
323 bool rasterflat
: 1; /* special handling for emit->rasterflat */
324 enum glsl_interp_mode interpolate
;
325 } inputs
[16 + 2]; /* +POSITION +FACE */
327 /* sum of input components (scalar). For frag shaders, it only counts
328 * the varying inputs:
332 /* For frag shaders, the total number of inputs (not scalar,
333 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
337 /* number of samplers/textures (which are currently 1:1): */
340 /* do we have one or more SSBO instructions: */
343 /* do we have kill instructions: */
346 /* Layout of constant registers, each section (in vec4). Pointer size
347 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
348 * UBO and stream-out consts.
351 /* user const start at zero */
353 /* NOTE that a3xx might need a section for SSBO addresses too */
356 unsigned driver_param
;
361 unsigned immediates_count
;
362 unsigned immediates_size
;
367 /* for astc srgb workaround, the number/base of additional
368 * alpha tex states we need, and index of original tex states
371 unsigned base
, count
;
372 unsigned orig_idx
[16];
375 /* shader variants form a linked list: */
376 struct ir3_shader_variant
*next
;
378 /* replicated here to avoid passing extra ptrs everywhere: */
379 gl_shader_stage type
;
380 struct ir3_shader
*shader
;
384 gl_shader_stage type
;
386 /* shader id (for debug): */
388 uint32_t variant_count
;
390 /* so we know when we can disable TGSI related hacks: */
393 struct ir3_compiler
*compiler
;
395 struct nir_shader
*nir
;
396 struct ir3_stream_output_info stream_output
;
398 struct ir3_shader_variant
*variants
;
401 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
403 struct ir3_shader
* ir3_shader_create(struct ir3_compiler
*compiler
,
404 const struct pipe_shader_state
*cso
, gl_shader_stage type
,
405 struct pipe_debug_callback
*debug
);
407 ir3_shader_create_compute(struct ir3_compiler
*compiler
,
408 const struct pipe_compute_state
*cso
,
409 struct pipe_debug_callback
*debug
);
410 void ir3_shader_destroy(struct ir3_shader
*shader
);
411 struct ir3_shader_variant
* ir3_shader_variant(struct ir3_shader
*shader
,
412 struct ir3_shader_key key
, bool binning_pass
,
413 struct pipe_debug_callback
*debug
);
414 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
415 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
417 struct fd_ringbuffer
;
419 void ir3_emit_vs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
420 struct fd_context
*ctx
, const struct pipe_draw_info
*info
);
421 void ir3_emit_fs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
422 struct fd_context
*ctx
);
423 void ir3_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
424 struct fd_context
*ctx
, const struct pipe_grid_info
*info
);
427 ir3_glsl_type_size(const struct glsl_type
*type
);
429 static inline const char *
430 ir3_shader_stage(struct ir3_shader
*shader
)
432 switch (shader
->type
) {
433 case MESA_SHADER_VERTEX
: return "VERT";
434 case MESA_SHADER_FRAGMENT
: return "FRAG";
435 case MESA_SHADER_COMPUTE
: return "CL";
437 unreachable("invalid type");
447 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
451 for (j
= 0; j
< so
->outputs_count
; j
++)
452 if (so
->outputs
[j
].slot
== slot
)
455 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
456 * in the vertex shader.. but the fragment shader doesn't know this
457 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
458 * at link time if there is no matching OUT.BCOLOR[n], we must map
459 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
460 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
462 if (slot
== VARYING_SLOT_BFC0
) {
463 slot
= VARYING_SLOT_COL0
;
464 } else if (slot
== VARYING_SLOT_BFC1
) {
465 slot
= VARYING_SLOT_COL1
;
466 } else if (slot
== VARYING_SLOT_COL0
) {
467 slot
= VARYING_SLOT_BFC0
;
468 } else if (slot
== VARYING_SLOT_COL1
) {
469 slot
= VARYING_SLOT_BFC1
;
474 for (j
= 0; j
< so
->outputs_count
; j
++)
475 if (so
->outputs
[j
].slot
== slot
)
484 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
486 while (++i
< so
->inputs_count
)
487 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
492 struct ir3_shader_linkage
{
503 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
507 debug_assert(i
< ARRAY_SIZE(l
->var
));
509 l
->var
[i
].regid
= regid
;
510 l
->var
[i
].compmask
= compmask
;
512 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
516 ir3_link_shaders(struct ir3_shader_linkage
*l
,
517 const struct ir3_shader_variant
*vs
,
518 const struct ir3_shader_variant
*fs
)
522 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
523 j
= ir3_next_varying(fs
, j
);
525 if (j
>= fs
->inputs_count
)
528 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
531 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
533 ir3_link_add(l
, vs
->outputs
[k
].regid
,
534 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
538 static inline uint32_t
539 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
542 for (j
= 0; j
< so
->outputs_count
; j
++)
543 if (so
->outputs
[j
].slot
== slot
)
544 return so
->outputs
[j
].regid
;
548 static inline uint32_t
549 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
552 for (j
= 0; j
< so
->inputs_count
; j
++)
553 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
554 return so
->inputs
[j
].regid
;
558 /* calculate register footprint in terms of half-regs (ie. one full
559 * reg counts as two half-regs).
561 static inline uint32_t
562 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
564 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
567 #endif /* IR3_SHADER_H_ */