src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "glsl/shader_enums.h"
  34
  35 #include "ir3.h"
  36 #include "disasm.h"
  37
  38 /* driver param indices: */
  39 enum ir3_driver_param {
  40         IR3_DP_VTXID_BASE = 0,
  41         IR3_DP_VTXCNT_MAX = 1,
  42         /* user-clip-plane components, up to 8x vec4's: */
  43         IR3_DP_UCP0_X     = 4,
  44         /* .... */
  45         IR3_DP_UCP7_W     = 35,
  46         IR3_DP_COUNT      = 36   /* must be aligned to vec4 */
  47 };
  48
  49 /* Layout of constant registers:
  50  *
  51  *    num_uniform * vec4  -  user consts
  52  *    4 * vec4            -  UBO addresses
  53  *    if (vertex shader) {
  54  *        N * vec4        -  driver params (IR3_DP_*)
  55  *        1 * vec4        -  stream-out addresses
  56  *    }
  57  *
  58  * TODO this could be made more dynamic, to at least skip sections
  59  * that we don't need..
  60  */
  61 #define IR3_UBOS_OFF         0  /* UBOs after user consts */
  62 #define IR3_DRIVER_PARAM_OFF 4  /* driver params after UBOs */
  63 #define IR3_TFBOS_OFF       (IR3_DRIVER_PARAM_OFF + IR3_DP_COUNT/4)
  64
  65 /* Configuration key used to identify a shader variant.. different
  66  * shader variants can be used to implement features not supported
  67  * in hw (two sided color), binning-pass vertex shader, etc.
  68  */
  69 struct ir3_shader_key {
  70         union {
  71                 struct {
  72                         /*
  73                          * Combined Vertex/Fragment shader parameters:
  74                          */
  75                         unsigned ucp_enables : 8;
  76
  77                         /* do we need to check {v,f}saturate_{s,t,r}? */
  78                         unsigned has_per_samp : 1;
  79
  80                         /*
  81                          * Vertex shader variant parameters:
  82                          */
  83                         unsigned binning_pass : 1;
  84
  85                         /*
  86                          * Fragment shader variant parameters:
  87                          */
  88                         unsigned color_two_side : 1;
  89                         unsigned half_precision : 1;
  90                         /* used when shader needs to handle flat varyings (a4xx)
  91                          * for front/back color inputs to frag shader:
  92                          */
  93                         unsigned rasterflat : 1;
  94                 };
  95                 uint32_t global;
  96         };
  97
  98         /* bitmask of sampler which needs coords clamped for vertex
  99          * shader:
 100          */
 101         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
 102
 103         /* bitmask of sampler which needs coords clamped for frag
 104          * shader:
 105          */
 106         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 107 };
 108
 109 static inline bool
 110 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 111 {
 112         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 113         if (a->has_per_samp || b->has_per_samp)
 114                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 115         return a->global == b->global;
 116 }
 117
 118 struct ir3_shader_variant {
 119         struct fd_bo *bo;
 120
 121         /* variant id (for debug) */
 122         uint32_t id;
 123
 124         struct ir3_shader_key key;
 125
 126         struct ir3_info info;
 127         struct ir3 *ir;
 128
 129         /* the instructions length is in units of instruction groups
 130          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 131          * instruction is 2 dwords):
 132          */
 133         unsigned instrlen;
 134
 135         /* the constants length is in units of vec4's, and is the sum of
 136          * the uniforms and the built-in compiler constants
 137          */
 138         unsigned constlen;
 139
 140         /* About Linkage:
 141          *   + Let the frag shader determine the position/compmask for the
 142          *     varyings, since it is the place where we know if the varying
 143          *     is actually used, and if so, which components are used.  So
 144          *     what the hw calls "outloc" is taken from the "inloc" of the
 145          *     frag shader.
 146          *   + From the vert shader, we only need the output regid
 147          */
 148
 149         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 150          * to bary.f instructions
 151          */
 152         uint8_t pos_regid;
 153         bool frag_coord, frag_face, color0_mrt;
 154
 155         /* NOTE: for input/outputs, slot is:
 156          *   gl_vert_attrib  - for VS inputs
 157          *   gl_varying_slot - for VS output / FS input
 158          *   gl_frag_result  - for FS output
 159          */
 160
 161         /* varyings/outputs: */
 162         unsigned outputs_count;
 163         struct {
 164                 uint8_t slot;
 165                 uint8_t regid;
 166         } outputs[16 + 2];  /* +POSITION +PSIZE */
 167         bool writes_pos, writes_psize;
 168
 169         /* vertices/inputs: */
 170         unsigned inputs_count;
 171         struct {
 172                 uint8_t slot;
 173                 uint8_t regid;
 174                 uint8_t compmask;
 175                 uint8_t ncomp;
 176                 /* In theory inloc of fs should match outloc of vs.  Or
 177                  * rather the outloc of the vs is 8 plus the offset passed
 178                  * to bary.f.  Presumably that +8 is to account for
 179                  * gl_Position/gl_PointSize?
 180                  *
 181                  * NOTE inloc is currently aligned to 4 (we don't try
 182                  * to pack varyings).  Changing this would likely break
 183                  * assumptions in few places (like setting up of flat
 184                  * shading in fd3_program) so be sure to check all the
 185                  * spots where inloc is used.
 186                  */
 187                 uint8_t inloc;
 188                 /* vertex shader specific: */
 189                 bool    sysval     : 1;   /* slot is a gl_system_value */
 190                 /* fragment shader specific: */
 191                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 192                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 193                 enum glsl_interp_qualifier interpolate;
 194         } inputs[16 + 2];  /* +POSITION +FACE */
 195
 196         unsigned total_in;       /* sum of inputs (scalar) */
 197
 198         /* do we have one or more texture sample instructions: */
 199         bool has_samp;
 200
 201         /* do we have kill instructions: */
 202         bool has_kill;
 203
 204         /* const reg # of first immediate, ie. 1 == c1
 205          * (not regid, because TGSI thinks in terms of vec4 registers,
 206          * not scalar registers)
 207          */
 208         unsigned first_driver_param;
 209         unsigned first_immediate;
 210         unsigned immediates_count;
 211         struct {
 212                 uint32_t val[4];
 213         } immediates[64];
 214
 215         /* shader variants form a linked list: */
 216         struct ir3_shader_variant *next;
 217
 218         /* replicated here to avoid passing extra ptrs everywhere: */
 219         enum shader_t type;
 220         struct ir3_shader *shader;
 221 };
 222
 223 struct ir3_shader {
 224         enum shader_t type;
 225
 226         /* shader id (for debug): */
 227         uint32_t id;
 228         uint32_t variant_count;
 229
 230         struct ir3_compiler *compiler;
 231
 232         struct pipe_context *pctx;
 233         const struct tgsi_token *tokens;
 234         struct pipe_stream_output_info stream_output;
 235
 236         struct ir3_shader_variant *variants;
 237 };
 238
 239 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 240
 241 struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
 242                 const struct pipe_shader_state *cso, enum shader_t type);
 243 void ir3_shader_destroy(struct ir3_shader *shader);
 244 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 245                 struct ir3_shader_key key);
 246 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 247
 248 struct fd_ringbuffer;
 249 void ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 250                 const struct pipe_draw_info *info, uint32_t dirty);
 251
 252 static inline const char *
 253 ir3_shader_stage(struct ir3_shader *shader)
 254 {
 255         switch (shader->type) {
 256         case SHADER_VERTEX:     return "VERT";
 257         case SHADER_FRAGMENT:   return "FRAG";
 258         case SHADER_COMPUTE:    return "CL";
 259         default:
 260                 unreachable("invalid type");
 261                 return NULL;
 262         }
 263 }
 264
 265 /*
 266  * Helper/util:
 267  */
 268
 269 #include "pipe/p_shader_tokens.h"
 270
 271 static inline int
 272 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 273 {
 274         int j;
 275
 276         for (j = 0; j < so->outputs_count; j++)
 277                 if (so->outputs[j].slot == slot)
 278                         return j;
 279
 280         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 281          * in the vertex shader.. but the fragment shader doesn't know this
 282          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 283          * at link time if there is no matching OUT.BCOLOR[n], we must map
 284          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 285          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 286          */
 287         if (slot == VARYING_SLOT_BFC0) {
 288                 slot = VARYING_SLOT_COL0;
 289         } else if (slot == VARYING_SLOT_BFC1) {
 290                 slot = VARYING_SLOT_COL1;
 291         } else if (slot == VARYING_SLOT_COL0) {
 292                 slot = VARYING_SLOT_BFC0;
 293         } else if (slot == VARYING_SLOT_COL1) {
 294                 slot = VARYING_SLOT_BFC1;
 295         } else {
 296                 return 0;
 297         }
 298
 299         for (j = 0; j < so->outputs_count; j++)
 300                 if (so->outputs[j].slot == slot)
 301                         return j;
 302
 303         debug_assert(0);
 304
 305         return 0;
 306 }
 307
 308 static inline int
 309 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 310 {
 311         while (++i < so->inputs_count)
 312                 if (so->inputs[i].compmask && so->inputs[i].bary)
 313                         break;
 314         return i;
 315 }
 316
 317 static inline uint32_t
 318 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 319 {
 320         int j;
 321         for (j = 0; j < so->outputs_count; j++)
 322                 if (so->outputs[j].slot == slot)
 323                         return so->outputs[j].regid;
 324         return regid(63, 0);
 325 }
 326
 327 #endif /* IR3_SHADER_H_ */