src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "compiler/shader_enums.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37 #include "disasm.h"
  38
  39 /* driver param indices: */
  40 enum ir3_driver_param {
  41         /* compute shader driver params: */
  42         IR3_DP_NUM_WORK_GROUPS_X = 0,
  43         IR3_DP_NUM_WORK_GROUPS_Y = 1,
  44         IR3_DP_NUM_WORK_GROUPS_Z = 2,
  45         IR3_DP_CS_COUNT   = 4,   /* must be aligned to vec4 */
  46
  47         /* vertex shader driver params: */
  48         IR3_DP_VTXID_BASE = 0,
  49         IR3_DP_VTXCNT_MAX = 1,
  50         /* user-clip-plane components, up to 8x vec4's: */
  51         IR3_DP_UCP0_X     = 4,
  52         /* .... */
  53         IR3_DP_UCP7_W     = 35,
  54         IR3_DP_VS_COUNT   = 36   /* must be aligned to vec4 */
  55 };
  56
  57 /* Configuration key used to identify a shader variant.. different
  58  * shader variants can be used to implement features not supported
  59  * in hw (two sided color), binning-pass vertex shader, etc.
  60  */
  61 struct ir3_shader_key {
  62         union {
  63                 struct {
  64                         /*
  65                          * Combined Vertex/Fragment shader parameters:
  66                          */
  67                         unsigned ucp_enables : 8;
  68
  69                         /* do we need to check {v,f}saturate_{s,t,r}? */
  70                         unsigned has_per_samp : 1;
  71
  72                         /*
  73                          * Vertex shader variant parameters:
  74                          */
  75                         unsigned binning_pass : 1;
  76                         unsigned vclamp_color : 1;
  77
  78                         /*
  79                          * Fragment shader variant parameters:
  80                          */
  81                         unsigned color_two_side : 1;
  82                         unsigned half_precision : 1;
  83                         /* used when shader needs to handle flat varyings (a4xx)
  84                          * for front/back color inputs to frag shader:
  85                          */
  86                         unsigned rasterflat : 1;
  87                         unsigned fclamp_color : 1;
  88                 };
  89                 uint32_t global;
  90         };
  91
  92         /* bitmask of sampler which needs coords clamped for vertex
  93          * shader:
  94          */
  95         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
  96
  97         /* bitmask of sampler which needs coords clamped for frag
  98          * shader:
  99          */
 100         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 101
 102         /* bitmask of samplers which need astc srgb workaround: */
 103         uint16_t vastc_srgb, fastc_srgb;
 104 };
 105
 106 static inline bool
 107 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 108 {
 109         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 110         if (a->has_per_samp || b->has_per_samp)
 111                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 112         return a->global == b->global;
 113 }
 114
 115 /* will the two keys produce different lowering for a fragment shader? */
 116 static inline bool
 117 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 118 {
 119         if (last_key->has_per_samp || key->has_per_samp) {
 120                 if ((last_key->fsaturate_s != key->fsaturate_s) ||
 121                                 (last_key->fsaturate_t != key->fsaturate_t) ||
 122                                 (last_key->fsaturate_r != key->fsaturate_r) ||
 123                                 (last_key->fastc_srgb != key->fastc_srgb))
 124                         return true;
 125         }
 126
 127         if (last_key->fclamp_color != key->fclamp_color)
 128                 return true;
 129
 130         if (last_key->color_two_side != key->color_two_side)
 131                 return true;
 132
 133         if (last_key->half_precision != key->half_precision)
 134                 return true;
 135
 136         if (last_key->rasterflat != key->rasterflat)
 137                 return true;
 138
 139         if (last_key->ucp_enables != key->ucp_enables)
 140                 return true;
 141
 142         return false;
 143 }
 144
 145 /* will the two keys produce different lowering for a vertex shader? */
 146 static inline bool
 147 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 148 {
 149         if (last_key->has_per_samp || key->has_per_samp) {
 150                 if ((last_key->vsaturate_s != key->vsaturate_s) ||
 151                                 (last_key->vsaturate_t != key->vsaturate_t) ||
 152                                 (last_key->vsaturate_r != key->vsaturate_r) ||
 153                                 (last_key->vastc_srgb != key->vastc_srgb))
 154                         return true;
 155         }
 156
 157         if (last_key->vclamp_color != key->vclamp_color)
 158                 return true;
 159
 160         if (last_key->ucp_enables != key->ucp_enables)
 161                 return true;
 162
 163         return false;
 164 }
 165
 166 struct ir3_shader_variant {
 167         struct fd_bo *bo;
 168
 169         /* variant id (for debug) */
 170         uint32_t id;
 171
 172         struct ir3_shader_key key;
 173
 174         struct ir3_info info;
 175         struct ir3 *ir;
 176
 177         /* the instructions length is in units of instruction groups
 178          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 179          * instruction is 2 dwords):
 180          */
 181         unsigned instrlen;
 182
 183         /* the constants length is in units of vec4's, and is the sum of
 184          * the uniforms and the built-in compiler constants
 185          */
 186         unsigned constlen;
 187
 188         /* number of uniforms (in vec4), not including built-in compiler
 189          * constants, etc.
 190          */
 191         unsigned num_uniforms;
 192         unsigned num_ubos;
 193
 194         /* About Linkage:
 195          *   + Let the frag shader determine the position/compmask for the
 196          *     varyings, since it is the place where we know if the varying
 197          *     is actually used, and if so, which components are used.  So
 198          *     what the hw calls "outloc" is taken from the "inloc" of the
 199          *     frag shader.
 200          *   + From the vert shader, we only need the output regid
 201          */
 202
 203         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 204          * to bary.f instructions
 205          */
 206         uint8_t pos_regid;
 207         bool frag_coord, frag_face, color0_mrt;
 208
 209         /* NOTE: for input/outputs, slot is:
 210          *   gl_vert_attrib  - for VS inputs
 211          *   gl_varying_slot - for VS output / FS input
 212          *   gl_frag_result  - for FS output
 213          */
 214
 215         /* varyings/outputs: */
 216         unsigned outputs_count;
 217         struct {
 218                 uint8_t slot;
 219                 uint8_t regid;
 220         } outputs[16 + 2];  /* +POSITION +PSIZE */
 221         bool writes_pos, writes_psize;
 222
 223         /* attributes (VS) / varyings (FS):
 224          * Note that sysval's should come *after* normal inputs.
 225          */
 226         unsigned inputs_count;
 227         struct {
 228                 uint8_t slot;
 229                 uint8_t regid;
 230                 uint8_t compmask;
 231                 uint8_t ncomp;
 232                 /* location of input (ie. offset passed to bary.f, etc).  This
 233                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 234                  * have the OUTLOCn value offset by 8, presumably to account
 235                  * for gl_Position/gl_PointSize)
 236                  */
 237                 uint8_t inloc;
 238                 /* vertex shader specific: */
 239                 bool    sysval     : 1;   /* slot is a gl_system_value */
 240                 /* fragment shader specific: */
 241                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 242                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 243                 enum glsl_interp_mode interpolate;
 244         } inputs[16 + 2];  /* +POSITION +FACE */
 245
 246         /* sum of input components (scalar).  For frag shaders, it only counts
 247          * the varying inputs:
 248          */
 249         unsigned total_in;
 250
 251         /* For frag shaders, the total number of inputs (not scalar,
 252          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 253          */
 254         unsigned varying_in;
 255
 256         /* do we have one or more texture sample instructions: */
 257         bool has_samp;
 258
 259         /* do we have one or more SSBO instructions: */
 260         bool has_ssbo;
 261
 262         /* do we have kill instructions: */
 263         bool has_kill;
 264
 265         /* Layout of constant registers, each section (in vec4). Pointer size
 266          * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
 267          * UBO and stream-out consts.
 268          */
 269         struct {
 270                 /* user const start at zero */
 271                 unsigned ubo;
 272                 unsigned driver_param;
 273                 unsigned tfbo;
 274                 unsigned immediate;
 275         } constbase;
 276
 277         unsigned immediates_count;
 278         struct {
 279                 uint32_t val[4];
 280         } immediates[64];
 281
 282         /* for astc srgb workaround, the number/base of additional
 283          * alpha tex states we need, and index of original tex states
 284          */
 285         struct {
 286                 unsigned base, count;
 287                 unsigned orig_idx[16];
 288         } astc_srgb;
 289
 290         /* shader variants form a linked list: */
 291         struct ir3_shader_variant *next;
 292
 293         /* replicated here to avoid passing extra ptrs everywhere: */
 294         enum shader_t type;
 295         struct ir3_shader *shader;
 296 };
 297
 298 typedef struct nir_shader nir_shader;
 299
 300 struct ir3_shader {
 301         enum shader_t type;
 302
 303         /* shader id (for debug): */
 304         uint32_t id;
 305         uint32_t variant_count;
 306
 307         /* so we know when we can disable TGSI related hacks: */
 308         bool from_tgsi;
 309
 310         struct ir3_compiler *compiler;
 311
 312         nir_shader *nir;
 313         struct pipe_stream_output_info stream_output;
 314
 315         struct ir3_shader_variant *variants;
 316 };
 317
 318 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 319
 320 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 321                 const struct pipe_shader_state *cso, enum shader_t type,
 322                 struct pipe_debug_callback *debug);
 323 struct ir3_shader *
 324 ir3_shader_create_compute(struct ir3_compiler *compiler,
 325                 const struct pipe_compute_state *cso,
 326                 struct pipe_debug_callback *debug);
 327 void ir3_shader_destroy(struct ir3_shader *shader);
 328 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 329                 struct ir3_shader_key key, struct pipe_debug_callback *debug);
 330 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 331 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 332
 333 struct fd_ringbuffer;
 334 struct fd_context;
 335 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 336                 struct fd_context *ctx, const struct pipe_draw_info *info);
 337 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 338                 struct fd_context *ctx);
 339 void ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 340                 struct fd_context *ctx, const struct pipe_grid_info *info);
 341
 342 static inline const char *
 343 ir3_shader_stage(struct ir3_shader *shader)
 344 {
 345         switch (shader->type) {
 346         case SHADER_VERTEX:     return "VERT";
 347         case SHADER_FRAGMENT:   return "FRAG";
 348         case SHADER_COMPUTE:    return "CL";
 349         default:
 350                 unreachable("invalid type");
 351                 return NULL;
 352         }
 353 }
 354
 355 /*
 356  * Helper/util:
 357  */
 358
 359 #include "pipe/p_shader_tokens.h"
 360
 361 static inline int
 362 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 363 {
 364         int j;
 365
 366         for (j = 0; j < so->outputs_count; j++)
 367                 if (so->outputs[j].slot == slot)
 368                         return j;
 369
 370         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 371          * in the vertex shader.. but the fragment shader doesn't know this
 372          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 373          * at link time if there is no matching OUT.BCOLOR[n], we must map
 374          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 375          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 376          */
 377         if (slot == VARYING_SLOT_BFC0) {
 378                 slot = VARYING_SLOT_COL0;
 379         } else if (slot == VARYING_SLOT_BFC1) {
 380                 slot = VARYING_SLOT_COL1;
 381         } else if (slot == VARYING_SLOT_COL0) {
 382                 slot = VARYING_SLOT_BFC0;
 383         } else if (slot == VARYING_SLOT_COL1) {
 384                 slot = VARYING_SLOT_BFC1;
 385         } else {
 386                 return 0;
 387         }
 388
 389         for (j = 0; j < so->outputs_count; j++)
 390                 if (so->outputs[j].slot == slot)
 391                         return j;
 392
 393         debug_assert(0);
 394
 395         return 0;
 396 }
 397
 398 static inline int
 399 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 400 {
 401         while (++i < so->inputs_count)
 402                 if (so->inputs[i].compmask && so->inputs[i].bary)
 403                         break;
 404         return i;
 405 }
 406
 407 struct ir3_shader_linkage {
 408         uint8_t max_loc;
 409         uint8_t cnt;
 410         struct {
 411                 uint8_t regid;
 412                 uint8_t compmask;
 413                 uint8_t loc;
 414         } var[32];
 415 };
 416
 417 static inline void
 418 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 419 {
 420         int i = l->cnt++;
 421
 422         debug_assert(i < ARRAY_SIZE(l->var));
 423
 424         l->var[i].regid    = regid;
 425         l->var[i].compmask = compmask;
 426         l->var[i].loc      = loc;
 427         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 428 }
 429
 430 static inline void
 431 ir3_link_shaders(struct ir3_shader_linkage *l,
 432                 const struct ir3_shader_variant *vs,
 433                 const struct ir3_shader_variant *fs)
 434 {
 435         int j = -1, k;
 436
 437         while (l->cnt < ARRAY_SIZE(l->var)) {
 438                 j = ir3_next_varying(fs, j);
 439
 440                 if (j >= fs->inputs_count)
 441                         break;
 442
 443                 if (fs->inputs[j].inloc >= fs->total_in)
 444                         continue;
 445
 446                 k = ir3_find_output(vs, fs->inputs[j].slot);
 447
 448                 ir3_link_add(l, vs->outputs[k].regid,
 449                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 450         }
 451 }
 452
 453 static inline uint32_t
 454 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 455 {
 456         int j;
 457         for (j = 0; j < so->outputs_count; j++)
 458                 if (so->outputs[j].slot == slot)
 459                         return so->outputs[j].regid;
 460         return regid(63, 0);
 461 }
 462
 463 static inline uint32_t
 464 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
 465 {
 466         int j;
 467         for (j = 0; j < so->inputs_count; j++)
 468                 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
 469                         return so->inputs[j].regid;
 470         return regid(63, 0);
 471 }
 472
 473 #endif /* IR3_SHADER_H_ */