1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
32 #include "pipe/p_state.h"
33 #include "compiler/shader_enums.h"
38 /* driver param indices: */
39 enum ir3_driver_param
{
40 IR3_DP_VTXID_BASE
= 0,
41 IR3_DP_VTXCNT_MAX
= 1,
42 /* user-clip-plane components, up to 8x vec4's: */
46 IR3_DP_COUNT
= 36 /* must be aligned to vec4 */
49 /* Layout of constant registers:
51 * num_uniform * vec4 - user consts
52 * 4 * vec4 - UBO addresses
53 * if (vertex shader) {
54 * N * vec4 - driver params (IR3_DP_*)
55 * 1 * vec4 - stream-out addresses
58 * TODO this could be made more dynamic, to at least skip sections
59 * that we don't need..
61 #define IR3_UBOS_OFF 0 /* UBOs after user consts */
62 #define IR3_DRIVER_PARAM_OFF 4 /* driver params after UBOs */
63 #define IR3_TFBOS_OFF (IR3_DRIVER_PARAM_OFF + IR3_DP_COUNT/4)
65 /* Configuration key used to identify a shader variant.. different
66 * shader variants can be used to implement features not supported
67 * in hw (two sided color), binning-pass vertex shader, etc.
69 struct ir3_shader_key
{
73 * Combined Vertex/Fragment shader parameters:
75 unsigned ucp_enables
: 8;
77 /* do we need to check {v,f}saturate_{s,t,r}? */
78 unsigned has_per_samp
: 1;
81 * Vertex shader variant parameters:
83 unsigned binning_pass
: 1;
84 unsigned vclamp_color
: 1;
87 * Fragment shader variant parameters:
89 unsigned color_two_side
: 1;
90 unsigned half_precision
: 1;
91 /* used when shader needs to handle flat varyings (a4xx)
92 * for front/back color inputs to frag shader:
94 unsigned rasterflat
: 1;
95 unsigned fclamp_color
: 1;
100 /* bitmask of sampler which needs coords clamped for vertex
103 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
105 /* bitmask of sampler which needs coords clamped for frag
108 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
110 /* bitmask of samplers which need astc srgb workaround: */
111 uint16_t vastc_srgb
, fastc_srgb
;
115 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
117 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
118 if (a
->has_per_samp
|| b
->has_per_samp
)
119 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
120 return a
->global
== b
->global
;
123 struct ir3_shader_variant
{
126 /* variant id (for debug) */
129 struct ir3_shader_key key
;
131 struct ir3_info info
;
134 /* the instructions length is in units of instruction groups
135 * (4 instructions for a3xx, 16 instructions for a4xx.. each
136 * instruction is 2 dwords):
140 /* the constants length is in units of vec4's, and is the sum of
141 * the uniforms and the built-in compiler constants
146 * + Let the frag shader determine the position/compmask for the
147 * varyings, since it is the place where we know if the varying
148 * is actually used, and if so, which components are used. So
149 * what the hw calls "outloc" is taken from the "inloc" of the
151 * + From the vert shader, we only need the output regid
154 /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
155 * to bary.f instructions
158 bool frag_coord
, frag_face
, color0_mrt
;
160 /* NOTE: for input/outputs, slot is:
161 * gl_vert_attrib - for VS inputs
162 * gl_varying_slot - for VS output / FS input
163 * gl_frag_result - for FS output
166 /* varyings/outputs: */
167 unsigned outputs_count
;
171 } outputs
[16 + 2]; /* +POSITION +PSIZE */
172 bool writes_pos
, writes_psize
;
174 /* attributes (VS) / varyings (FS):
175 * Note that sysval's should come *after* normal inputs.
177 unsigned inputs_count
;
183 /* In theory inloc of fs should match outloc of vs. Or
184 * rather the outloc of the vs is 8 plus the offset passed
185 * to bary.f. Presumably that +8 is to account for
186 * gl_Position/gl_PointSize?
188 * NOTE inloc is currently aligned to 4 (we don't try
189 * to pack varyings). Changing this would likely break
190 * assumptions in few places (like setting up of flat
191 * shading in fd3_program) so be sure to check all the
192 * spots where inloc is used.
195 /* vertex shader specific: */
196 bool sysval
: 1; /* slot is a gl_system_value */
197 /* fragment shader specific: */
198 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
199 bool rasterflat
: 1; /* special handling for emit->rasterflat */
200 enum glsl_interp_qualifier interpolate
;
201 } inputs
[16 + 2]; /* +POSITION +FACE */
203 /* sum of input components (scalar). For frag shaders, it only counts
204 * the varying inputs:
208 /* For frag shaders, the total number of inputs (not scalar,
209 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
213 /* do we have one or more texture sample instructions: */
216 /* do we have kill instructions: */
219 /* const reg # of first immediate, ie. 1 == c1
220 * (not regid, because TGSI thinks in terms of vec4 registers,
221 * not scalar registers)
223 unsigned first_driver_param
;
224 unsigned first_immediate
;
225 unsigned immediates_count
;
230 /* for astc srgb workaround, the number/base of additional
231 * alpha tex states we need, and index of original tex states
234 unsigned base
, count
;
235 unsigned orig_idx
[16];
238 /* shader variants form a linked list: */
239 struct ir3_shader_variant
*next
;
241 /* replicated here to avoid passing extra ptrs everywhere: */
243 struct ir3_shader
*shader
;
246 typedef struct nir_shader nir_shader
;
251 /* shader id (for debug): */
253 uint32_t variant_count
;
255 /* so we know when we can disable TGSI related hacks: */
258 struct ir3_compiler
*compiler
;
261 struct pipe_stream_output_info stream_output
;
263 struct ir3_shader_variant
*variants
;
266 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
268 struct ir3_shader
* ir3_shader_create(struct ir3_compiler
*compiler
,
269 const struct pipe_shader_state
*cso
, enum shader_t type
,
270 struct pipe_debug_callback
*debug
);
271 void ir3_shader_destroy(struct ir3_shader
*shader
);
272 struct ir3_shader_variant
* ir3_shader_variant(struct ir3_shader
*shader
,
273 struct ir3_shader_key key
, struct pipe_debug_callback
*debug
);
274 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
);
276 struct fd_ringbuffer
;
278 void ir3_emit_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
279 struct fd_context
*ctx
, const struct pipe_draw_info
*info
, uint32_t dirty
);
281 static inline const char *
282 ir3_shader_stage(struct ir3_shader
*shader
)
284 switch (shader
->type
) {
285 case SHADER_VERTEX
: return "VERT";
286 case SHADER_FRAGMENT
: return "FRAG";
287 case SHADER_COMPUTE
: return "CL";
289 unreachable("invalid type");
298 #include "pipe/p_shader_tokens.h"
301 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
305 for (j
= 0; j
< so
->outputs_count
; j
++)
306 if (so
->outputs
[j
].slot
== slot
)
309 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
310 * in the vertex shader.. but the fragment shader doesn't know this
311 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
312 * at link time if there is no matching OUT.BCOLOR[n], we must map
313 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
314 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
316 if (slot
== VARYING_SLOT_BFC0
) {
317 slot
= VARYING_SLOT_COL0
;
318 } else if (slot
== VARYING_SLOT_BFC1
) {
319 slot
= VARYING_SLOT_COL1
;
320 } else if (slot
== VARYING_SLOT_COL0
) {
321 slot
= VARYING_SLOT_BFC0
;
322 } else if (slot
== VARYING_SLOT_COL1
) {
323 slot
= VARYING_SLOT_BFC1
;
328 for (j
= 0; j
< so
->outputs_count
; j
++)
329 if (so
->outputs
[j
].slot
== slot
)
338 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
340 while (++i
< so
->inputs_count
)
341 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
346 static inline uint32_t
347 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
350 for (j
= 0; j
< so
->outputs_count
; j
++)
351 if (so
->outputs
[j
].slot
== slot
)
352 return so
->outputs
[j
].regid
;
356 #endif /* IR3_SHADER_H_ */