src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "compiler/shader_enums.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37 #include "disasm.h"
  38
  39 struct glsl_type;
  40
  41 /* driver param indices: */
  42 enum ir3_driver_param {
  43         /* compute shader driver params: */
  44         IR3_DP_NUM_WORK_GROUPS_X = 0,
  45         IR3_DP_NUM_WORK_GROUPS_Y = 1,
  46         IR3_DP_NUM_WORK_GROUPS_Z = 2,
  47         IR3_DP_LOCAL_GROUP_SIZE_X = 4,
  48         IR3_DP_LOCAL_GROUP_SIZE_Y = 5,
  49         IR3_DP_LOCAL_GROUP_SIZE_Z = 6,
  50         /* NOTE: gl_NumWorkGroups should be vec4 aligned because
  51          * glDispatchComputeIndirect() needs to load these from
  52          * the info->indirect buffer.  Keep that in mind when/if
  53          * adding any addition CS driver params.
  54          */
  55         IR3_DP_CS_COUNT   = 8,   /* must be aligned to vec4 */
  56
  57         /* vertex shader driver params: */
  58         IR3_DP_VTXID_BASE = 0,
  59         IR3_DP_VTXCNT_MAX = 1,
  60         /* user-clip-plane components, up to 8x vec4's: */
  61         IR3_DP_UCP0_X     = 4,
  62         /* .... */
  63         IR3_DP_UCP7_W     = 35,
  64         IR3_DP_VS_COUNT   = 36   /* must be aligned to vec4 */
  65 };
  66
  67 /**
  68  * For consts needed to pass internal values to shader which may or may not
  69  * be required, rather than allocating worst-case const space, we scan the
  70  * shader and allocate consts as-needed:
  71  *
  72  *   + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
  73  *     for a given SSBO
  74  *
  75  *   + Image dimensions: needed to calculate pixel offset, but only for
  76  *     images that have a image_store intrinsic
  77  */
  78 struct ir3_driver_const_layout {
  79         struct {
  80                 uint32_t mask;  /* bitmask of SSBOs that have get_buffer_size */
  81                 uint32_t count; /* number of consts allocated */
  82                 /* one const allocated per SSBO which has get_buffer_size,
  83                  * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
  84                  * consts:
  85                  */
  86                 uint32_t off[PIPE_MAX_SHADER_BUFFERS];
  87         } ssbo_size;
  88
  89         struct {
  90                 uint32_t mask;  /* bitmask of images that have image_store */
  91                 uint32_t count; /* number of consts allocated */
  92                 /* three const allocated per image which has image_store:
  93                  *  + cpp         (bytes per pixel)
  94                  *  + pitch       (y pitch)
  95                  *  + array_pitch (z pitch)
  96                  */
  97                 uint32_t off[PIPE_MAX_SHADER_IMAGES];
  98         } image_dims;
  99 };
 100
 101 /* Configuration key used to identify a shader variant.. different
 102  * shader variants can be used to implement features not supported
 103  * in hw (two sided color), binning-pass vertex shader, etc.
 104  */
 105 struct ir3_shader_key {
 106         union {
 107                 struct {
 108                         /*
 109                          * Combined Vertex/Fragment shader parameters:
 110                          */
 111                         unsigned ucp_enables : 8;
 112
 113                         /* do we need to check {v,f}saturate_{s,t,r}? */
 114                         unsigned has_per_samp : 1;
 115
 116                         /*
 117                          * Vertex shader variant parameters:
 118                          */
 119                         unsigned binning_pass : 1;
 120                         unsigned vclamp_color : 1;
 121
 122                         /*
 123                          * Fragment shader variant parameters:
 124                          */
 125                         unsigned color_two_side : 1;
 126                         unsigned half_precision : 1;
 127                         /* used when shader needs to handle flat varyings (a4xx)
 128                          * for front/back color inputs to frag shader:
 129                          */
 130                         unsigned rasterflat : 1;
 131                         unsigned fclamp_color : 1;
 132                 };
 133                 uint32_t global;
 134         };
 135
 136         /* bitmask of sampler which needs coords clamped for vertex
 137          * shader:
 138          */
 139         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
 140
 141         /* bitmask of sampler which needs coords clamped for frag
 142          * shader:
 143          */
 144         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 145
 146         /* bitmask of samplers which need astc srgb workaround: */
 147         uint16_t vastc_srgb, fastc_srgb;
 148 };
 149
 150 static inline bool
 151 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 152 {
 153         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 154         if (a->has_per_samp || b->has_per_samp)
 155                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 156         return a->global == b->global;
 157 }
 158
 159 /* will the two keys produce different lowering for a fragment shader? */
 160 static inline bool
 161 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 162 {
 163         if (last_key->has_per_samp || key->has_per_samp) {
 164                 if ((last_key->fsaturate_s != key->fsaturate_s) ||
 165                                 (last_key->fsaturate_t != key->fsaturate_t) ||
 166                                 (last_key->fsaturate_r != key->fsaturate_r) ||
 167                                 (last_key->fastc_srgb != key->fastc_srgb))
 168                         return true;
 169         }
 170
 171         if (last_key->fclamp_color != key->fclamp_color)
 172                 return true;
 173
 174         if (last_key->color_two_side != key->color_two_side)
 175                 return true;
 176
 177         if (last_key->half_precision != key->half_precision)
 178                 return true;
 179
 180         if (last_key->rasterflat != key->rasterflat)
 181                 return true;
 182
 183         if (last_key->ucp_enables != key->ucp_enables)
 184                 return true;
 185
 186         return false;
 187 }
 188
 189 /* will the two keys produce different lowering for a vertex shader? */
 190 static inline bool
 191 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 192 {
 193         if (last_key->has_per_samp || key->has_per_samp) {
 194                 if ((last_key->vsaturate_s != key->vsaturate_s) ||
 195                                 (last_key->vsaturate_t != key->vsaturate_t) ||
 196                                 (last_key->vsaturate_r != key->vsaturate_r) ||
 197                                 (last_key->vastc_srgb != key->vastc_srgb))
 198                         return true;
 199         }
 200
 201         if (last_key->vclamp_color != key->vclamp_color)
 202                 return true;
 203
 204         if (last_key->ucp_enables != key->ucp_enables)
 205                 return true;
 206
 207         return false;
 208 }
 209
 210 struct ir3_shader_variant {
 211         struct fd_bo *bo;
 212
 213         /* variant id (for debug) */
 214         uint32_t id;
 215
 216         struct ir3_shader_key key;
 217
 218         struct ir3_driver_const_layout const_layout;
 219         struct ir3_info info;
 220         struct ir3 *ir;
 221
 222         /* the instructions length is in units of instruction groups
 223          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 224          * instruction is 2 dwords):
 225          */
 226         unsigned instrlen;
 227
 228         /* the constants length is in units of vec4's, and is the sum of
 229          * the uniforms and the built-in compiler constants
 230          */
 231         unsigned constlen;
 232
 233         /* number of uniforms (in vec4), not including built-in compiler
 234          * constants, etc.
 235          */
 236         unsigned num_uniforms;
 237
 238         unsigned num_ubos;
 239
 240         /* About Linkage:
 241          *   + Let the frag shader determine the position/compmask for the
 242          *     varyings, since it is the place where we know if the varying
 243          *     is actually used, and if so, which components are used.  So
 244          *     what the hw calls "outloc" is taken from the "inloc" of the
 245          *     frag shader.
 246          *   + From the vert shader, we only need the output regid
 247          */
 248
 249         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 250          * to bary.f instructions
 251          */
 252         uint8_t pos_regid;
 253         bool frag_coord, frag_face, color0_mrt;
 254
 255         /* NOTE: for input/outputs, slot is:
 256          *   gl_vert_attrib  - for VS inputs
 257          *   gl_varying_slot - for VS output / FS input
 258          *   gl_frag_result  - for FS output
 259          */
 260
 261         /* varyings/outputs: */
 262         unsigned outputs_count;
 263         struct {
 264                 uint8_t slot;
 265                 uint8_t regid;
 266         } outputs[16 + 2];  /* +POSITION +PSIZE */
 267         bool writes_pos, writes_psize;
 268
 269         /* attributes (VS) / varyings (FS):
 270          * Note that sysval's should come *after* normal inputs.
 271          */
 272         unsigned inputs_count;
 273         struct {
 274                 uint8_t slot;
 275                 uint8_t regid;
 276                 uint8_t compmask;
 277                 uint8_t ncomp;
 278                 /* location of input (ie. offset passed to bary.f, etc).  This
 279                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 280                  * have the OUTLOCn value offset by 8, presumably to account
 281                  * for gl_Position/gl_PointSize)
 282                  */
 283                 uint8_t inloc;
 284                 /* vertex shader specific: */
 285                 bool    sysval     : 1;   /* slot is a gl_system_value */
 286                 /* fragment shader specific: */
 287                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 288                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 289                 enum glsl_interp_mode interpolate;
 290         } inputs[16 + 2];  /* +POSITION +FACE */
 291
 292         /* sum of input components (scalar).  For frag shaders, it only counts
 293          * the varying inputs:
 294          */
 295         unsigned total_in;
 296
 297         /* For frag shaders, the total number of inputs (not scalar,
 298          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 299          */
 300         unsigned varying_in;
 301
 302         /* do we have one or more texture sample instructions: */
 303         bool has_samp;
 304
 305         /* do we have one or more SSBO instructions: */
 306         bool has_ssbo;
 307
 308         /* do we have kill instructions: */
 309         bool has_kill;
 310
 311         /* Layout of constant registers, each section (in vec4). Pointer size
 312          * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
 313          * UBO and stream-out consts.
 314          */
 315         struct {
 316                 /* user const start at zero */
 317                 unsigned ubo;
 318                 /* NOTE that a3xx might need a section for SSBO addresses too */
 319                 unsigned ssbo_sizes;
 320                 unsigned image_dims;
 321                 unsigned driver_param;
 322                 unsigned tfbo;
 323                 unsigned immediate;
 324         } constbase;
 325
 326         unsigned immediates_count;
 327         struct {
 328                 uint32_t val[4];
 329         } immediates[64];
 330
 331         /* for astc srgb workaround, the number/base of additional
 332          * alpha tex states we need, and index of original tex states
 333          */
 334         struct {
 335                 unsigned base, count;
 336                 unsigned orig_idx[16];
 337         } astc_srgb;
 338
 339         /* shader variants form a linked list: */
 340         struct ir3_shader_variant *next;
 341
 342         /* replicated here to avoid passing extra ptrs everywhere: */
 343         enum shader_t type;
 344         struct ir3_shader *shader;
 345 };
 346
 347 typedef struct nir_shader nir_shader;
 348
 349 struct ir3_shader {
 350         enum shader_t type;
 351
 352         /* shader id (for debug): */
 353         uint32_t id;
 354         uint32_t variant_count;
 355
 356         /* so we know when we can disable TGSI related hacks: */
 357         bool from_tgsi;
 358
 359         struct ir3_compiler *compiler;
 360
 361         nir_shader *nir;
 362         struct pipe_stream_output_info stream_output;
 363
 364         struct ir3_shader_variant *variants;
 365 };
 366
 367 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 368
 369 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 370                 const struct pipe_shader_state *cso, enum shader_t type,
 371                 struct pipe_debug_callback *debug);
 372 struct ir3_shader *
 373 ir3_shader_create_compute(struct ir3_compiler *compiler,
 374                 const struct pipe_compute_state *cso,
 375                 struct pipe_debug_callback *debug);
 376 void ir3_shader_destroy(struct ir3_shader *shader);
 377 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 378                 struct ir3_shader_key key, struct pipe_debug_callback *debug);
 379 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 380 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 381
 382 struct fd_ringbuffer;
 383 struct fd_context;
 384 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 385                 struct fd_context *ctx, const struct pipe_draw_info *info);
 386 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 387                 struct fd_context *ctx);
 388 void ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 389                 struct fd_context *ctx, const struct pipe_grid_info *info);
 390
 391 int
 392 ir3_glsl_type_size(const struct glsl_type *type);
 393
 394 static inline const char *
 395 ir3_shader_stage(struct ir3_shader *shader)
 396 {
 397         switch (shader->type) {
 398         case SHADER_VERTEX:     return "VERT";
 399         case SHADER_FRAGMENT:   return "FRAG";
 400         case SHADER_COMPUTE:    return "CL";
 401         default:
 402                 unreachable("invalid type");
 403                 return NULL;
 404         }
 405 }
 406
 407 /*
 408  * Helper/util:
 409  */
 410
 411 #include "pipe/p_shader_tokens.h"
 412
 413 static inline int
 414 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 415 {
 416         int j;
 417
 418         for (j = 0; j < so->outputs_count; j++)
 419                 if (so->outputs[j].slot == slot)
 420                         return j;
 421
 422         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 423          * in the vertex shader.. but the fragment shader doesn't know this
 424          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 425          * at link time if there is no matching OUT.BCOLOR[n], we must map
 426          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 427          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 428          */
 429         if (slot == VARYING_SLOT_BFC0) {
 430                 slot = VARYING_SLOT_COL0;
 431         } else if (slot == VARYING_SLOT_BFC1) {
 432                 slot = VARYING_SLOT_COL1;
 433         } else if (slot == VARYING_SLOT_COL0) {
 434                 slot = VARYING_SLOT_BFC0;
 435         } else if (slot == VARYING_SLOT_COL1) {
 436                 slot = VARYING_SLOT_BFC1;
 437         } else {
 438                 return 0;
 439         }
 440
 441         for (j = 0; j < so->outputs_count; j++)
 442                 if (so->outputs[j].slot == slot)
 443                         return j;
 444
 445         debug_assert(0);
 446
 447         return 0;
 448 }
 449
 450 static inline int
 451 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 452 {
 453         while (++i < so->inputs_count)
 454                 if (so->inputs[i].compmask && so->inputs[i].bary)
 455                         break;
 456         return i;
 457 }
 458
 459 struct ir3_shader_linkage {
 460         uint8_t max_loc;
 461         uint8_t cnt;
 462         struct {
 463                 uint8_t regid;
 464                 uint8_t compmask;
 465                 uint8_t loc;
 466         } var[32];
 467 };
 468
 469 static inline void
 470 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 471 {
 472         int i = l->cnt++;
 473
 474         debug_assert(i < ARRAY_SIZE(l->var));
 475
 476         l->var[i].regid    = regid;
 477         l->var[i].compmask = compmask;
 478         l->var[i].loc      = loc;
 479         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 480 }
 481
 482 static inline void
 483 ir3_link_shaders(struct ir3_shader_linkage *l,
 484                 const struct ir3_shader_variant *vs,
 485                 const struct ir3_shader_variant *fs)
 486 {
 487         int j = -1, k;
 488
 489         while (l->cnt < ARRAY_SIZE(l->var)) {
 490                 j = ir3_next_varying(fs, j);
 491
 492                 if (j >= fs->inputs_count)
 493                         break;
 494
 495                 if (fs->inputs[j].inloc >= fs->total_in)
 496                         continue;
 497
 498                 k = ir3_find_output(vs, fs->inputs[j].slot);
 499
 500                 ir3_link_add(l, vs->outputs[k].regid,
 501                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 502         }
 503 }
 504
 505 static inline uint32_t
 506 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 507 {
 508         int j;
 509         for (j = 0; j < so->outputs_count; j++)
 510                 if (so->outputs[j].slot == slot)
 511                         return so->outputs[j].regid;
 512         return regid(63, 0);
 513 }
 514
 515 static inline uint32_t
 516 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
 517 {
 518         int j;
 519         for (j = 0; j < so->inputs_count; j++)
 520                 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
 521                         return so->inputs[j].regid;
 522         return regid(63, 0);
 523 }
 524
 525 #endif /* IR3_SHADER_H_ */