freedreno: add adreno 420 support
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.h
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #ifndef IR3_SHADER_H_
30 #define IR3_SHADER_H_
31
32 #include "ir3.h"
33 #include "disasm.h"
34
35 typedef uint16_t ir3_semantic; /* semantic name + index */
36 static inline ir3_semantic
37 ir3_semantic_name(uint8_t name, uint16_t index)
38 {
39 return (name << 8) | (index & 0xff);
40 }
41
42 static inline uint8_t sem2name(ir3_semantic sem)
43 {
44 return sem >> 8;
45 }
46
47 static inline uint16_t sem2idx(ir3_semantic sem)
48 {
49 return sem & 0xff;
50 }
51
52 /* Configuration key used to identify a shader variant.. different
53 * shader variants can be used to implement features not supported
54 * in hw (two sided color), binning-pass vertex shader, etc.
55 */
56 struct ir3_shader_key {
57 union {
58 struct {
59 /* do we need to check {v,f}saturate_{s,t,r}? */
60 unsigned has_per_samp : 1;
61
62 /*
63 * Vertex shader variant parameters:
64 */
65 unsigned binning_pass : 1;
66
67 /*
68 * Fragment shader variant parameters:
69 */
70 unsigned color_two_side : 1;
71 unsigned half_precision : 1;
72 /* For rendering to alpha, we need a bit of special handling
73 * since the hw always takes gl_FragColor starting from x
74 * component, rather than figuring out to take the w component.
75 * We could be more clever and generate variants for other
76 * render target formats (ie. luminance formats are xxx1), but
77 * let's start with this and see how it goes:
78 */
79 unsigned alpha : 1;
80 };
81 uint32_t global;
82 };
83
84 /* bitmask of sampler which needs coords clamped for vertex
85 * shader:
86 */
87 uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
88
89 /* bitmask of sampler which needs coords clamped for frag
90 * shader:
91 */
92 uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
93
94 };
95
96 static inline bool
97 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
98 {
99 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
100 if (a->has_per_samp || b->has_per_samp)
101 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
102 return a->global == b->global;
103 }
104
105 struct ir3_shader_variant {
106 struct fd_bo *bo;
107
108 struct ir3_shader_key key;
109
110 struct ir3_info info;
111 struct ir3 *ir;
112
113 /* the instructions length is in units of instruction groups
114 * (4 instructions for a3xx, 16 instructions for a4xx.. each
115 * instruction is 2 dwords):
116 */
117 unsigned instrlen;
118
119 /* the constants length is in units of vec4's, and is the sum of
120 * the uniforms and the built-in compiler constants
121 */
122 unsigned constlen;
123
124 /* About Linkage:
125 * + Let the frag shader determine the position/compmask for the
126 * varyings, since it is the place where we know if the varying
127 * is actually used, and if so, which components are used. So
128 * what the hw calls "outloc" is taken from the "inloc" of the
129 * frag shader.
130 * + From the vert shader, we only need the output regid
131 */
132
133 /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
134 * to bary.f instructions
135 */
136 uint8_t pos_regid;
137 bool frag_coord, frag_face;
138
139 /* varyings/outputs: */
140 unsigned outputs_count;
141 struct {
142 ir3_semantic semantic;
143 uint8_t regid;
144 } outputs[16 + 2]; /* +POSITION +PSIZE */
145 bool writes_pos, writes_psize;
146
147 /* vertices/inputs: */
148 unsigned inputs_count;
149 struct {
150 ir3_semantic semantic;
151 uint8_t regid;
152 uint8_t compmask;
153 uint8_t ncomp;
154 /* In theory inloc of fs should match outloc of vs. Or
155 * rather the outloc of the vs is 8 plus the offset passed
156 * to bary.f. Presumably that +8 is to account for
157 * gl_Position/gl_PointSize?
158 *
159 * NOTE inloc is currently aligned to 4 (we don't try
160 * to pack varyings). Changing this would likely break
161 * assumptions in few places (like setting up of flat
162 * shading in fd3_program) so be sure to check all the
163 * spots where inloc is used.
164 */
165 uint8_t inloc;
166 uint8_t bary;
167 uint8_t interpolate;
168 } inputs[16 + 2]; /* +POSITION +FACE */
169
170 unsigned total_in; /* sum of inputs (scalar) */
171
172 /* do we have one or more texture sample instructions: */
173 bool has_samp;
174
175 /* do we have kill instructions: */
176 bool has_kill;
177
178 /* const reg # of first immediate, ie. 1 == c1
179 * (not regid, because TGSI thinks in terms of vec4 registers,
180 * not scalar registers)
181 */
182 unsigned first_immediate;
183 unsigned immediates_count;
184 struct {
185 uint32_t val[4];
186 } immediates[64];
187
188 /* shader variants form a linked list: */
189 struct ir3_shader_variant *next;
190
191 /* replicated here to avoid passing extra ptrs everywhere: */
192 enum shader_t type;
193 struct ir3_shader *shader;
194 };
195
196 struct ir3_shader {
197 enum shader_t type;
198
199 struct pipe_context *pctx;
200 const struct tgsi_token *tokens;
201
202 struct ir3_shader_variant *variants;
203
204 /* so far, only used for blit_prog shader.. values for
205 * VPC_VARYING_PS_REPL[i].MODE
206 */
207 uint32_t vpsrepl[8];
208 };
209
210
211 struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
212 const struct tgsi_token *tokens, enum shader_t type);
213 void ir3_shader_destroy(struct ir3_shader *shader);
214
215 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
216 struct ir3_shader_key key);
217
218 /*
219 * Helper/util:
220 */
221
222 static inline int
223 ir3_find_output(const struct ir3_shader_variant *so, ir3_semantic semantic)
224 {
225 int j;
226
227 for (j = 0; j < so->outputs_count; j++)
228 if (so->outputs[j].semantic == semantic)
229 return j;
230
231 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
232 * in the vertex shader.. but the fragment shader doesn't know this
233 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
234 * at link time if there is no matching OUT.BCOLOR[n], we must map
235 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
236 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
237 */
238 if (sem2name(semantic) == TGSI_SEMANTIC_BCOLOR) {
239 unsigned idx = sem2idx(semantic);
240 semantic = ir3_semantic_name(TGSI_SEMANTIC_COLOR, idx);
241 } else if (sem2name(semantic) == TGSI_SEMANTIC_COLOR) {
242 unsigned idx = sem2idx(semantic);
243 semantic = ir3_semantic_name(TGSI_SEMANTIC_BCOLOR, idx);
244 } else {
245 return 0;
246 }
247
248 for (j = 0; j < so->outputs_count; j++)
249 if (so->outputs[j].semantic == semantic)
250 return j;
251
252 debug_assert(0);
253
254 return 0;
255 }
256
257 static inline int
258 ir3_next_varying(const struct ir3_shader_variant *so, int i)
259 {
260 while (++i < so->inputs_count)
261 if (so->inputs[i].compmask && so->inputs[i].bary)
262 break;
263 return i;
264 }
265
266 static inline uint32_t
267 ir3_find_output_regid(const struct ir3_shader_variant *so, ir3_semantic semantic)
268 {
269 int j;
270 for (j = 0; j < so->outputs_count; j++)
271 if (so->outputs[j].semantic == semantic)
272 return so->outputs[j].regid;
273 return regid(63, 0);
274 }
275
276 #endif /* IR3_SHADER_H_ */