freedreno/a3xx: alpha render-target shenanigans
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.h
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #ifndef IR3_SHADER_H_
30 #define IR3_SHADER_H_
31
32 #include "ir3.h"
33 #include "disasm.h"
34
35 typedef uint16_t ir3_semantic; /* semantic name + index */
36 static inline ir3_semantic
37 ir3_semantic_name(uint8_t name, uint16_t index)
38 {
39 return (name << 8) | (index & 0xff);
40 }
41
42 static inline uint8_t sem2name(ir3_semantic sem)
43 {
44 return sem >> 8;
45 }
46
47 static inline uint16_t sem2idx(ir3_semantic sem)
48 {
49 return sem & 0xff;
50 }
51
52 /* Configuration key used to identify a shader variant.. different
53 * shader variants can be used to implement features not supported
54 * in hw (two sided color), binning-pass vertex shader, etc.
55 */
56 struct ir3_shader_key {
57 /*
58 * Vertex shader variant parameters:
59 */
60 unsigned binning_pass : 1;
61
62 /*
63 * Fragment shader variant parameters:
64 */
65 unsigned color_two_side : 1;
66 unsigned half_precision : 1;
67 /* For rendering to alpha, we need a bit of special handling
68 * since the hw always takes gl_FragColor starting from x
69 * component, rather than figuring out to take the w component.
70 * We could be more clever and generate variants for other
71 * render target formats (ie. luminance formats are xxx1), but
72 * let's start with this and see how it goes:
73 */
74 unsigned alpha : 1;
75 };
76
77 struct ir3_shader_variant {
78 struct fd_bo *bo;
79
80 struct ir3_shader_key key;
81
82 struct ir3_info info;
83 struct ir3 *ir;
84
85 /* the instructions length is in units of instruction groups
86 * (4 instructions, 8 dwords):
87 */
88 unsigned instrlen;
89
90 /* the constants length is in units of vec4's, and is the sum of
91 * the uniforms and the built-in compiler constants
92 */
93 unsigned constlen;
94
95 /* About Linkage:
96 * + Let the frag shader determine the position/compmask for the
97 * varyings, since it is the place where we know if the varying
98 * is actually used, and if so, which components are used. So
99 * what the hw calls "outloc" is taken from the "inloc" of the
100 * frag shader.
101 * + From the vert shader, we only need the output regid
102 */
103
104 /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
105 * to bary.f instructions
106 */
107 uint8_t pos_regid;
108 bool frag_coord, frag_face;
109
110 /* varyings/outputs: */
111 unsigned outputs_count;
112 struct {
113 ir3_semantic semantic;
114 uint8_t regid;
115 } outputs[16 + 2]; /* +POSITION +PSIZE */
116 bool writes_pos, writes_psize;
117
118 /* vertices/inputs: */
119 unsigned inputs_count;
120 struct {
121 ir3_semantic semantic;
122 uint8_t regid;
123 uint8_t compmask;
124 uint8_t ncomp;
125 /* in theory inloc of fs should match outloc of vs: */
126 uint8_t inloc;
127 uint8_t bary;
128 } inputs[16 + 2]; /* +POSITION +FACE */
129
130 unsigned total_in; /* sum of inputs (scalar) */
131
132 /* do we have one or more texture sample instructions: */
133 bool has_samp;
134
135 /* const reg # of first immediate, ie. 1 == c1
136 * (not regid, because TGSI thinks in terms of vec4 registers,
137 * not scalar registers)
138 */
139 unsigned first_immediate;
140 unsigned immediates_count;
141 struct {
142 uint32_t val[4];
143 } immediates[64];
144
145 /* shader variants form a linked list: */
146 struct ir3_shader_variant *next;
147
148 /* replicated here to avoid passing extra ptrs everywhere: */
149 enum shader_t type;
150 struct ir3_shader *shader;
151 };
152
153 struct ir3_shader {
154 enum shader_t type;
155
156 struct pipe_context *pctx;
157 const struct tgsi_token *tokens;
158
159 struct ir3_shader_variant *variants;
160
161 /* so far, only used for blit_prog shader.. values for
162 * VPC_VARYING_INTERP[i].MODE and VPC_VARYING_PS_REPL[i].MODE
163 */
164 uint32_t vinterp[4], vpsrepl[4];
165 };
166
167
168 struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
169 const struct tgsi_token *tokens, enum shader_t type);
170 void ir3_shader_destroy(struct ir3_shader *shader);
171
172 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
173 struct ir3_shader_key key);
174
175 #endif /* IR3_SHADER_H_ */