src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "compiler/shader_enums.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37 #include "disasm.h"
  38
  39 struct glsl_type;
  40
  41 /* driver param indices: */
  42 enum ir3_driver_param {
  43         /* compute shader driver params: */
  44         IR3_DP_NUM_WORK_GROUPS_X = 0,
  45         IR3_DP_NUM_WORK_GROUPS_Y = 1,
  46         IR3_DP_NUM_WORK_GROUPS_Z = 2,
  47         IR3_DP_CS_COUNT   = 4,   /* must be aligned to vec4 */
  48
  49         /* vertex shader driver params: */
  50         IR3_DP_VTXID_BASE = 0,
  51         IR3_DP_VTXCNT_MAX = 1,
  52         /* user-clip-plane components, up to 8x vec4's: */
  53         IR3_DP_UCP0_X     = 4,
  54         /* .... */
  55         IR3_DP_UCP7_W     = 35,
  56         IR3_DP_VS_COUNT   = 36   /* must be aligned to vec4 */
  57 };
  58
  59 /**
  60  * For consts needed to pass internal values to shader which may or may not
  61  * be required, rather than allocating worst-case const space, we scan the
  62  * shader and allocate consts as-needed:
  63  *
  64  *   + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
  65  *     for a given SSBO
  66  *
  67  *   + Image dimensions: needed to calculate pixel offset, but only for
  68  *     images that have a image_store intrinsic
  69  */
  70 struct ir3_driver_const_layout {
  71         struct {
  72                 uint32_t mask;  /* bitmask of SSBOs that have get_buffer_size */
  73                 uint32_t count; /* number of consts allocated */
  74                 /* one const allocated per SSBO which has get_buffer_size,
  75                  * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
  76                  * consts:
  77                  */
  78                 uint32_t off[PIPE_MAX_SHADER_BUFFERS];
  79         } ssbo_size;
  80
  81         struct {
  82                 uint32_t mask;  /* bitmask of images that have image_store */
  83                 uint32_t count; /* number of consts allocated */
  84                 /* three const allocated per image which has image_store:
  85                  *  + cpp         (bytes per pixel)
  86                  *  + pitch       (y pitch)
  87                  *  + array_pitch (z pitch)
  88                  */
  89                 uint32_t off[PIPE_MAX_SHADER_IMAGES];
  90         } image_dims;
  91 };
  92
  93 /* Configuration key used to identify a shader variant.. different
  94  * shader variants can be used to implement features not supported
  95  * in hw (two sided color), binning-pass vertex shader, etc.
  96  */
  97 struct ir3_shader_key {
  98         union {
  99                 struct {
 100                         /*
 101                          * Combined Vertex/Fragment shader parameters:
 102                          */
 103                         unsigned ucp_enables : 8;
 104
 105                         /* do we need to check {v,f}saturate_{s,t,r}? */
 106                         unsigned has_per_samp : 1;
 107
 108                         /*
 109                          * Vertex shader variant parameters:
 110                          */
 111                         unsigned binning_pass : 1;
 112                         unsigned vclamp_color : 1;
 113
 114                         /*
 115                          * Fragment shader variant parameters:
 116                          */
 117                         unsigned color_two_side : 1;
 118                         unsigned half_precision : 1;
 119                         /* used when shader needs to handle flat varyings (a4xx)
 120                          * for front/back color inputs to frag shader:
 121                          */
 122                         unsigned rasterflat : 1;
 123                         unsigned fclamp_color : 1;
 124                 };
 125                 uint32_t global;
 126         };
 127
 128         /* bitmask of sampler which needs coords clamped for vertex
 129          * shader:
 130          */
 131         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
 132
 133         /* bitmask of sampler which needs coords clamped for frag
 134          * shader:
 135          */
 136         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 137
 138         /* bitmask of samplers which need astc srgb workaround: */
 139         uint16_t vastc_srgb, fastc_srgb;
 140 };
 141
 142 static inline bool
 143 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 144 {
 145         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 146         if (a->has_per_samp || b->has_per_samp)
 147                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 148         return a->global == b->global;
 149 }
 150
 151 /* will the two keys produce different lowering for a fragment shader? */
 152 static inline bool
 153 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 154 {
 155         if (last_key->has_per_samp || key->has_per_samp) {
 156                 if ((last_key->fsaturate_s != key->fsaturate_s) ||
 157                                 (last_key->fsaturate_t != key->fsaturate_t) ||
 158                                 (last_key->fsaturate_r != key->fsaturate_r) ||
 159                                 (last_key->fastc_srgb != key->fastc_srgb))
 160                         return true;
 161         }
 162
 163         if (last_key->fclamp_color != key->fclamp_color)
 164                 return true;
 165
 166         if (last_key->color_two_side != key->color_two_side)
 167                 return true;
 168
 169         if (last_key->half_precision != key->half_precision)
 170                 return true;
 171
 172         if (last_key->rasterflat != key->rasterflat)
 173                 return true;
 174
 175         if (last_key->ucp_enables != key->ucp_enables)
 176                 return true;
 177
 178         return false;
 179 }
 180
 181 /* will the two keys produce different lowering for a vertex shader? */
 182 static inline bool
 183 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 184 {
 185         if (last_key->has_per_samp || key->has_per_samp) {
 186                 if ((last_key->vsaturate_s != key->vsaturate_s) ||
 187                                 (last_key->vsaturate_t != key->vsaturate_t) ||
 188                                 (last_key->vsaturate_r != key->vsaturate_r) ||
 189                                 (last_key->vastc_srgb != key->vastc_srgb))
 190                         return true;
 191         }
 192
 193         if (last_key->vclamp_color != key->vclamp_color)
 194                 return true;
 195
 196         if (last_key->ucp_enables != key->ucp_enables)
 197                 return true;
 198
 199         return false;
 200 }
 201
 202 struct ir3_shader_variant {
 203         struct fd_bo *bo;
 204
 205         /* variant id (for debug) */
 206         uint32_t id;
 207
 208         struct ir3_shader_key key;
 209
 210         struct ir3_driver_const_layout const_layout;
 211         struct ir3_info info;
 212         struct ir3 *ir;
 213
 214         /* the instructions length is in units of instruction groups
 215          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 216          * instruction is 2 dwords):
 217          */
 218         unsigned instrlen;
 219
 220         /* the constants length is in units of vec4's, and is the sum of
 221          * the uniforms and the built-in compiler constants
 222          */
 223         unsigned constlen;
 224
 225         /* number of uniforms (in vec4), not including built-in compiler
 226          * constants, etc.
 227          */
 228         unsigned num_uniforms;
 229
 230         unsigned num_ubos;
 231
 232         /* About Linkage:
 233          *   + Let the frag shader determine the position/compmask for the
 234          *     varyings, since it is the place where we know if the varying
 235          *     is actually used, and if so, which components are used.  So
 236          *     what the hw calls "outloc" is taken from the "inloc" of the
 237          *     frag shader.
 238          *   + From the vert shader, we only need the output regid
 239          */
 240
 241         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 242          * to bary.f instructions
 243          */
 244         uint8_t pos_regid;
 245         bool frag_coord, frag_face, color0_mrt;
 246
 247         /* NOTE: for input/outputs, slot is:
 248          *   gl_vert_attrib  - for VS inputs
 249          *   gl_varying_slot - for VS output / FS input
 250          *   gl_frag_result  - for FS output
 251          */
 252
 253         /* varyings/outputs: */
 254         unsigned outputs_count;
 255         struct {
 256                 uint8_t slot;
 257                 uint8_t regid;
 258         } outputs[16 + 2];  /* +POSITION +PSIZE */
 259         bool writes_pos, writes_psize;
 260
 261         /* attributes (VS) / varyings (FS):
 262          * Note that sysval's should come *after* normal inputs.
 263          */
 264         unsigned inputs_count;
 265         struct {
 266                 uint8_t slot;
 267                 uint8_t regid;
 268                 uint8_t compmask;
 269                 uint8_t ncomp;
 270                 /* location of input (ie. offset passed to bary.f, etc).  This
 271                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 272                  * have the OUTLOCn value offset by 8, presumably to account
 273                  * for gl_Position/gl_PointSize)
 274                  */
 275                 uint8_t inloc;
 276                 /* vertex shader specific: */
 277                 bool    sysval     : 1;   /* slot is a gl_system_value */
 278                 /* fragment shader specific: */
 279                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 280                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 281                 enum glsl_interp_mode interpolate;
 282         } inputs[16 + 2];  /* +POSITION +FACE */
 283
 284         /* sum of input components (scalar).  For frag shaders, it only counts
 285          * the varying inputs:
 286          */
 287         unsigned total_in;
 288
 289         /* For frag shaders, the total number of inputs (not scalar,
 290          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 291          */
 292         unsigned varying_in;
 293
 294         /* do we have one or more texture sample instructions: */
 295         bool has_samp;
 296
 297         /* do we have one or more SSBO instructions: */
 298         bool has_ssbo;
 299
 300         /* do we have kill instructions: */
 301         bool has_kill;
 302
 303         /* Layout of constant registers, each section (in vec4). Pointer size
 304          * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
 305          * UBO and stream-out consts.
 306          */
 307         struct {
 308                 /* user const start at zero */
 309                 unsigned ubo;
 310                 /* NOTE that a3xx might need a section for SSBO addresses too */
 311                 unsigned ssbo_sizes;
 312                 unsigned image_dims;
 313                 unsigned driver_param;
 314                 unsigned tfbo;
 315                 unsigned immediate;
 316         } constbase;
 317
 318         unsigned immediates_count;
 319         struct {
 320                 uint32_t val[4];
 321         } immediates[64];
 322
 323         /* for astc srgb workaround, the number/base of additional
 324          * alpha tex states we need, and index of original tex states
 325          */
 326         struct {
 327                 unsigned base, count;
 328                 unsigned orig_idx[16];
 329         } astc_srgb;
 330
 331         /* shader variants form a linked list: */
 332         struct ir3_shader_variant *next;
 333
 334         /* replicated here to avoid passing extra ptrs everywhere: */
 335         enum shader_t type;
 336         struct ir3_shader *shader;
 337 };
 338
 339 typedef struct nir_shader nir_shader;
 340
 341 struct ir3_shader {
 342         enum shader_t type;
 343
 344         /* shader id (for debug): */
 345         uint32_t id;
 346         uint32_t variant_count;
 347
 348         /* so we know when we can disable TGSI related hacks: */
 349         bool from_tgsi;
 350
 351         struct ir3_compiler *compiler;
 352
 353         nir_shader *nir;
 354         struct pipe_stream_output_info stream_output;
 355
 356         struct ir3_shader_variant *variants;
 357 };
 358
 359 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 360
 361 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 362                 const struct pipe_shader_state *cso, enum shader_t type,
 363                 struct pipe_debug_callback *debug);
 364 struct ir3_shader *
 365 ir3_shader_create_compute(struct ir3_compiler *compiler,
 366                 const struct pipe_compute_state *cso,
 367                 struct pipe_debug_callback *debug);
 368 void ir3_shader_destroy(struct ir3_shader *shader);
 369 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 370                 struct ir3_shader_key key, struct pipe_debug_callback *debug);
 371 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 372 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 373
 374 struct fd_ringbuffer;
 375 struct fd_context;
 376 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 377                 struct fd_context *ctx, const struct pipe_draw_info *info);
 378 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 379                 struct fd_context *ctx);
 380 void ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 381                 struct fd_context *ctx, const struct pipe_grid_info *info);
 382
 383 int
 384 ir3_glsl_type_size(const struct glsl_type *type);
 385
 386 static inline const char *
 387 ir3_shader_stage(struct ir3_shader *shader)
 388 {
 389         switch (shader->type) {
 390         case SHADER_VERTEX:     return "VERT";
 391         case SHADER_FRAGMENT:   return "FRAG";
 392         case SHADER_COMPUTE:    return "CL";
 393         default:
 394                 unreachable("invalid type");
 395                 return NULL;
 396         }
 397 }
 398
 399 /*
 400  * Helper/util:
 401  */
 402
 403 #include "pipe/p_shader_tokens.h"
 404
 405 static inline int
 406 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 407 {
 408         int j;
 409
 410         for (j = 0; j < so->outputs_count; j++)
 411                 if (so->outputs[j].slot == slot)
 412                         return j;
 413
 414         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 415          * in the vertex shader.. but the fragment shader doesn't know this
 416          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 417          * at link time if there is no matching OUT.BCOLOR[n], we must map
 418          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 419          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 420          */
 421         if (slot == VARYING_SLOT_BFC0) {
 422                 slot = VARYING_SLOT_COL0;
 423         } else if (slot == VARYING_SLOT_BFC1) {
 424                 slot = VARYING_SLOT_COL1;
 425         } else if (slot == VARYING_SLOT_COL0) {
 426                 slot = VARYING_SLOT_BFC0;
 427         } else if (slot == VARYING_SLOT_COL1) {
 428                 slot = VARYING_SLOT_BFC1;
 429         } else {
 430                 return 0;
 431         }
 432
 433         for (j = 0; j < so->outputs_count; j++)
 434                 if (so->outputs[j].slot == slot)
 435                         return j;
 436
 437         debug_assert(0);
 438
 439         return 0;
 440 }
 441
 442 static inline int
 443 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 444 {
 445         while (++i < so->inputs_count)
 446                 if (so->inputs[i].compmask && so->inputs[i].bary)
 447                         break;
 448         return i;
 449 }
 450
 451 struct ir3_shader_linkage {
 452         uint8_t max_loc;
 453         uint8_t cnt;
 454         struct {
 455                 uint8_t regid;
 456                 uint8_t compmask;
 457                 uint8_t loc;
 458         } var[32];
 459 };
 460
 461 static inline void
 462 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 463 {
 464         int i = l->cnt++;
 465
 466         debug_assert(i < ARRAY_SIZE(l->var));
 467
 468         l->var[i].regid    = regid;
 469         l->var[i].compmask = compmask;
 470         l->var[i].loc      = loc;
 471         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 472 }
 473
 474 static inline void
 475 ir3_link_shaders(struct ir3_shader_linkage *l,
 476                 const struct ir3_shader_variant *vs,
 477                 const struct ir3_shader_variant *fs)
 478 {
 479         int j = -1, k;
 480
 481         while (l->cnt < ARRAY_SIZE(l->var)) {
 482                 j = ir3_next_varying(fs, j);
 483
 484                 if (j >= fs->inputs_count)
 485                         break;
 486
 487                 if (fs->inputs[j].inloc >= fs->total_in)
 488                         continue;
 489
 490                 k = ir3_find_output(vs, fs->inputs[j].slot);
 491
 492                 ir3_link_add(l, vs->outputs[k].regid,
 493                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 494         }
 495 }
 496
 497 static inline uint32_t
 498 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 499 {
 500         int j;
 501         for (j = 0; j < so->outputs_count; j++)
 502                 if (so->outputs[j].slot == slot)
 503                         return so->outputs[j].regid;
 504         return regid(63, 0);
 505 }
 506
 507 static inline uint32_t
 508 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
 509 {
 510         int j;
 511         for (j = 0; j < so->inputs_count; j++)
 512                 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
 513                         return so->inputs[j].regid;
 514         return regid(63, 0);
 515 }
 516
 517 #endif /* IR3_SHADER_H_ */