src/gallium/drivers/freedreno/ir3/ir3_shader.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef IR3_SHADER_H_
  30 #define IR3_SHADER_H_
  31
  32 #include "pipe/p_state.h"
  33 #include "compiler/shader_enums.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37 #include "disasm.h"
  38
  39 /* driver param indices: */
  40 enum ir3_driver_param {
  41         IR3_DP_VTXID_BASE = 0,
  42         IR3_DP_VTXCNT_MAX = 1,
  43         /* user-clip-plane components, up to 8x vec4's: */
  44         IR3_DP_UCP0_X     = 4,
  45         /* .... */
  46         IR3_DP_UCP7_W     = 35,
  47         IR3_DP_COUNT      = 36   /* must be aligned to vec4 */
  48 };
  49
  50 /* Configuration key used to identify a shader variant.. different
  51  * shader variants can be used to implement features not supported
  52  * in hw (two sided color), binning-pass vertex shader, etc.
  53  */
  54 struct ir3_shader_key {
  55         union {
  56                 struct {
  57                         /*
  58                          * Combined Vertex/Fragment shader parameters:
  59                          */
  60                         unsigned ucp_enables : 8;
  61
  62                         /* do we need to check {v,f}saturate_{s,t,r}? */
  63                         unsigned has_per_samp : 1;
  64
  65                         /*
  66                          * Vertex shader variant parameters:
  67                          */
  68                         unsigned binning_pass : 1;
  69                         unsigned vclamp_color : 1;
  70
  71                         /*
  72                          * Fragment shader variant parameters:
  73                          */
  74                         unsigned color_two_side : 1;
  75                         unsigned half_precision : 1;
  76                         /* used when shader needs to handle flat varyings (a4xx)
  77                          * for front/back color inputs to frag shader:
  78                          */
  79                         unsigned rasterflat : 1;
  80                         unsigned fclamp_color : 1;
  81                 };
  82                 uint32_t global;
  83         };
  84
  85         /* bitmask of sampler which needs coords clamped for vertex
  86          * shader:
  87          */
  88         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
  89
  90         /* bitmask of sampler which needs coords clamped for frag
  91          * shader:
  92          */
  93         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
  94
  95         /* bitmask of samplers which need astc srgb workaround: */
  96         uint16_t vastc_srgb, fastc_srgb;
  97 };
  98
  99 static inline bool
 100 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 101 {
 102         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 103         if (a->has_per_samp || b->has_per_samp)
 104                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 105         return a->global == b->global;
 106 }
 107
 108 /* will the two keys produce different lowering for a fragment shader? */
 109 static inline bool
 110 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 111 {
 112         if (last_key->has_per_samp || key->has_per_samp) {
 113                 if ((last_key->fsaturate_s != key->fsaturate_s) ||
 114                                 (last_key->fsaturate_t != key->fsaturate_t) ||
 115                                 (last_key->fsaturate_r != key->fsaturate_r) ||
 116                                 (last_key->fastc_srgb != key->fastc_srgb))
 117                         return true;
 118         }
 119
 120         if (last_key->fclamp_color != key->fclamp_color)
 121                 return true;
 122
 123         if (last_key->color_two_side != key->color_two_side)
 124                 return true;
 125
 126         if (last_key->half_precision != key->half_precision)
 127                 return true;
 128
 129         if (last_key->rasterflat != key->rasterflat)
 130                 return true;
 131
 132         if (last_key->ucp_enables != key->ucp_enables)
 133                 return true;
 134
 135         return false;
 136 }
 137
 138 /* will the two keys produce different lowering for a vertex shader? */
 139 static inline bool
 140 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 141 {
 142         if (last_key->has_per_samp || key->has_per_samp) {
 143                 if ((last_key->vsaturate_s != key->vsaturate_s) ||
 144                                 (last_key->vsaturate_t != key->vsaturate_t) ||
 145                                 (last_key->vsaturate_r != key->vsaturate_r) ||
 146                                 (last_key->vastc_srgb != key->vastc_srgb))
 147                         return true;
 148         }
 149
 150         if (last_key->vclamp_color != key->vclamp_color)
 151                 return true;
 152
 153         if (last_key->ucp_enables != key->ucp_enables)
 154                 return true;
 155
 156         return false;
 157 }
 158
 159 struct ir3_shader_variant {
 160         struct fd_bo *bo;
 161
 162         /* variant id (for debug) */
 163         uint32_t id;
 164
 165         struct ir3_shader_key key;
 166
 167         struct ir3_info info;
 168         struct ir3 *ir;
 169
 170         /* the instructions length is in units of instruction groups
 171          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 172          * instruction is 2 dwords):
 173          */
 174         unsigned instrlen;
 175
 176         /* the constants length is in units of vec4's, and is the sum of
 177          * the uniforms and the built-in compiler constants
 178          */
 179         unsigned constlen;
 180
 181         /* number of uniforms (in vec4), not including built-in compiler
 182          * constants, etc.
 183          */
 184         unsigned num_uniforms;
 185         unsigned num_ubos;
 186
 187         /* About Linkage:
 188          *   + Let the frag shader determine the position/compmask for the
 189          *     varyings, since it is the place where we know if the varying
 190          *     is actually used, and if so, which components are used.  So
 191          *     what the hw calls "outloc" is taken from the "inloc" of the
 192          *     frag shader.
 193          *   + From the vert shader, we only need the output regid
 194          */
 195
 196         /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
 197          * to bary.f instructions
 198          */
 199         uint8_t pos_regid;
 200         bool frag_coord, frag_face, color0_mrt;
 201
 202         /* NOTE: for input/outputs, slot is:
 203          *   gl_vert_attrib  - for VS inputs
 204          *   gl_varying_slot - for VS output / FS input
 205          *   gl_frag_result  - for FS output
 206          */
 207
 208         /* varyings/outputs: */
 209         unsigned outputs_count;
 210         struct {
 211                 uint8_t slot;
 212                 uint8_t regid;
 213         } outputs[16 + 2];  /* +POSITION +PSIZE */
 214         bool writes_pos, writes_psize;
 215
 216         /* attributes (VS) / varyings (FS):
 217          * Note that sysval's should come *after* normal inputs.
 218          */
 219         unsigned inputs_count;
 220         struct {
 221                 uint8_t slot;
 222                 uint8_t regid;
 223                 uint8_t compmask;
 224                 uint8_t ncomp;
 225                 /* location of input (ie. offset passed to bary.f, etc).  This
 226                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 227                  * have the OUTLOCn value offset by 8, presumably to account
 228                  * for gl_Position/gl_PointSize)
 229                  */
 230                 uint8_t inloc;
 231                 /* vertex shader specific: */
 232                 bool    sysval     : 1;   /* slot is a gl_system_value */
 233                 /* fragment shader specific: */
 234                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 235                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 236                 enum glsl_interp_mode interpolate;
 237         } inputs[16 + 2];  /* +POSITION +FACE */
 238
 239         /* sum of input components (scalar).  For frag shaders, it only counts
 240          * the varying inputs:
 241          */
 242         unsigned total_in;
 243
 244         /* For frag shaders, the total number of inputs (not scalar,
 245          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 246          */
 247         unsigned varying_in;
 248
 249         /* do we have one or more texture sample instructions: */
 250         bool has_samp;
 251
 252         /* do we have one or more SSBO instructions: */
 253         bool has_ssbo;
 254
 255         /* do we have kill instructions: */
 256         bool has_kill;
 257
 258         /* Layout of constant registers, each section (in vec4). Pointer size
 259          * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
 260          * UBO and stream-out consts.
 261          */
 262         struct {
 263                 /* user const start at zero */
 264                 unsigned ubo;
 265                 unsigned driver_param;
 266                 unsigned tfbo;
 267                 unsigned immediate;
 268         } constbase;
 269
 270         unsigned immediates_count;
 271         struct {
 272                 uint32_t val[4];
 273         } immediates[64];
 274
 275         /* for astc srgb workaround, the number/base of additional
 276          * alpha tex states we need, and index of original tex states
 277          */
 278         struct {
 279                 unsigned base, count;
 280                 unsigned orig_idx[16];
 281         } astc_srgb;
 282
 283         /* shader variants form a linked list: */
 284         struct ir3_shader_variant *next;
 285
 286         /* replicated here to avoid passing extra ptrs everywhere: */
 287         enum shader_t type;
 288         struct ir3_shader *shader;
 289 };
 290
 291 typedef struct nir_shader nir_shader;
 292
 293 struct ir3_shader {
 294         enum shader_t type;
 295
 296         /* shader id (for debug): */
 297         uint32_t id;
 298         uint32_t variant_count;
 299
 300         /* so we know when we can disable TGSI related hacks: */
 301         bool from_tgsi;
 302
 303         struct ir3_compiler *compiler;
 304
 305         nir_shader *nir;
 306         struct pipe_stream_output_info stream_output;
 307
 308         struct ir3_shader_variant *variants;
 309 };
 310
 311 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 312
 313 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 314                 const struct pipe_shader_state *cso, enum shader_t type,
 315                 struct pipe_debug_callback *debug);
 316 void ir3_shader_destroy(struct ir3_shader *shader);
 317 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 318                 struct ir3_shader_key key, struct pipe_debug_callback *debug);
 319 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 320 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 321
 322 struct fd_ringbuffer;
 323 struct fd_context;
 324 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 325                 struct fd_context *ctx, const struct pipe_draw_info *info);
 326 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 327                 struct fd_context *ctx);
 328
 329 static inline const char *
 330 ir3_shader_stage(struct ir3_shader *shader)
 331 {
 332         switch (shader->type) {
 333         case SHADER_VERTEX:     return "VERT";
 334         case SHADER_FRAGMENT:   return "FRAG";
 335         case SHADER_COMPUTE:    return "CL";
 336         default:
 337                 unreachable("invalid type");
 338                 return NULL;
 339         }
 340 }
 341
 342 /*
 343  * Helper/util:
 344  */
 345
 346 #include "pipe/p_shader_tokens.h"
 347
 348 static inline int
 349 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 350 {
 351         int j;
 352
 353         for (j = 0; j < so->outputs_count; j++)
 354                 if (so->outputs[j].slot == slot)
 355                         return j;
 356
 357         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 358          * in the vertex shader.. but the fragment shader doesn't know this
 359          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 360          * at link time if there is no matching OUT.BCOLOR[n], we must map
 361          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 362          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 363          */
 364         if (slot == VARYING_SLOT_BFC0) {
 365                 slot = VARYING_SLOT_COL0;
 366         } else if (slot == VARYING_SLOT_BFC1) {
 367                 slot = VARYING_SLOT_COL1;
 368         } else if (slot == VARYING_SLOT_COL0) {
 369                 slot = VARYING_SLOT_BFC0;
 370         } else if (slot == VARYING_SLOT_COL1) {
 371                 slot = VARYING_SLOT_BFC1;
 372         } else {
 373                 return 0;
 374         }
 375
 376         for (j = 0; j < so->outputs_count; j++)
 377                 if (so->outputs[j].slot == slot)
 378                         return j;
 379
 380         debug_assert(0);
 381
 382         return 0;
 383 }
 384
 385 static inline int
 386 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 387 {
 388         while (++i < so->inputs_count)
 389                 if (so->inputs[i].compmask && so->inputs[i].bary)
 390                         break;
 391         return i;
 392 }
 393
 394 struct ir3_shader_linkage {
 395         uint8_t max_loc;
 396         uint8_t cnt;
 397         struct {
 398                 uint8_t regid;
 399                 uint8_t compmask;
 400                 uint8_t loc;
 401         } var[32];
 402 };
 403
 404 static inline void
 405 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 406 {
 407         int i = l->cnt++;
 408
 409         debug_assert(i < ARRAY_SIZE(l->var));
 410
 411         l->var[i].regid    = regid;
 412         l->var[i].compmask = compmask;
 413         l->var[i].loc      = loc;
 414         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 415 }
 416
 417 static inline void
 418 ir3_link_shaders(struct ir3_shader_linkage *l,
 419                 const struct ir3_shader_variant *vs,
 420                 const struct ir3_shader_variant *fs)
 421 {
 422         int j = -1, k;
 423
 424         while (l->cnt < ARRAY_SIZE(l->var)) {
 425                 j = ir3_next_varying(fs, j);
 426
 427                 if (j >= fs->inputs_count)
 428                         break;
 429
 430                 if (fs->inputs[j].inloc >= fs->total_in)
 431                         continue;
 432
 433                 k = ir3_find_output(vs, fs->inputs[j].slot);
 434
 435                 ir3_link_add(l, vs->outputs[k].regid,
 436                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 437         }
 438 }
 439
 440 static inline uint32_t
 441 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 442 {
 443         int j;
 444         for (j = 0; j < so->outputs_count; j++)
 445                 if (so->outputs[j].slot == slot)
 446                         return so->outputs[j].regid;
 447         return regid(63, 0);
 448 }
 449
 450 static inline uint32_t
 451 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
 452 {
 453         int j;
 454         for (j = 0; j < so->inputs_count; j++)
 455                 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
 456                         return so->inputs[j].regid;
 457         return regid(63, 0);
 458 }
 459
 460 #endif /* IR3_SHADER_H_ */