src/gallium/drivers/i915/i915_fpc_optimize.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2011 The Chromium OS authors.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL GOOGLE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "i915_reg.h"
  29 #include "i915_context.h"
  30 #include "i915_fpc.h"
  31
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_math.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_string.h"
  36 #include "tgsi/tgsi_parse.h"
  37 #include "tgsi/tgsi_dump.h"
  38 #include "tgsi/tgsi_exec.h"
  39
  40 struct i915_optimize_context
  41 {
  42    int first_write[TGSI_EXEC_NUM_TEMPS];
  43    int last_read[TGSI_EXEC_NUM_TEMPS];
  44 };
  45
  46 static boolean same_src_dst_reg(struct i915_full_src_register *s1, struct i915_full_dst_register *d1)
  47 {
  48    return (s1->Register.File == d1->Register.File &&
  49            s1->Register.Indirect == d1->Register.Indirect &&
  50            s1->Register.Dimension == d1->Register.Dimension &&
  51            s1->Register.Index == d1->Register.Index);
  52 }
  53
  54 static boolean same_dst_reg(struct i915_full_dst_register *d1, struct i915_full_dst_register *d2)
  55 {
  56    return (d1->Register.File == d2->Register.File &&
  57            d1->Register.Indirect == d2->Register.Indirect &&
  58            d1->Register.Dimension == d2->Register.Dimension &&
  59            d1->Register.Index == d2->Register.Index);
  60 }
  61
  62 static boolean same_src_reg(struct i915_full_src_register *d1, struct i915_full_src_register *d2)
  63 {
  64    return (d1->Register.File == d2->Register.File &&
  65            d1->Register.Indirect == d2->Register.Indirect &&
  66            d1->Register.Dimension == d2->Register.Dimension &&
  67            d1->Register.Index == d2->Register.Index &&
  68            d1->Register.Absolute == d2->Register.Absolute &&
  69            d1->Register.Negate == d2->Register.Negate);
  70 }
  71
  72 static const struct {
  73    boolean is_texture;
  74    boolean commutes;
  75    unsigned neutral_element;
  76    unsigned num_dst;
  77    unsigned num_src;
  78 } op_table [TGSI_OPCODE_LAST] = {
  79    [ TGSI_OPCODE_ADD     ] = { false,   true,  TGSI_SWIZZLE_ZERO,  1,  2 },
  80    [ TGSI_OPCODE_CEIL    ] = { false,  false,                  0,  1,  1 },
  81    [ TGSI_OPCODE_CMP     ] = { false,  false,                  0,  1,  2 },
  82    [ TGSI_OPCODE_COS     ] = { false,  false,                  0,  1,  1 },
  83    [ TGSI_OPCODE_DDX     ] = { false,  false,                  0,  1,  0 },
  84    [ TGSI_OPCODE_DDY     ] = { false,  false,                  0,  1,  0 },
  85    [ TGSI_OPCODE_DP2     ] = { false,   true,   TGSI_SWIZZLE_ONE,  1,  2 },
  86    [ TGSI_OPCODE_DP3     ] = { false,   true,   TGSI_SWIZZLE_ONE,  1,  2 },
  87    [ TGSI_OPCODE_DP4     ] = { false,   true,   TGSI_SWIZZLE_ONE,  1,  2 },
  88    [ TGSI_OPCODE_DST     ] = { false,  false,                  0,  1,  2 },
  89    [ TGSI_OPCODE_END     ] = { false,  false,                  0,  0,  0 },
  90    [ TGSI_OPCODE_EX2     ] = { false,  false,                  0,  1,  1 },
  91    [ TGSI_OPCODE_FLR     ] = { false,  false,                  0,  1,  1 },
  92    [ TGSI_OPCODE_FRC     ] = { false,  false,                  0,  1,  1 },
  93    [ TGSI_OPCODE_KILL_IF ] = { false,  false,                  0,  0,  1 },
  94    [ TGSI_OPCODE_KILL    ] = { false,  false,                  0,  0,  0 },
  95    [ TGSI_OPCODE_LG2     ] = { false,  false,                  0,  1,  1 },
  96    [ TGSI_OPCODE_LIT     ] = { false,  false,                  0,  1,  1 },
  97    [ TGSI_OPCODE_LRP     ] = { false,  false,                  0,  1,  3 },
  98    [ TGSI_OPCODE_MAX     ] = { false,  false,                  0,  1,  2 },
  99    [ TGSI_OPCODE_MAD     ] = { false,  false,                  0,  1,  3 },
 100    [ TGSI_OPCODE_MIN     ] = { false,  false,                  0,  1,  2 },
 101    [ TGSI_OPCODE_MOV     ] = { false,  false,                  0,  1,  1 },
 102    [ TGSI_OPCODE_MUL     ] = { false,   true,   TGSI_SWIZZLE_ONE,  1,  2 },
 103    [ TGSI_OPCODE_NOP     ] = { false,  false,                  0,  0,  0 },
 104    [ TGSI_OPCODE_POW     ] = { false,  false,                  0,  1,  2 },
 105    [ TGSI_OPCODE_RCP     ] = { false,  false,                  0,  1,  1 },
 106    [ TGSI_OPCODE_RET     ] = { false,  false,                  0,  0,  0 },
 107    [ TGSI_OPCODE_RSQ     ] = { false,  false,                  0,  1,  1 },
 108    [ TGSI_OPCODE_SCS     ] = { false,  false,                  0,  1,  1 },
 109    [ TGSI_OPCODE_SEQ     ] = { false,  false,                  0,  1,  2 },
 110    [ TGSI_OPCODE_SGE     ] = { false,  false,                  0,  1,  2 },
 111    [ TGSI_OPCODE_SGT     ] = { false,  false,                  0,  1,  2 },
 112    [ TGSI_OPCODE_SIN     ] = { false,  false,                  0,  1,  1 },
 113    [ TGSI_OPCODE_SLE     ] = { false,  false,                  0,  1,  2 },
 114    [ TGSI_OPCODE_SLT     ] = { false,  false,                  0,  1,  2 },
 115    [ TGSI_OPCODE_SNE     ] = { false,  false,                  0,  1,  2 },
 116    [ TGSI_OPCODE_SSG     ] = { false,  false,                  0,  1,  1 },
 117    [ TGSI_OPCODE_TEX     ] = {  true,  false,                  0,  1,  2 },
 118    [ TGSI_OPCODE_TRUNC   ] = { false,  false,                  0,  1,  1 },
 119    [ TGSI_OPCODE_TXB     ] = {  true,  false,                  0,  1,  2 },
 120    [ TGSI_OPCODE_TXP     ] = {  true,  false,                  0,  1,  2 },
 121    [ TGSI_OPCODE_XPD     ] = { false,  false,                  0,  1,  2 },
 122 };
 123
 124 static boolean op_has_dst(unsigned opcode)
 125 {
 126    return (op_table[opcode].num_dst > 0);
 127 }
 128
 129 static int op_num_dst(unsigned opcode)
 130 {
 131    return op_table[opcode].num_dst;
 132 }
 133
 134 static int op_num_src(unsigned opcode)
 135 {
 136    return op_table[opcode].num_src;
 137 }
 138
 139 static boolean op_commutes(unsigned opcode)
 140 {
 141    return op_table[opcode].commutes;
 142 }
 143
 144 static unsigned mask_for_unswizzled(int num_components)
 145 {
 146    unsigned mask = 0;
 147    switch(num_components)
 148    {
 149       case 4:
 150          mask |= TGSI_WRITEMASK_W;
 151       case 3:
 152          mask |= TGSI_WRITEMASK_Z;
 153       case 2:
 154          mask |= TGSI_WRITEMASK_Y;
 155       case 1:
 156          mask |= TGSI_WRITEMASK_X;
 157    }
 158    return mask;
 159 }
 160
 161 static boolean is_unswizzled(struct i915_full_src_register *r,
 162                              unsigned write_mask)
 163 {
 164    if ( write_mask & TGSI_WRITEMASK_X && r->Register.SwizzleX != TGSI_SWIZZLE_X)
 165       return FALSE;
 166    if ( write_mask & TGSI_WRITEMASK_Y && r->Register.SwizzleY != TGSI_SWIZZLE_Y)
 167       return FALSE;
 168    if ( write_mask & TGSI_WRITEMASK_Z && r->Register.SwizzleZ != TGSI_SWIZZLE_Z)
 169       return FALSE;
 170    if ( write_mask & TGSI_WRITEMASK_W && r->Register.SwizzleW != TGSI_SWIZZLE_W)
 171       return FALSE;
 172    return TRUE;
 173 }
 174
 175 static boolean op_is_texture(unsigned opcode)
 176 {
 177    return op_table[opcode].is_texture;
 178 }
 179
 180 static unsigned op_neutral_element(unsigned opcode)
 181 {
 182    unsigned ne = op_table[opcode].neutral_element;
 183    if (!ne) {
 184       debug_printf("No neutral element for opcode %d\n",opcode);
 185       ne = TGSI_SWIZZLE_ZERO;
 186    }
 187    return ne;
 188 }
 189
 190 /*
 191  * Sets the swizzle to the neutral element for the operation for the bits
 192  * of writemask which are set, swizzle to identity otherwise.
 193  */
 194 static void set_neutral_element_swizzle(struct i915_full_src_register *r,
 195                                         unsigned write_mask,
 196                                         unsigned neutral)
 197 {
 198    if ( write_mask & TGSI_WRITEMASK_X )
 199       r->Register.SwizzleX = neutral;
 200    else
 201       r->Register.SwizzleX = TGSI_SWIZZLE_X;
 202
 203    if ( write_mask & TGSI_WRITEMASK_Y )
 204       r->Register.SwizzleY = neutral;
 205    else
 206       r->Register.SwizzleY = TGSI_SWIZZLE_Y;
 207
 208    if ( write_mask & TGSI_WRITEMASK_Z )
 209       r->Register.SwizzleZ = neutral;
 210    else
 211       r->Register.SwizzleZ = TGSI_SWIZZLE_Z;
 212
 213    if ( write_mask & TGSI_WRITEMASK_W )
 214       r->Register.SwizzleW = neutral;
 215    else
 216       r->Register.SwizzleW = TGSI_SWIZZLE_W;
 217 }
 218
 219 static void copy_src_reg(struct i915_src_register *o, const struct tgsi_src_register *i)
 220 {
 221    o->File      = i->File;
 222    o->Indirect  = i->Indirect;
 223    o->Dimension = i->Dimension;
 224    o->Index     = i->Index;
 225    o->SwizzleX  = i->SwizzleX;
 226    o->SwizzleY  = i->SwizzleY;
 227    o->SwizzleZ  = i->SwizzleZ;
 228    o->SwizzleW  = i->SwizzleW;
 229    o->Absolute  = i->Absolute;
 230    o->Negate    = i->Negate;
 231 }
 232
 233 static void copy_dst_reg(struct i915_dst_register *o, const struct tgsi_dst_register *i)
 234 {
 235    o->File      = i->File;
 236    o->WriteMask = i->WriteMask;
 237    o->Indirect  = i->Indirect;
 238    o->Dimension = i->Dimension;
 239    o->Index     = i->Index;
 240 }
 241
 242 static void copy_instruction(struct i915_full_instruction *o, const struct tgsi_full_instruction *i)
 243 {
 244    memcpy(&o->Instruction, &i->Instruction, sizeof(o->Instruction));
 245    memcpy(&o->Texture, &i->Texture, sizeof(o->Texture));
 246
 247    copy_dst_reg(&o->Dst[0].Register, &i->Dst[0].Register);
 248
 249    copy_src_reg(&o->Src[0].Register, &i->Src[0].Register);
 250    copy_src_reg(&o->Src[1].Register, &i->Src[1].Register);
 251    copy_src_reg(&o->Src[2].Register, &i->Src[2].Register);
 252 }
 253
 254 static void copy_token(union i915_full_token *o, union tgsi_full_token *i)
 255 {
 256    if (i->Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
 257       memcpy(o, i, sizeof(*o));
 258    else
 259       copy_instruction(&o->FullInstruction, &i->FullInstruction);
 260
 261 }
 262
 263 static void liveness_mark_written(struct i915_optimize_context *ctx,
 264                                   struct i915_full_dst_register *dst_reg,
 265                                   int pos)
 266 {
 267    int dst_reg_index;
 268    if (dst_reg->Register.File == TGSI_FILE_TEMPORARY) {
 269       dst_reg_index = dst_reg->Register.Index;
 270       assert(dst_reg_index < TGSI_EXEC_NUM_TEMPS);
 271       /* dead -> live transition */
 272       if (ctx->first_write[dst_reg_index] != -1)
 273          ctx->first_write[dst_reg_index] = pos;
 274    }
 275 }
 276
 277 static void liveness_mark_read(struct i915_optimize_context *ctx,
 278                                struct i915_full_src_register *src_reg,
 279                                int pos)
 280 {
 281    int src_reg_index;
 282    if (src_reg->Register.File == TGSI_FILE_TEMPORARY) {
 283       src_reg_index = src_reg->Register.Index;
 284       assert(src_reg_index < TGSI_EXEC_NUM_TEMPS);
 285       /* live -> dead transition */
 286       if (ctx->last_read[src_reg_index] != -1)
 287          ctx->last_read[src_reg_index] = pos;
 288    }
 289 }
 290
 291 static void liveness_analysis(struct i915_optimize_context *ctx,
 292                               struct i915_token_list *tokens)
 293 {
 294    struct i915_full_dst_register *dst_reg;
 295    struct i915_full_src_register *src_reg;
 296    union i915_full_token *current;
 297    unsigned opcode;
 298    int num_dst, num_src;
 299    int i = 0;
 300
 301    for(i = 0; i < TGSI_EXEC_NUM_TEMPS; i++)
 302    {
 303       ctx->first_write[i] = -1;
 304       ctx->last_read[i] = -1;
 305    }
 306
 307    for(i = 0; i < tokens->NumTokens; i++)
 308    {
 309       current = &tokens->Tokens[i];
 310
 311       if (current->Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
 312          continue;
 313
 314       opcode = current->FullInstruction.Instruction.Opcode;
 315       num_dst = op_num_dst(opcode);
 316
 317       switch(num_dst)
 318       {
 319          case 1:
 320             dst_reg = &current->FullInstruction.Dst[0];
 321             liveness_mark_written(ctx, dst_reg, i);
 322          case 0:
 323             break;
 324          default:
 325             debug_printf("Op %d has %d dst regs\n", opcode, num_dst);
 326             break;
 327       }
 328    }
 329
 330    for(i = tokens->NumTokens - 1; i >= 0; i--)
 331    {
 332       current = &tokens->Tokens[i];
 333
 334       if (current->Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
 335          continue;
 336
 337       opcode = current->FullInstruction.Instruction.Opcode;
 338       num_src = op_num_src(opcode);
 339
 340       switch(num_src)
 341       {
 342          case 3:
 343             src_reg = &current->FullInstruction.Src[2];
 344             liveness_mark_read(ctx, src_reg, i);
 345          case 2:
 346             src_reg = &current->FullInstruction.Src[1];
 347             liveness_mark_read(ctx, src_reg, i);
 348          case 1:
 349             src_reg = &current->FullInstruction.Src[0];
 350             liveness_mark_read(ctx, src_reg, i);
 351          case 0:
 352             break;
 353          default:
 354             debug_printf("Op %d has %d src regs\n", opcode, num_src);
 355             break;
 356       }
 357    }
 358 }
 359
 360 static int unused_from(struct i915_optimize_context *ctx, struct i915_full_dst_register *dst_reg, int from)
 361 {
 362    int dst_reg_index = dst_reg->Register.Index;
 363    assert(dst_reg_index < TGSI_EXEC_NUM_TEMPS);
 364    return (from >= ctx->last_read[dst_reg_index]);
 365 }
 366
 367 /* Returns a mask with the components used for a texture access instruction */
 368 static unsigned i915_tex_mask(union i915_full_token *instr)
 369 {
 370    unsigned mask;
 371
 372    /* Get the number of coords */
 373    mask = mask_for_unswizzled(i915_num_coords(instr->FullInstruction.Texture.Texture));
 374
 375    /* Add the W component if projective */
 376    if (instr->FullInstruction.Instruction.Opcode == TGSI_OPCODE_TXP)
 377       mask |= TGSI_WRITEMASK_W;
 378
 379    return mask;
 380 }
 381
 382 static boolean target_is_texture2d(uint tex)
 383 {
 384    switch (tex) {
 385    case TGSI_TEXTURE_2D:
 386    case TGSI_TEXTURE_RECT:
 387       return true;
 388    default:
 389       return false;
 390    }
 391 }
 392
 393
 394 /*
 395  * Optimize away useless indirect texture reads:
 396  *    MOV TEMP[0].xy, IN[0].xyyy
 397  *    TEX TEMP[1], TEMP[0], SAMP[0], 2D
 398  * into:
 399  *    TEX TEMP[1], IN[0], SAMP[0], 2D
 400  *
 401  * note: this only seems to work on 2D/RECT textures, but not SHAADOW2D/1D/..
 402  */
 403 static void i915_fpc_optimize_mov_before_tex(struct i915_optimize_context *ctx,
 404                                              struct i915_token_list *tokens,
 405                                              int index)
 406 {
 407    union i915_full_token *current = &tokens->Tokens[index - 1];
 408    union i915_full_token *next = &tokens->Tokens[index];
 409
 410    if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 411         next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 412         current->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 413         op_is_texture(next->FullInstruction.Instruction.Opcode) &&
 414         target_is_texture2d(next->FullInstruction.Texture.Texture) &&
 415         same_src_dst_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Dst[0]) &&
 416         is_unswizzled(&current->FullInstruction.Src[0], i915_tex_mask(next)) &&
 417         unused_from(ctx, &current->FullInstruction.Dst[0], index))
 418    {
 419       memcpy(&next->FullInstruction.Src[0], &current->FullInstruction.Src[0], sizeof(struct i915_src_register));
 420       current->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
 421    }
 422 }
 423
 424 /*
 425  * Optimize away things like:
 426  *    MOV TEMP[0].xy, TEMP[1].xyyy (first write for TEMP[0])
 427  *    MOV TEMP[0].w, TEMP[1].wwww (last write for TEMP[0])
 428  * into:
 429  *    NOP
 430  *    MOV OUT[0].xyw, TEMP[1].xyww
 431  */
 432 static void i915_fpc_optimize_mov_after_mov(union i915_full_token *current, union i915_full_token *next)
 433 {
 434    struct i915_full_src_register *src_reg1, *src_reg2;
 435    struct i915_full_dst_register *dst_reg1, *dst_reg2;
 436    unsigned swizzle_x, swizzle_y, swizzle_z, swizzle_w;
 437
 438    if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 439         next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 440         current->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 441         next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 442         current->FullInstruction.Instruction.Saturate == next->FullInstruction.Instruction.Saturate &&
 443         same_dst_reg(&next->FullInstruction.Dst[0], &current->FullInstruction.Dst[0]) &&
 444         same_src_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Src[0]) &&
 445         !same_src_dst_reg(&current->FullInstruction.Src[0], &current->FullInstruction.Dst[0]) )
 446    {
 447       src_reg1 = &current->FullInstruction.Src[0];
 448       dst_reg1 = &current->FullInstruction.Dst[0];
 449       src_reg2 = &next->FullInstruction.Src[0];
 450       dst_reg2 = &next->FullInstruction.Dst[0];
 451
 452       /* Start with swizzles from the first mov */
 453       swizzle_x = src_reg1->Register.SwizzleX;
 454       swizzle_y = src_reg1->Register.SwizzleY;
 455       swizzle_z = src_reg1->Register.SwizzleZ;
 456       swizzle_w = src_reg1->Register.SwizzleW;
 457
 458       /* Pile the second mov on top */
 459       if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_X)
 460          swizzle_x = src_reg2->Register.SwizzleX;
 461       if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Y)
 462          swizzle_y = src_reg2->Register.SwizzleY;
 463       if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Z)
 464          swizzle_z = src_reg2->Register.SwizzleZ;
 465       if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_W)
 466          swizzle_w = src_reg2->Register.SwizzleW;
 467
 468       dst_reg2->Register.WriteMask |= dst_reg1->Register.WriteMask;
 469       src_reg2->Register.SwizzleX = swizzle_x;
 470       src_reg2->Register.SwizzleY = swizzle_y;
 471       src_reg2->Register.SwizzleZ = swizzle_z;
 472       src_reg2->Register.SwizzleW = swizzle_w;
 473
 474       current->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
 475
 476       return;
 477    }
 478 }
 479
 480 /*
 481  * Optimize away things like:
 482  *    MUL OUT[0].xyz, TEMP[1], TEMP[2]
 483  *    MOV OUT[0].w, TEMP[2]
 484  * into:
 485  *    MUL OUT[0].xyzw, TEMP[1].xyz1, TEMP[2]
 486  * This is useful for optimizing texenv.
 487  */
 488 static void i915_fpc_optimize_mov_after_alu(union i915_full_token *current, union i915_full_token *next)
 489 {
 490    if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 491         next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 492         op_commutes(current->FullInstruction.Instruction.Opcode) &&
 493         current->FullInstruction.Instruction.Saturate == next->FullInstruction.Instruction.Saturate &&
 494         next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 495         same_dst_reg(&next->FullInstruction.Dst[0], &current->FullInstruction.Dst[0]) &&
 496         same_src_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Src[1]) &&
 497         !same_src_dst_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Dst[0]) &&
 498         is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
 499         is_unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
 500         is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
 501    {
 502       next->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
 503
 504       set_neutral_element_swizzle(&current->FullInstruction.Src[1], 0, 0);
 505       set_neutral_element_swizzle(&current->FullInstruction.Src[0],
 506                                   next->FullInstruction.Dst[0].Register.WriteMask,
 507                                   op_neutral_element(current->FullInstruction.Instruction.Opcode));
 508
 509       current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
 510                                                            next->FullInstruction.Dst[0].Register.WriteMask;
 511       return;
 512    }
 513
 514    if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 515         next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 516         op_commutes(current->FullInstruction.Instruction.Opcode) &&
 517         current->FullInstruction.Instruction.Saturate == next->FullInstruction.Instruction.Saturate &&
 518         next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 519         same_dst_reg(&next->FullInstruction.Dst[0], &current->FullInstruction.Dst[0]) &&
 520         same_src_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Src[0]) &&
 521         !same_src_dst_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Dst[0]) &&
 522         is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
 523         is_unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
 524         is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
 525    {
 526       next->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
 527
 528       set_neutral_element_swizzle(&current->FullInstruction.Src[0], 0, 0);
 529       set_neutral_element_swizzle(&current->FullInstruction.Src[1],
 530                                   next->FullInstruction.Dst[0].Register.WriteMask,
 531                                   op_neutral_element(current->FullInstruction.Instruction.Opcode));
 532
 533       current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
 534                                                            next->FullInstruction.Dst[0].Register.WriteMask;
 535       return;
 536    }
 537 }
 538
 539 /*
 540  * Optimize away things like:
 541  *    MOV TEMP[0].xyz TEMP[0].xyzx
 542  * into:
 543  *    NOP
 544  */
 545 static boolean i915_fpc_useless_mov(union tgsi_full_token *tgsi_current)
 546 {
 547    union i915_full_token current;
 548    copy_token(&current , tgsi_current);
 549    if ( current.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 550         current.FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 551         op_has_dst(current.FullInstruction.Instruction.Opcode) &&
 552         !current.FullInstruction.Instruction.Saturate &&
 553         current.FullInstruction.Src[0].Register.Absolute == 0 &&
 554         current.FullInstruction.Src[0].Register.Negate == 0 &&
 555         is_unswizzled(&current.FullInstruction.Src[0], current.FullInstruction.Dst[0].Register.WriteMask) &&
 556         same_src_dst_reg(&current.FullInstruction.Src[0], &current.FullInstruction.Dst[0]) )
 557    {
 558       return TRUE;
 559    }
 560    return FALSE;
 561 }
 562
 563 /*
 564  * Optimize away things like:
 565  *    *** TEMP[0], TEMP[1], TEMP[2]
 566  *    MOV OUT[0] TEMP[0]
 567  * into:
 568  *    *** OUT[0], TEMP[1], TEMP[2]
 569  */
 570 static void i915_fpc_optimize_useless_mov_after_inst(struct i915_optimize_context *ctx,
 571                                                      struct i915_token_list *tokens,
 572                                                      int index)
 573 {
 574    union i915_full_token *current = &tokens->Tokens[index - 1];
 575    union i915_full_token *next = &tokens->Tokens[index];
 576
 577    // &out_tokens->Tokens[i-1], &out_tokens->Tokens[i]);
 578    if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 579         next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
 580         next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
 581         op_has_dst(current->FullInstruction.Instruction.Opcode) &&
 582         !next->FullInstruction.Instruction.Saturate &&
 583         next->FullInstruction.Src[0].Register.Absolute == 0 &&
 584         next->FullInstruction.Src[0].Register.Negate == 0 &&
 585         unused_from(ctx, &current->FullInstruction.Dst[0], index) &&
 586         current->FullInstruction.Dst[0].Register.WriteMask == TGSI_WRITEMASK_XYZW &&
 587         is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) &&
 588         current->FullInstruction.Dst[0].Register.WriteMask == next->FullInstruction.Dst[0].Register.WriteMask &&
 589         same_src_dst_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Dst[0]) )
 590    {
 591       next->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
 592
 593       current->FullInstruction.Dst[0] = next->FullInstruction.Dst[0];
 594       return;
 595    }
 596 }
 597
 598 struct i915_token_list* i915_optimize(const struct tgsi_token *tokens)
 599 {
 600    struct i915_token_list *out_tokens = MALLOC(sizeof(struct i915_token_list));
 601    struct tgsi_parse_context parse;
 602    struct i915_optimize_context *ctx;
 603    int i = 0;
 604
 605    ctx = malloc(sizeof(*ctx));
 606
 607    out_tokens->NumTokens = 0;
 608
 609    /* Count the tokens */
 610    tgsi_parse_init( &parse, tokens );
 611    while( !tgsi_parse_end_of_tokens( &parse ) ) {
 612       tgsi_parse_token( &parse );
 613       out_tokens->NumTokens++;
 614    }
 615    tgsi_parse_free (&parse);
 616
 617    /* Allocate our tokens */
 618    out_tokens->Tokens = MALLOC(sizeof(union i915_full_token) * out_tokens->NumTokens);
 619
 620    tgsi_parse_init( &parse, tokens );
 621    while( !tgsi_parse_end_of_tokens( &parse ) ) {
 622       tgsi_parse_token( &parse );
 623
 624       if (i915_fpc_useless_mov(&parse.FullToken)) {
 625          out_tokens->NumTokens--;
 626          continue;
 627       }
 628
 629       copy_token(&out_tokens->Tokens[i] , &parse.FullToken);
 630
 631       i++;
 632    }
 633    tgsi_parse_free (&parse);
 634
 635    liveness_analysis(ctx, out_tokens);
 636
 637    i = 1;
 638    while( i < out_tokens->NumTokens) {
 639       i915_fpc_optimize_useless_mov_after_inst(ctx, out_tokens, i);
 640       i915_fpc_optimize_mov_after_alu(&out_tokens->Tokens[i-1], &out_tokens->Tokens[i]);
 641       i915_fpc_optimize_mov_after_mov(&out_tokens->Tokens[i-1], &out_tokens->Tokens[i]);
 642       i915_fpc_optimize_mov_before_tex(ctx, out_tokens, i);
 643       i++;
 644    }
 645
 646    free(ctx);
 647
 648    return out_tokens;
 649 }
 650
 651 void i915_optimize_free(struct i915_token_list *tokens)
 652 {
 653    free(tokens->Tokens);
 654    free(tokens);
 655 }
 656
 657