projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium: remove the swizzling parts of ExtSwizzle
[mesa.git] / src / gallium / drivers / i915 / i915_fpc_translate.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdarg.h>
30
31 #include "i915_reg.h"
32 #include "i915_context.h"
33 #include "i915_fpc.h"
34
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "draw/draw_vertex.h"
43
44
45 /**
46 * Simple pass-through fragment shader to use when we don't have
47 * a real shader (or it fails to compile for some reason).
48 */
49 static unsigned passthrough[] =
50 {
51 _3DSTATE_PIXEL_SHADER_PROGRAM | ((2*3)-1),
52
53 /* declare input color:
54 */
55 (D0_DCL |
56 (REG_TYPE_T << D0_TYPE_SHIFT) |
57 (T_DIFFUSE << D0_NR_SHIFT) |
58 D0_CHANNEL_ALL),
59 0,
60 0,
61
62 /* move to output color:
63 */
64 (A0_MOV |
65 (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
66 A0_DEST_CHANNEL_ALL |
67 (REG_TYPE_T << A0_SRC0_TYPE_SHIFT) |
68 (T_DIFFUSE << A0_SRC0_NR_SHIFT)),
69 0x01230000, /* .xyzw */
70 0
71 };
72
73
74 /* 1, -1/3!, 1/5!, -1/7! */
75 static const float sin_constants[4] = { 1.0,
76 -1.0f / (3 * 2 * 1),
77 1.0f / (5 * 4 * 3 * 2 * 1),
78 -1.0f / (7 * 6 * 5 * 4 * 3 * 2 * 1)
79 };
80
81 /* 1, -1/2!, 1/4!, -1/6! */
82 static const float cos_constants[4] = { 1.0,
83 -1.0f / (2 * 1),
84 1.0f / (4 * 3 * 2 * 1),
85 -1.0f / (6 * 5 * 4 * 3 * 2 * 1)
86 };
87
88
89
90 /**
91 * component-wise negation of ureg
92 */
93 static INLINE int
94 negate(int reg, int x, int y, int z, int w)
95 {
96 /* Another neat thing about the UREG representation */
97 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
98 ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) |
99 ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) |
100 ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT));
101 }
102
103
104 /**
105 * In the event of a translation failure, we'll generate a simple color
106 * pass-through program.
107 */
108 static void
109 i915_use_passthrough_shader(struct i915_fragment_shader *fs)
110 {
111 fs->program = (uint *) MALLOC(sizeof(passthrough));
112 if (fs->program) {
113 memcpy(fs->program, passthrough, sizeof(passthrough));
114 fs->program_len = Elements(passthrough);
115 }
116 fs->num_constants = 0;
117 }
118
119
120 void
121 i915_program_error(struct i915_fp_compile *p, const char *msg, ...)
122 {
123 va_list args;
124 char buffer[1024];
125
126 debug_printf("i915_program_error: ");
127 va_start( args, msg );
128 util_vsnprintf( buffer, sizeof(buffer), msg, args );
129 va_end( args );
130 debug_printf("%s", buffer);
131 debug_printf("\n");
132
133 p->error = 1;
134 }
135
136
137
138 /**
139 * Construct a ureg for the given source register. Will emit
140 * constants, apply swizzling and negation as needed.
141 */
142 static uint
143 src_vector(struct i915_fp_compile *p,
144 const struct tgsi_full_src_register *source)
145 {
146 uint index = source->SrcRegister.Index;
147 uint src = 0, sem_name, sem_ind;
148
149 switch (source->SrcRegister.File) {
150 case TGSI_FILE_TEMPORARY:
151 if (source->SrcRegister.Index >= I915_MAX_TEMPORARY) {
152 i915_program_error(p, "Exceeded max temporary reg");
153 return 0;
154 }
155 src = UREG(REG_TYPE_R, index);
156 break;
157 case TGSI_FILE_INPUT:
158 /* XXX: Packing COL1, FOGC into a single attribute works for
159 * texenv programs, but will fail for real fragment programs
160 * that use these attributes and expect them to be a full 4
161 * components wide. Could use a texcoord to pass these
162 * attributes if necessary, but that won't work in the general
163 * case.
164 *
165 * We also use a texture coordinate to pass wpos when possible.
166 */
167
168 sem_name = p->shader->info.input_semantic_name[index];
169 sem_ind = p->shader->info.input_semantic_index[index];
170
171 switch (sem_name) {
172 case TGSI_SEMANTIC_POSITION:
173 debug_printf("SKIP SEM POS\n");
174 /*
175 assert(p->wpos_tex != -1);
176 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
177 */
178 break;
179 case TGSI_SEMANTIC_COLOR:
180 if (sem_ind == 0) {
181 src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
182 }
183 else {
184 /* secondary color */
185 assert(sem_ind == 1);
186 src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
187 src = swizzle(src, X, Y, Z, ONE);
188 }
189 break;
190 case TGSI_SEMANTIC_FOG:
191 src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
192 src = swizzle(src, W, W, W, W);
193 break;
194 case TGSI_SEMANTIC_GENERIC:
195 /* usually a texcoord */
196 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind, D0_CHANNEL_ALL);
197 break;
198 default:
199 i915_program_error(p, "Bad source->Index");
200 return 0;
201 }
202 break;
203
204 case TGSI_FILE_IMMEDIATE:
205 assert(index < p->num_immediates);
206 index = p->immediates_map[index];
207 /* fall-through */
208 case TGSI_FILE_CONSTANT:
209 src = UREG(REG_TYPE_CONST, index);
210 break;
211
212 default:
213 i915_program_error(p, "Bad source->File");
214 return 0;
215 }
216
217 src = swizzle(src,
218 source->SrcRegister.SwizzleX,
219 source->SrcRegister.SwizzleY,
220 source->SrcRegister.SwizzleZ,
221 source->SrcRegister.SwizzleW);
222
223
224 /* There's both negate-all-components and per-component negation.
225 * Try to handle both here.
226 */
227 {
228 int nx = source->SrcRegisterExtSwz.NegateX;
229 int ny = source->SrcRegisterExtSwz.NegateY;
230 int nz = source->SrcRegisterExtSwz.NegateZ;
231 int nw = source->SrcRegisterExtSwz.NegateW;
232 if (source->SrcRegister.Negate) {
233 nx = !nx;
234 ny = !ny;
235 nz = !nz;
236 nw = !nw;
237 }
238 src = negate(src, nx, ny, nz, nw);
239 }
240
241 /* no abs() or post-abs negation */
242 #if 0
243 /* XXX assertions disabled to allow arbfplight.c to run */
244 /* XXX enable these assertions, or fix things */
245 assert(!source->SrcRegisterExtMod.Absolute);
246 assert(!source->SrcRegisterExtMod.Negate);
247 #endif
248 return src;
249 }
250
251
252 /**
253 * Construct a ureg for a destination register.
254 */
255 static uint
256 get_result_vector(struct i915_fp_compile *p,
257 const struct tgsi_full_dst_register *dest)
258 {
259 switch (dest->DstRegister.File) {
260 case TGSI_FILE_OUTPUT:
261 {
262 uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
263 switch (sem_name) {
264 case TGSI_SEMANTIC_POSITION:
265 return UREG(REG_TYPE_OD, 0);
266 case TGSI_SEMANTIC_COLOR:
267 return UREG(REG_TYPE_OC, 0);
268 default:
269 i915_program_error(p, "Bad inst->DstReg.Index/semantics");
270 return 0;
271 }
272 }
273 case TGSI_FILE_TEMPORARY:
274 return UREG(REG_TYPE_R, dest->DstRegister.Index);
275 default:
276 i915_program_error(p, "Bad inst->DstReg.File");
277 return 0;
278 }
279 }
280
281
282 /**
283 * Compute flags for saturation and writemask.
284 */
285 static uint
286 get_result_flags(const struct tgsi_full_instruction *inst)
287 {
288 const uint writeMask
289 = inst->FullDstRegisters[0].DstRegister.WriteMask;
290 uint flags = 0x0;
291
292 if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
293 flags |= A0_DEST_SATURATE;
294
295 if (writeMask & TGSI_WRITEMASK_X)
296 flags |= A0_DEST_CHANNEL_X;
297 if (writeMask & TGSI_WRITEMASK_Y)
298 flags |= A0_DEST_CHANNEL_Y;
299 if (writeMask & TGSI_WRITEMASK_Z)
300 flags |= A0_DEST_CHANNEL_Z;
301 if (writeMask & TGSI_WRITEMASK_W)
302 flags |= A0_DEST_CHANNEL_W;
303
304 return flags;
305 }
306
307
308 /**
309 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
310 */
311 static uint
312 translate_tex_src_target(struct i915_fp_compile *p, uint tex)
313 {
314 switch (tex) {
315 case TGSI_TEXTURE_SHADOW1D:
316 /* fall-through */
317 case TGSI_TEXTURE_1D:
318 return D0_SAMPLE_TYPE_2D;
319
320 case TGSI_TEXTURE_SHADOW2D:
321 /* fall-through */
322 case TGSI_TEXTURE_2D:
323 return D0_SAMPLE_TYPE_2D;
324
325 case TGSI_TEXTURE_SHADOWRECT:
326 /* fall-through */
327 case TGSI_TEXTURE_RECT:
328 return D0_SAMPLE_TYPE_2D;
329
330 case TGSI_TEXTURE_3D:
331 return D0_SAMPLE_TYPE_VOLUME;
332
333 case TGSI_TEXTURE_CUBE:
334 return D0_SAMPLE_TYPE_CUBE;
335
336 default:
337 i915_program_error(p, "TexSrc type");
338 return 0;
339 }
340 }
341
342
343 /**
344 * Generate texel lookup instruction.
345 */
346 static void
347 emit_tex(struct i915_fp_compile *p,
348 const struct tgsi_full_instruction *inst,
349 uint opcode)
350 {
351 uint texture = inst->InstructionExtTexture.Texture;
352 uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
353 uint tex = translate_tex_src_target( p, texture );
354 uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
355 uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
356
357 i915_emit_texld( p,
358 get_result_vector( p, &inst->FullDstRegisters[0] ),
359 get_result_flags( inst ),
360 sampler,
361 coord,
362 opcode);
363 }
364
365
366 /**
367 * Generate a simple arithmetic instruction
368 * \param opcode the i915 opcode
369 * \param numArgs the number of input/src arguments
370 */
371 static void
372 emit_simple_arith(struct i915_fp_compile *p,
373 const struct tgsi_full_instruction *inst,
374 uint opcode, uint numArgs)
375 {
376 uint arg1, arg2, arg3;
377
378 assert(numArgs <= 3);
379
380 arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
381 arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
382 arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
383
384 i915_emit_arith( p,
385 opcode,
386 get_result_vector( p, &inst->FullDstRegisters[0]),
387 get_result_flags( inst ), 0,
388 arg1,
389 arg2,
390 arg3 );
391 }
392
393
394 /** As above, but swap the first two src regs */
395 static void
396 emit_simple_arith_swap2(struct i915_fp_compile *p,
397 const struct tgsi_full_instruction *inst,
398 uint opcode, uint numArgs)
399 {
400 struct tgsi_full_instruction inst2;
401
402 assert(numArgs == 2);
403
404 /* transpose first two registers */
405 inst2 = *inst;
406 inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
407 inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
408
409 emit_simple_arith(p, &inst2, opcode, numArgs);
410 }
411
412
413 #ifndef M_PI
414 #define M_PI 3.14159265358979323846
415 #endif
416
417 /*
418 * Translate TGSI instruction to i915 instruction.
419 *
420 * Possible concerns:
421 *
422 * SIN, COS -- could use another taylor step?
423 * LIT -- results seem a little different to sw mesa
424 * LOG -- different to mesa on negative numbers, but this is conformant.
425 */
426 static void
427 i915_translate_instruction(struct i915_fp_compile *p,
428 const struct tgsi_full_instruction *inst)
429 {
430 uint writemask;
431 uint src0, src1, src2, flags;
432 uint tmp = 0;
433
434 switch (inst->Instruction.Opcode) {
435 case TGSI_OPCODE_ABS:
436 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
437 i915_emit_arith(p,
438 A0_MAX,
439 get_result_vector(p, &inst->FullDstRegisters[0]),
440 get_result_flags(inst), 0,
441 src0, negate(src0, 1, 1, 1, 1), 0);
442 break;
443
444 case TGSI_OPCODE_ADD:
445 emit_simple_arith(p, inst, A0_ADD, 2);
446 break;
447
448 case TGSI_OPCODE_CMP:
449 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
450 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
451 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
452 i915_emit_arith(p, A0_CMP,
453 get_result_vector(p, &inst->FullDstRegisters[0]),
454 get_result_flags(inst),
455 0, src0, src2, src1); /* NOTE: order of src2, src1 */
456 break;
457
458 case TGSI_OPCODE_COS:
459 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
460 tmp = i915_get_utemp(p);
461
462 i915_emit_arith(p,
463 A0_MUL,
464 tmp, A0_DEST_CHANNEL_X, 0,
465 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
466
467 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
468
469 /* By choosing different taylor constants, could get rid of this mul:
470 */
471 i915_emit_arith(p,
472 A0_MUL,
473 tmp, A0_DEST_CHANNEL_X, 0,
474 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
475
476 /*
477 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
478 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
479 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
480 * result = DP4 t0, cos_constants
481 */
482 i915_emit_arith(p,
483 A0_MUL,
484 tmp, A0_DEST_CHANNEL_XY, 0,
485 swizzle(tmp, X, X, ONE, ONE),
486 swizzle(tmp, X, ONE, ONE, ONE), 0);
487
488 i915_emit_arith(p,
489 A0_MUL,
490 tmp, A0_DEST_CHANNEL_XYZ, 0,
491 swizzle(tmp, X, Y, X, ONE),
492 swizzle(tmp, X, X, ONE, ONE), 0);
493
494 i915_emit_arith(p,
495 A0_MUL,
496 tmp, A0_DEST_CHANNEL_XYZ, 0,
497 swizzle(tmp, X, X, Z, ONE),
498 swizzle(tmp, Z, ONE, ONE, ONE), 0);
499
500 i915_emit_arith(p,
501 A0_DP4,
502 get_result_vector(p, &inst->FullDstRegisters[0]),
503 get_result_flags(inst), 0,
504 swizzle(tmp, ONE, Z, Y, X),
505 i915_emit_const4fv(p, cos_constants), 0);
506 break;
507
508 case TGSI_OPCODE_DP3:
509 emit_simple_arith(p, inst, A0_DP3, 2);
510 break;
511
512 case TGSI_OPCODE_DP4:
513 emit_simple_arith(p, inst, A0_DP4, 2);
514 break;
515
516 case TGSI_OPCODE_DPH:
517 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
518 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
519
520 i915_emit_arith(p,
521 A0_DP4,
522 get_result_vector(p, &inst->FullDstRegisters[0]),
523 get_result_flags(inst), 0,
524 swizzle(src0, X, Y, Z, ONE), src1, 0);
525 break;
526
527 case TGSI_OPCODE_DST:
528 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
529 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
530
531 /* result[0] = 1 * 1;
532 * result[1] = a[1] * b[1];
533 * result[2] = a[2] * 1;
534 * result[3] = 1 * b[3];
535 */
536 i915_emit_arith(p,
537 A0_MUL,
538 get_result_vector(p, &inst->FullDstRegisters[0]),
539 get_result_flags(inst), 0,
540 swizzle(src0, ONE, Y, Z, ONE),
541 swizzle(src1, ONE, Y, ONE, W), 0);
542 break;
543
544 case TGSI_OPCODE_END:
545 /* no-op */
546 break;
547
548 case TGSI_OPCODE_EX2:
549 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
550
551 i915_emit_arith(p,
552 A0_EXP,
553 get_result_vector(p, &inst->FullDstRegisters[0]),
554 get_result_flags(inst), 0,
555 swizzle(src0, X, X, X, X), 0, 0);
556 break;
557
558 case TGSI_OPCODE_FLR:
559 emit_simple_arith(p, inst, A0_FLR, 1);
560 break;
561
562 case TGSI_OPCODE_FRC:
563 emit_simple_arith(p, inst, A0_FRC, 1);
564 break;
565
566 case TGSI_OPCODE_KIL:
567 /* kill if src[0].x < 0 || src[0].y < 0 ... */
568 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
569 tmp = i915_get_utemp(p);
570
571 i915_emit_texld(p,
572 tmp, /* dest reg: a dummy reg */
573 A0_DEST_CHANNEL_ALL, /* dest writemask */
574 0, /* sampler */
575 src0, /* coord*/
576 T0_TEXKILL); /* opcode */
577 break;
578
579 case TGSI_OPCODE_KILP:
580 assert(0); /* not tested yet */
581 break;
582
583 case TGSI_OPCODE_LG2:
584 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
585
586 i915_emit_arith(p,
587 A0_LOG,
588 get_result_vector(p, &inst->FullDstRegisters[0]),
589 get_result_flags(inst), 0,
590 swizzle(src0, X, X, X, X), 0, 0);
591 break;
592
593 case TGSI_OPCODE_LIT:
594 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
595 tmp = i915_get_utemp(p);
596
597 /* tmp = max( a.xyzw, a.00zw )
598 * XXX: Clamp tmp.w to -128..128
599 * tmp.y = log(tmp.y)
600 * tmp.y = tmp.w * tmp.y
601 * tmp.y = exp(tmp.y)
602 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
603 */
604 i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0,
605 src0, swizzle(src0, ZERO, ZERO, Z, W), 0);
606
607 i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0,
608 swizzle(tmp, Y, Y, Y, Y), 0, 0);
609
610 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0,
611 swizzle(tmp, ZERO, Y, ZERO, ZERO),
612 swizzle(tmp, ZERO, W, ZERO, ZERO), 0);
613
614 i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0,
615 swizzle(tmp, Y, Y, Y, Y), 0, 0);
616
617 i915_emit_arith(p, A0_CMP,
618 get_result_vector(p, &inst->FullDstRegisters[0]),
619 get_result_flags(inst), 0,
620 negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
621 swizzle(tmp, ONE, X, ZERO, ONE),
622 swizzle(tmp, ONE, X, Y, ONE));
623
624 break;
625
626 case TGSI_OPCODE_LRP:
627 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
628 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
629 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
630 flags = get_result_flags(inst);
631 tmp = i915_get_utemp(p);
632
633 /* b*a + c*(1-a)
634 *
635 * b*a + c - ca
636 *
637 * tmp = b*a + c,
638 * result = (-c)*a + tmp
639 */
640 i915_emit_arith(p, A0_MAD, tmp,
641 flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
642
643 i915_emit_arith(p, A0_MAD,
644 get_result_vector(p, &inst->FullDstRegisters[0]),
645 flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
646 break;
647
648 case TGSI_OPCODE_MAD:
649 emit_simple_arith(p, inst, A0_MAD, 3);
650 break;
651
652 case TGSI_OPCODE_MAX:
653 emit_simple_arith(p, inst, A0_MAX, 2);
654 break;
655
656 case TGSI_OPCODE_MIN:
657 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
658 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
659 tmp = i915_get_utemp(p);
660 flags = get_result_flags(inst);
661
662 i915_emit_arith(p,
663 A0_MAX,
664 tmp, flags & A0_DEST_CHANNEL_ALL, 0,
665 negate(src0, 1, 1, 1, 1),
666 negate(src1, 1, 1, 1, 1), 0);
667
668 i915_emit_arith(p,
669 A0_MOV,
670 get_result_vector(p, &inst->FullDstRegisters[0]),
671 flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
672 break;
673
674 case TGSI_OPCODE_MOV:
675 emit_simple_arith(p, inst, A0_MOV, 1);
676 break;
677
678 case TGSI_OPCODE_MUL:
679 emit_simple_arith(p, inst, A0_MUL, 2);
680 break;
681
682 case TGSI_OPCODE_POW:
683 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
684 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
685 tmp = i915_get_utemp(p);
686 flags = get_result_flags(inst);
687
688 /* XXX: masking on intermediate values, here and elsewhere.
689 */
690 i915_emit_arith(p,
691 A0_LOG,
692 tmp, A0_DEST_CHANNEL_X, 0,
693 swizzle(src0, X, X, X, X), 0, 0);
694
695 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0);
696
697 i915_emit_arith(p,
698 A0_EXP,
699 get_result_vector(p, &inst->FullDstRegisters[0]),
700 flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
701 break;
702
703 case TGSI_OPCODE_RET:
704 /* XXX: no-op? */
705 break;
706
707 case TGSI_OPCODE_RCP:
708 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
709
710 i915_emit_arith(p,
711 A0_RCP,
712 get_result_vector(p, &inst->FullDstRegisters[0]),
713 get_result_flags(inst), 0,
714 swizzle(src0, X, X, X, X), 0, 0);
715 break;
716
717 case TGSI_OPCODE_RSQ:
718 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
719
720 i915_emit_arith(p,
721 A0_RSQ,
722 get_result_vector(p, &inst->FullDstRegisters[0]),
723 get_result_flags(inst), 0,
724 swizzle(src0, X, X, X, X), 0, 0);
725 break;
726
727 case TGSI_OPCODE_SCS:
728 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
729 tmp = i915_get_utemp(p);
730
731 /*
732 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
733 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
734 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
735 * scs.x = DP4 t1, sin_constants
736 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
737 * scs.y = DP4 t1, cos_constants
738 */
739 i915_emit_arith(p,
740 A0_MUL,
741 tmp, A0_DEST_CHANNEL_XY, 0,
742 swizzle(src0, X, X, ONE, ONE),
743 swizzle(src0, X, ONE, ONE, ONE), 0);
744
745 i915_emit_arith(p,
746 A0_MUL,
747 tmp, A0_DEST_CHANNEL_ALL, 0,
748 swizzle(tmp, X, Y, X, Y),
749 swizzle(tmp, X, X, ONE, ONE), 0);
750
751 writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
752
753 if (writemask & TGSI_WRITEMASK_Y) {
754 uint tmp1;
755
756 if (writemask & TGSI_WRITEMASK_X)
757 tmp1 = i915_get_utemp(p);
758 else
759 tmp1 = tmp;
760
761 i915_emit_arith(p,
762 A0_MUL,
763 tmp1, A0_DEST_CHANNEL_ALL, 0,
764 swizzle(tmp, X, Y, Y, W),
765 swizzle(tmp, X, Z, ONE, ONE), 0);
766
767 i915_emit_arith(p,
768 A0_DP4,
769 get_result_vector(p, &inst->FullDstRegisters[0]),
770 A0_DEST_CHANNEL_Y, 0,
771 swizzle(tmp1, W, Z, Y, X),
772 i915_emit_const4fv(p, sin_constants), 0);
773 }
774
775 if (writemask & TGSI_WRITEMASK_X) {
776 i915_emit_arith(p,
777 A0_MUL,
778 tmp, A0_DEST_CHANNEL_XYZ, 0,
779 swizzle(tmp, X, X, Z, ONE),
780 swizzle(tmp, Z, ONE, ONE, ONE), 0);
781
782 i915_emit_arith(p,
783 A0_DP4,
784 get_result_vector(p, &inst->FullDstRegisters[0]),
785 A0_DEST_CHANNEL_X, 0,
786 swizzle(tmp, ONE, Z, Y, X),
787 i915_emit_const4fv(p, cos_constants), 0);
788 }
789 break;
790
791 case TGSI_OPCODE_SGE:
792 emit_simple_arith(p, inst, A0_SGE, 2);
793 break;
794
795 case TGSI_OPCODE_SLE:
796 /* like SGE, but swap reg0, reg1 */
797 emit_simple_arith_swap2(p, inst, A0_SGE, 2);
798 break;
799
800 case TGSI_OPCODE_SIN:
801 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
802 tmp = i915_get_utemp(p);
803
804 i915_emit_arith(p,
805 A0_MUL,
806 tmp, A0_DEST_CHANNEL_X, 0,
807 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
808
809 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
810
811 /* By choosing different taylor constants, could get rid of this mul:
812 */
813 i915_emit_arith(p,
814 A0_MUL,
815 tmp, A0_DEST_CHANNEL_X, 0,
816 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
817
818 /*
819 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
820 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
821 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
822 * result = DP4 t1.wzyx, sin_constants
823 */
824 i915_emit_arith(p,
825 A0_MUL,
826 tmp, A0_DEST_CHANNEL_XY, 0,
827 swizzle(tmp, X, X, ONE, ONE),
828 swizzle(tmp, X, ONE, ONE, ONE), 0);
829
830 i915_emit_arith(p,
831 A0_MUL,
832 tmp, A0_DEST_CHANNEL_ALL, 0,
833 swizzle(tmp, X, Y, X, Y),
834 swizzle(tmp, X, X, ONE, ONE), 0);
835
836 i915_emit_arith(p,
837 A0_MUL,
838 tmp, A0_DEST_CHANNEL_ALL, 0,
839 swizzle(tmp, X, Y, Y, W),
840 swizzle(tmp, X, Z, ONE, ONE), 0);
841
842 i915_emit_arith(p,
843 A0_DP4,
844 get_result_vector(p, &inst->FullDstRegisters[0]),
845 get_result_flags(inst), 0,
846 swizzle(tmp, W, Z, Y, X),
847 i915_emit_const4fv(p, sin_constants), 0);
848 break;
849
850 case TGSI_OPCODE_SLT:
851 emit_simple_arith(p, inst, A0_SLT, 2);
852 break;
853
854 case TGSI_OPCODE_SGT:
855 /* like SLT, but swap reg0, reg1 */
856 emit_simple_arith_swap2(p, inst, A0_SLT, 2);
857 break;
858
859 case TGSI_OPCODE_SUB:
860 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
861 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
862
863 i915_emit_arith(p,
864 A0_ADD,
865 get_result_vector(p, &inst->FullDstRegisters[0]),
866 get_result_flags(inst), 0,
867 src0, negate(src1, 1, 1, 1, 1), 0);
868 break;
869
870 case TGSI_OPCODE_TEX:
871 emit_tex(p, inst, T0_TEXLD);
872 break;
873
874 case TGSI_OPCODE_TXB:
875 emit_tex(p, inst, T0_TEXLDB);
876 break;
877
878 case TGSI_OPCODE_TXP:
879 emit_tex(p, inst, T0_TEXLDP);
880 break;
881
882 case TGSI_OPCODE_XPD:
883 /* Cross product:
884 * result.x = src0.y * src1.z - src0.z * src1.y;
885 * result.y = src0.z * src1.x - src0.x * src1.z;
886 * result.z = src0.x * src1.y - src0.y * src1.x;
887 * result.w = undef;
888 */
889 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
890 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
891 tmp = i915_get_utemp(p);
892
893 i915_emit_arith(p,
894 A0_MUL,
895 tmp, A0_DEST_CHANNEL_ALL, 0,
896 swizzle(src0, Z, X, Y, ONE),
897 swizzle(src1, Y, Z, X, ONE), 0);
898
899 i915_emit_arith(p,
900 A0_MAD,
901 get_result_vector(p, &inst->FullDstRegisters[0]),
902 get_result_flags(inst), 0,
903 swizzle(src0, Y, Z, X, ONE),
904 swizzle(src1, Z, X, Y, ONE),
905 negate(tmp, 1, 1, 1, 0));
906 break;
907
908 default:
909 i915_program_error(p, "bad opcode %d", inst->Instruction.Opcode);
910 p->error = 1;
911 return;
912 }
913
914 i915_release_utemps(p);
915 }
916
917
918 /**
919 * Translate TGSI fragment shader into i915 hardware instructions.
920 * \param p the translation state
921 * \param tokens the TGSI token array
922 */
923 static void
924 i915_translate_instructions(struct i915_fp_compile *p,
925 const struct tgsi_token *tokens)
926 {
927 struct i915_fragment_shader *ifs = p->shader;
928 struct tgsi_parse_context parse;
929
930 tgsi_parse_init( &parse, tokens );
931
932 while( !tgsi_parse_end_of_tokens( &parse ) ) {
933
934 tgsi_parse_token( &parse );
935
936 switch( parse.FullToken.Token.Type ) {
937 case TGSI_TOKEN_TYPE_DECLARATION:
938 if (parse.FullToken.FullDeclaration.Declaration.File
939 == TGSI_FILE_CONSTANT) {
940 uint i;
941 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
942 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
943 i++) {
944 assert(ifs->constant_flags[i] == 0x0);
945 ifs->constant_flags[i] = I915_CONSTFLAG_USER;
946 ifs->num_constants = MAX2(ifs->num_constants, i + 1);
947 }
948 }
949 else if (parse.FullToken.FullDeclaration.Declaration.File
950 == TGSI_FILE_TEMPORARY) {
951 uint i;
952 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
953 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
954 i++) {
955 assert(i < I915_MAX_TEMPORARY);
956 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
957 p->temp_flag |= (1 << i); /* mark temp as used */
958 }
959 }
960 break;
961
962 case TGSI_TOKEN_TYPE_IMMEDIATE:
963 {
964 const struct tgsi_full_immediate *imm
965 = &parse.FullToken.FullImmediate;
966 const uint pos = p->num_immediates++;
967 uint j;
968 assert( imm->Immediate.NrTokens <= 4 + 1 );
969 for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
970 p->immediates[pos][j] = imm->u[j].Float;
971 }
972 }
973 break;
974
975 case TGSI_TOKEN_TYPE_INSTRUCTION:
976 if (p->first_instruction) {
977 /* resolve location of immediates */
978 uint i, j;
979 for (i = 0; i < p->num_immediates; i++) {
980 /* find constant slot for this immediate */
981 for (j = 0; j < I915_MAX_CONSTANT; j++) {
982 if (ifs->constant_flags[j] == 0x0) {
983 memcpy(ifs->constants[j],
984 p->immediates[i],
985 4 * sizeof(float));
986 /*printf("immediate %d maps to const %d\n", i, j);*/
987 ifs->constant_flags[j] = 0xf; /* all four comps used */
988 p->immediates_map[i] = j;
989 ifs->num_constants = MAX2(ifs->num_constants, j + 1);
990 break;
991 }
992 }
993 }
994
995 p->first_instruction = FALSE;
996 }
997
998 i915_translate_instruction(p, &parse.FullToken.FullInstruction);
999 break;
1000
1001 default:
1002 assert( 0 );
1003 }
1004
1005 } /* while */
1006
1007 tgsi_parse_free (&parse);
1008 }
1009
1010
1011 static struct i915_fp_compile *
1012 i915_init_compile(struct i915_context *i915,
1013 struct i915_fragment_shader *ifs)
1014 {
1015 struct i915_fp_compile *p = CALLOC_STRUCT(i915_fp_compile);
1016
1017 p->shader = ifs;
1018
1019 /* Put new constants at end of const buffer, growing downward.
1020 * The problem is we don't know how many user-defined constants might
1021 * be specified with pipe->set_constant_buffer().
1022 * Should pre-scan the user's program to determine the highest-numbered
1023 * constant referenced.
1024 */
1025 ifs->num_constants = 0;
1026 memset(ifs->constant_flags, 0, sizeof(ifs->constant_flags));
1027
1028 p->first_instruction = TRUE;
1029
1030 p->nr_tex_indirect = 1; /* correct? */
1031 p->nr_tex_insn = 0;
1032 p->nr_alu_insn = 0;
1033 p->nr_decl_insn = 0;
1034
1035 p->csr = p->program;
1036 p->decl = p->declarations;
1037 p->decl_s = 0;
1038 p->decl_t = 0;
1039 p->temp_flag = ~0x0 << I915_MAX_TEMPORARY;
1040 p->utemp_flag = ~0x7;
1041
1042 p->wpos_tex = -1;
1043
1044 /* initialize the first program word */
1045 *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM;
1046
1047 return p;
1048 }
1049
1050
1051 /* Copy compile results to the fragment program struct and destroy the
1052 * compilation context.
1053 */
1054 static void
1055 i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p)
1056 {
1057 struct i915_fragment_shader *ifs = p->shader;
1058 unsigned long program_size = (unsigned long) (p->csr - p->program);
1059 unsigned long decl_size = (unsigned long) (p->decl - p->declarations);
1060
1061 if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
1062 i915_program_error(p, "Exceeded max nr indirect texture lookups");
1063
1064 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
1065 i915_program_error(p, "Exceeded max TEX instructions");
1066
1067 if (p->nr_alu_insn > I915_MAX_ALU_INSN)
1068 i915_program_error(p, "Exceeded max ALU instructions");
1069
1070 if (p->nr_decl_insn > I915_MAX_DECL_INSN)
1071 i915_program_error(p, "Exceeded max DECL instructions");
1072
1073 if (p->error) {
1074 p->NumNativeInstructions = 0;
1075 p->NumNativeAluInstructions = 0;
1076 p->NumNativeTexInstructions = 0;
1077 p->NumNativeTexIndirections = 0;
1078
1079 i915_use_passthrough_shader(ifs);
1080 }
1081 else {
1082 p->NumNativeInstructions
1083 = p->nr_alu_insn + p->nr_tex_insn + p->nr_decl_insn;
1084 p->NumNativeAluInstructions = p->nr_alu_insn;
1085 p->NumNativeTexInstructions = p->nr_tex_insn;
1086 p->NumNativeTexIndirections = p->nr_tex_indirect;
1087
1088 /* patch in the program length */
1089 p->declarations[0] |= program_size + decl_size - 2;
1090
1091 /* Copy compilation results to fragment program struct:
1092 */
1093 assert(!ifs->program);
1094 ifs->program
1095 = (uint *) MALLOC((program_size + decl_size) * sizeof(uint));
1096 if (ifs->program) {
1097 ifs->program_len = program_size + decl_size;
1098
1099 memcpy(ifs->program,
1100 p->declarations,
1101 decl_size * sizeof(uint));
1102
1103 memcpy(ifs->program + decl_size,
1104 p->program,
1105 program_size * sizeof(uint));
1106 }
1107 }
1108
1109 /* Release the compilation struct:
1110 */
1111 FREE(p);
1112 }
1113
1114
1115 /**
1116 * Find an unused texture coordinate slot to use for fragment WPOS.
1117 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1118 */
1119 static void
1120 i915_find_wpos_space(struct i915_fp_compile *p)
1121 {
1122 #if 0
1123 const uint inputs
1124 = p->shader->inputs_read | (1 << TGSI_ATTRIB_POS); /*XXX hack*/
1125 uint i;
1126
1127 p->wpos_tex = -1;
1128
1129 if (inputs & (1 << TGSI_ATTRIB_POS)) {
1130 for (i = 0; i < I915_TEX_UNITS; i++) {
1131 if ((inputs & (1 << (TGSI_ATTRIB_TEX0 + i))) == 0) {
1132 p->wpos_tex = i;
1133 return;
1134 }
1135 }
1136
1137 i915_program_error(p, "No free texcoord for wpos value");
1138 }
1139 #else
1140 if (p->shader->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1141 /* frag shader using the fragment position input */
1142 #if 0
1143 assert(0);
1144 #endif
1145 }
1146 #endif
1147 }
1148
1149
1150
1151
1152 /**
1153 * Rather than trying to intercept and jiggle depth writes during
1154 * emit, just move the value into its correct position at the end of
1155 * the program:
1156 */
1157 static void
1158 i915_fixup_depth_write(struct i915_fp_compile *p)
1159 {
1160 /* XXX assuming pos/depth is always in output[0] */
1161 if (p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1162 const uint depth = UREG(REG_TYPE_OD, 0);
1163
1164 i915_emit_arith(p,
1165 A0_MOV, /* opcode */
1166 depth, /* dest reg */
1167 A0_DEST_CHANNEL_W, /* write mask */
1168 0, /* saturate? */
1169 swizzle(depth, X, Y, Z, Z), /* src0 */
1170 0, 0 /* src1, src2 */);
1171 }
1172 }
1173
1174
1175 void
1176 i915_translate_fragment_program( struct i915_context *i915,
1177 struct i915_fragment_shader *fs)
1178 {
1179 struct i915_fp_compile *p = i915_init_compile(i915, fs);
1180 const struct tgsi_token *tokens = fs->state.tokens;
1181
1182 i915_find_wpos_space(p);
1183
1184 #if 0
1185 tgsi_dump(tokens, 0);
1186 #endif
1187
1188 i915_translate_instructions(p, tokens);
1189 i915_fixup_depth_write(p);
1190
1191 i915_fini_compile(i915, p);
1192 }