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[mesa.git] / src / gallium / drivers / i915 / i915_fpc_translate.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdarg.h>
30
31 #include "i915_reg.h"
32 #include "i915_context.h"
33 #include "i915_fpc.h"
34
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "draw/draw_vertex.h"
43
44
45 /**
46 * Simple pass-through fragment shader to use when we don't have
47 * a real shader (or it fails to compile for some reason).
48 */
49 static unsigned passthrough[] =
50 {
51 _3DSTATE_PIXEL_SHADER_PROGRAM | ((2*3)-1),
52
53 /* declare input color:
54 */
55 (D0_DCL |
56 (REG_TYPE_T << D0_TYPE_SHIFT) |
57 (T_DIFFUSE << D0_NR_SHIFT) |
58 D0_CHANNEL_ALL),
59 0,
60 0,
61
62 /* move to output color:
63 */
64 (A0_MOV |
65 (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
66 A0_DEST_CHANNEL_ALL |
67 (REG_TYPE_T << A0_SRC0_TYPE_SHIFT) |
68 (T_DIFFUSE << A0_SRC0_NR_SHIFT)),
69 0x01230000, /* .xyzw */
70 0
71 };
72
73
74 /* 1, -1/3!, 1/5!, -1/7! */
75 static const float sin_constants[4] = { 1.0,
76 -1.0f / (3 * 2 * 1),
77 1.0f / (5 * 4 * 3 * 2 * 1),
78 -1.0f / (7 * 6 * 5 * 4 * 3 * 2 * 1)
79 };
80
81 /* 1, -1/2!, 1/4!, -1/6! */
82 static const float cos_constants[4] = { 1.0,
83 -1.0f / (2 * 1),
84 1.0f / (4 * 3 * 2 * 1),
85 -1.0f / (6 * 5 * 4 * 3 * 2 * 1)
86 };
87
88
89
90 /**
91 * component-wise negation of ureg
92 */
93 static INLINE int
94 negate(int reg, int x, int y, int z, int w)
95 {
96 /* Another neat thing about the UREG representation */
97 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
98 ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) |
99 ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) |
100 ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT));
101 }
102
103
104 /**
105 * In the event of a translation failure, we'll generate a simple color
106 * pass-through program.
107 */
108 static void
109 i915_use_passthrough_shader(struct i915_fragment_shader *fs)
110 {
111 fs->program = (uint *) MALLOC(sizeof(passthrough));
112 if (fs->program) {
113 memcpy(fs->program, passthrough, sizeof(passthrough));
114 fs->program_len = Elements(passthrough);
115 }
116 fs->num_constants = 0;
117 }
118
119
120 void
121 i915_program_error(struct i915_fp_compile *p, const char *msg, ...)
122 {
123 va_list args;
124 char buffer[1024];
125
126 debug_printf("i915_program_error: ");
127 va_start( args, msg );
128 util_vsnprintf( buffer, sizeof(buffer), msg, args );
129 va_end( args );
130 debug_printf("%s", buffer);
131 debug_printf("\n");
132
133 p->error = 1;
134 }
135
136
137
138 /**
139 * Construct a ureg for the given source register. Will emit
140 * constants, apply swizzling and negation as needed.
141 */
142 static uint
143 src_vector(struct i915_fp_compile *p,
144 const struct tgsi_full_src_register *source)
145 {
146 uint index = source->Register.Index;
147 uint src = 0, sem_name, sem_ind;
148
149 switch (source->Register.File) {
150 case TGSI_FILE_TEMPORARY:
151 if (source->Register.Index >= I915_MAX_TEMPORARY) {
152 i915_program_error(p, "Exceeded max temporary reg");
153 return 0;
154 }
155 src = UREG(REG_TYPE_R, index);
156 break;
157 case TGSI_FILE_INPUT:
158 /* XXX: Packing COL1, FOGC into a single attribute works for
159 * texenv programs, but will fail for real fragment programs
160 * that use these attributes and expect them to be a full 4
161 * components wide. Could use a texcoord to pass these
162 * attributes if necessary, but that won't work in the general
163 * case.
164 *
165 * We also use a texture coordinate to pass wpos when possible.
166 */
167
168 sem_name = p->shader->info.input_semantic_name[index];
169 sem_ind = p->shader->info.input_semantic_index[index];
170
171 switch (sem_name) {
172 case TGSI_SEMANTIC_POSITION:
173 debug_printf("SKIP SEM POS\n");
174 /*
175 assert(p->wpos_tex != -1);
176 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
177 */
178 break;
179 case TGSI_SEMANTIC_COLOR:
180 if (sem_ind == 0) {
181 src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
182 }
183 else {
184 /* secondary color */
185 assert(sem_ind == 1);
186 src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
187 src = swizzle(src, X, Y, Z, ONE);
188 }
189 break;
190 case TGSI_SEMANTIC_FOG:
191 src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
192 src = swizzle(src, W, W, W, W);
193 break;
194 case TGSI_SEMANTIC_GENERIC:
195 if (sem_ind < 8)
196 /* a texcoord */
197 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind, D0_CHANNEL_ALL);
198 else if ( (sem_ind >= 10) && (sem_ind < 18) )
199 /* a varying */
200 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind - 10, D0_CHANNEL_ALL);
201 else
202 debug_printf("%s: unhandled generic %d\n", __func__, sem_ind);
203 break;
204 default:
205 i915_program_error(p, "Bad source->Index");
206 return 0;
207 }
208 break;
209
210 case TGSI_FILE_IMMEDIATE:
211 assert(index < p->num_immediates);
212 index = p->immediates_map[index];
213 /* fall-through */
214 case TGSI_FILE_CONSTANT:
215 src = UREG(REG_TYPE_CONST, index);
216 break;
217
218 default:
219 i915_program_error(p, "Bad source->File");
220 return 0;
221 }
222
223 src = swizzle(src,
224 source->Register.SwizzleX,
225 source->Register.SwizzleY,
226 source->Register.SwizzleZ,
227 source->Register.SwizzleW);
228
229
230 /* There's both negate-all-components and per-component negation.
231 * Try to handle both here.
232 */
233 {
234 int n = source->Register.Negate;
235 src = negate(src, n, n, n, n);
236 }
237
238 /* no abs() */
239 #if 0
240 /* XXX assertions disabled to allow arbfplight.c to run */
241 /* XXX enable these assertions, or fix things */
242 assert(!source->Register.Absolute);
243 #endif
244 return src;
245 }
246
247
248 /**
249 * Construct a ureg for a destination register.
250 */
251 static uint
252 get_result_vector(struct i915_fp_compile *p,
253 const struct tgsi_full_dst_register *dest)
254 {
255 switch (dest->Register.File) {
256 case TGSI_FILE_OUTPUT:
257 {
258 uint sem_name = p->shader->info.output_semantic_name[dest->Register.Index];
259 switch (sem_name) {
260 case TGSI_SEMANTIC_POSITION:
261 return UREG(REG_TYPE_OD, 0);
262 case TGSI_SEMANTIC_COLOR:
263 return UREG(REG_TYPE_OC, 0);
264 default:
265 i915_program_error(p, "Bad inst->DstReg.Index/semantics");
266 return 0;
267 }
268 }
269 case TGSI_FILE_TEMPORARY:
270 return UREG(REG_TYPE_R, dest->Register.Index);
271 default:
272 i915_program_error(p, "Bad inst->DstReg.File");
273 return 0;
274 }
275 }
276
277
278 /**
279 * Compute flags for saturation and writemask.
280 */
281 static uint
282 get_result_flags(const struct tgsi_full_instruction *inst)
283 {
284 const uint writeMask
285 = inst->Dst[0].Register.WriteMask;
286 uint flags = 0x0;
287
288 if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
289 flags |= A0_DEST_SATURATE;
290
291 if (writeMask & TGSI_WRITEMASK_X)
292 flags |= A0_DEST_CHANNEL_X;
293 if (writeMask & TGSI_WRITEMASK_Y)
294 flags |= A0_DEST_CHANNEL_Y;
295 if (writeMask & TGSI_WRITEMASK_Z)
296 flags |= A0_DEST_CHANNEL_Z;
297 if (writeMask & TGSI_WRITEMASK_W)
298 flags |= A0_DEST_CHANNEL_W;
299
300 return flags;
301 }
302
303
304 /**
305 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
306 */
307 static uint
308 translate_tex_src_target(struct i915_fp_compile *p, uint tex)
309 {
310 switch (tex) {
311 case TGSI_TEXTURE_SHADOW1D:
312 /* fall-through */
313 case TGSI_TEXTURE_1D:
314 return D0_SAMPLE_TYPE_2D;
315
316 case TGSI_TEXTURE_SHADOW2D:
317 /* fall-through */
318 case TGSI_TEXTURE_2D:
319 return D0_SAMPLE_TYPE_2D;
320
321 case TGSI_TEXTURE_SHADOWRECT:
322 /* fall-through */
323 case TGSI_TEXTURE_RECT:
324 return D0_SAMPLE_TYPE_2D;
325
326 case TGSI_TEXTURE_3D:
327 return D0_SAMPLE_TYPE_VOLUME;
328
329 case TGSI_TEXTURE_CUBE:
330 return D0_SAMPLE_TYPE_CUBE;
331
332 default:
333 i915_program_error(p, "TexSrc type");
334 return 0;
335 }
336 }
337
338
339 /**
340 * Generate texel lookup instruction.
341 */
342 static void
343 emit_tex(struct i915_fp_compile *p,
344 const struct tgsi_full_instruction *inst,
345 uint opcode)
346 {
347 uint texture = inst->Texture.Texture;
348 uint unit = inst->Src[1].Register.Index;
349 uint tex = translate_tex_src_target( p, texture );
350 uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
351 uint coord = src_vector( p, &inst->Src[0]);
352
353 i915_emit_texld( p,
354 get_result_vector( p, &inst->Dst[0] ),
355 get_result_flags( inst ),
356 sampler,
357 coord,
358 opcode);
359 }
360
361
362 /**
363 * Generate a simple arithmetic instruction
364 * \param opcode the i915 opcode
365 * \param numArgs the number of input/src arguments
366 */
367 static void
368 emit_simple_arith(struct i915_fp_compile *p,
369 const struct tgsi_full_instruction *inst,
370 uint opcode, uint numArgs)
371 {
372 uint arg1, arg2, arg3;
373
374 assert(numArgs <= 3);
375
376 arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->Src[0] );
377 arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->Src[1] );
378 arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->Src[2] );
379
380 i915_emit_arith( p,
381 opcode,
382 get_result_vector( p, &inst->Dst[0]),
383 get_result_flags( inst ), 0,
384 arg1,
385 arg2,
386 arg3 );
387 }
388
389
390 /** As above, but swap the first two src regs */
391 static void
392 emit_simple_arith_swap2(struct i915_fp_compile *p,
393 const struct tgsi_full_instruction *inst,
394 uint opcode, uint numArgs)
395 {
396 struct tgsi_full_instruction inst2;
397
398 assert(numArgs == 2);
399
400 /* transpose first two registers */
401 inst2 = *inst;
402 inst2.Src[0] = inst->Src[1];
403 inst2.Src[1] = inst->Src[0];
404
405 emit_simple_arith(p, &inst2, opcode, numArgs);
406 }
407
408
409 #ifndef M_PI
410 #define M_PI 3.14159265358979323846
411 #endif
412
413 /*
414 * Translate TGSI instruction to i915 instruction.
415 *
416 * Possible concerns:
417 *
418 * SIN, COS -- could use another taylor step?
419 * LIT -- results seem a little different to sw mesa
420 * LOG -- different to mesa on negative numbers, but this is conformant.
421 */
422 static void
423 i915_translate_instruction(struct i915_fp_compile *p,
424 const struct tgsi_full_instruction *inst)
425 {
426 uint writemask;
427 uint src0, src1, src2, flags;
428 uint tmp = 0;
429
430 switch (inst->Instruction.Opcode) {
431 case TGSI_OPCODE_ABS:
432 src0 = src_vector(p, &inst->Src[0]);
433 i915_emit_arith(p,
434 A0_MAX,
435 get_result_vector(p, &inst->Dst[0]),
436 get_result_flags(inst), 0,
437 src0, negate(src0, 1, 1, 1, 1), 0);
438 break;
439
440 case TGSI_OPCODE_ADD:
441 emit_simple_arith(p, inst, A0_ADD, 2);
442 break;
443
444 case TGSI_OPCODE_CMP:
445 src0 = src_vector(p, &inst->Src[0]);
446 src1 = src_vector(p, &inst->Src[1]);
447 src2 = src_vector(p, &inst->Src[2]);
448 i915_emit_arith(p, A0_CMP,
449 get_result_vector(p, &inst->Dst[0]),
450 get_result_flags(inst),
451 0, src0, src2, src1); /* NOTE: order of src2, src1 */
452 break;
453
454 case TGSI_OPCODE_COS:
455 src0 = src_vector(p, &inst->Src[0]);
456 tmp = i915_get_utemp(p);
457
458 i915_emit_arith(p,
459 A0_MUL,
460 tmp, A0_DEST_CHANNEL_X, 0,
461 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
462
463 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
464
465 /* By choosing different taylor constants, could get rid of this mul:
466 */
467 i915_emit_arith(p,
468 A0_MUL,
469 tmp, A0_DEST_CHANNEL_X, 0,
470 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
471
472 /*
473 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
474 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
475 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
476 * result = DP4 t0, cos_constants
477 */
478 i915_emit_arith(p,
479 A0_MUL,
480 tmp, A0_DEST_CHANNEL_XY, 0,
481 swizzle(tmp, X, X, ONE, ONE),
482 swizzle(tmp, X, ONE, ONE, ONE), 0);
483
484 i915_emit_arith(p,
485 A0_MUL,
486 tmp, A0_DEST_CHANNEL_XYZ, 0,
487 swizzle(tmp, X, Y, X, ONE),
488 swizzle(tmp, X, X, ONE, ONE), 0);
489
490 i915_emit_arith(p,
491 A0_MUL,
492 tmp, A0_DEST_CHANNEL_XYZ, 0,
493 swizzle(tmp, X, X, Z, ONE),
494 swizzle(tmp, Z, ONE, ONE, ONE), 0);
495
496 i915_emit_arith(p,
497 A0_DP4,
498 get_result_vector(p, &inst->Dst[0]),
499 get_result_flags(inst), 0,
500 swizzle(tmp, ONE, Z, Y, X),
501 i915_emit_const4fv(p, cos_constants), 0);
502 break;
503
504 case TGSI_OPCODE_DP3:
505 emit_simple_arith(p, inst, A0_DP3, 2);
506 break;
507
508 case TGSI_OPCODE_DP4:
509 emit_simple_arith(p, inst, A0_DP4, 2);
510 break;
511
512 case TGSI_OPCODE_DPH:
513 src0 = src_vector(p, &inst->Src[0]);
514 src1 = src_vector(p, &inst->Src[1]);
515
516 i915_emit_arith(p,
517 A0_DP4,
518 get_result_vector(p, &inst->Dst[0]),
519 get_result_flags(inst), 0,
520 swizzle(src0, X, Y, Z, ONE), src1, 0);
521 break;
522
523 case TGSI_OPCODE_DST:
524 src0 = src_vector(p, &inst->Src[0]);
525 src1 = src_vector(p, &inst->Src[1]);
526
527 /* result[0] = 1 * 1;
528 * result[1] = a[1] * b[1];
529 * result[2] = a[2] * 1;
530 * result[3] = 1 * b[3];
531 */
532 i915_emit_arith(p,
533 A0_MUL,
534 get_result_vector(p, &inst->Dst[0]),
535 get_result_flags(inst), 0,
536 swizzle(src0, ONE, Y, Z, ONE),
537 swizzle(src1, ONE, Y, ONE, W), 0);
538 break;
539
540 case TGSI_OPCODE_END:
541 /* no-op */
542 break;
543
544 case TGSI_OPCODE_EX2:
545 src0 = src_vector(p, &inst->Src[0]);
546
547 i915_emit_arith(p,
548 A0_EXP,
549 get_result_vector(p, &inst->Dst[0]),
550 get_result_flags(inst), 0,
551 swizzle(src0, X, X, X, X), 0, 0);
552 break;
553
554 case TGSI_OPCODE_FLR:
555 emit_simple_arith(p, inst, A0_FLR, 1);
556 break;
557
558 case TGSI_OPCODE_FRC:
559 emit_simple_arith(p, inst, A0_FRC, 1);
560 break;
561
562 case TGSI_OPCODE_KIL:
563 /* kill if src[0].x < 0 || src[0].y < 0 ... */
564 src0 = src_vector(p, &inst->Src[0]);
565 tmp = i915_get_utemp(p);
566
567 i915_emit_texld(p,
568 tmp, /* dest reg: a dummy reg */
569 A0_DEST_CHANNEL_ALL, /* dest writemask */
570 0, /* sampler */
571 src0, /* coord*/
572 T0_TEXKILL); /* opcode */
573 break;
574
575 case TGSI_OPCODE_KILP:
576 assert(0); /* not tested yet */
577 break;
578
579 case TGSI_OPCODE_LG2:
580 src0 = src_vector(p, &inst->Src[0]);
581
582 i915_emit_arith(p,
583 A0_LOG,
584 get_result_vector(p, &inst->Dst[0]),
585 get_result_flags(inst), 0,
586 swizzle(src0, X, X, X, X), 0, 0);
587 break;
588
589 case TGSI_OPCODE_LIT:
590 src0 = src_vector(p, &inst->Src[0]);
591 tmp = i915_get_utemp(p);
592
593 /* tmp = max( a.xyzw, a.00zw )
594 * XXX: Clamp tmp.w to -128..128
595 * tmp.y = log(tmp.y)
596 * tmp.y = tmp.w * tmp.y
597 * tmp.y = exp(tmp.y)
598 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
599 */
600 i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0,
601 src0, swizzle(src0, ZERO, ZERO, Z, W), 0);
602
603 i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0,
604 swizzle(tmp, Y, Y, Y, Y), 0, 0);
605
606 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0,
607 swizzle(tmp, ZERO, Y, ZERO, ZERO),
608 swizzle(tmp, ZERO, W, ZERO, ZERO), 0);
609
610 i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0,
611 swizzle(tmp, Y, Y, Y, Y), 0, 0);
612
613 i915_emit_arith(p, A0_CMP,
614 get_result_vector(p, &inst->Dst[0]),
615 get_result_flags(inst), 0,
616 negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
617 swizzle(tmp, ONE, X, ZERO, ONE),
618 swizzle(tmp, ONE, X, Y, ONE));
619
620 break;
621
622 case TGSI_OPCODE_LRP:
623 src0 = src_vector(p, &inst->Src[0]);
624 src1 = src_vector(p, &inst->Src[1]);
625 src2 = src_vector(p, &inst->Src[2]);
626 flags = get_result_flags(inst);
627 tmp = i915_get_utemp(p);
628
629 /* b*a + c*(1-a)
630 *
631 * b*a + c - ca
632 *
633 * tmp = b*a + c,
634 * result = (-c)*a + tmp
635 */
636 i915_emit_arith(p, A0_MAD, tmp,
637 flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
638
639 i915_emit_arith(p, A0_MAD,
640 get_result_vector(p, &inst->Dst[0]),
641 flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
642 break;
643
644 case TGSI_OPCODE_MAD:
645 emit_simple_arith(p, inst, A0_MAD, 3);
646 break;
647
648 case TGSI_OPCODE_MAX:
649 emit_simple_arith(p, inst, A0_MAX, 2);
650 break;
651
652 case TGSI_OPCODE_MIN:
653 src0 = src_vector(p, &inst->Src[0]);
654 src1 = src_vector(p, &inst->Src[1]);
655 tmp = i915_get_utemp(p);
656 flags = get_result_flags(inst);
657
658 i915_emit_arith(p,
659 A0_MAX,
660 tmp, flags & A0_DEST_CHANNEL_ALL, 0,
661 negate(src0, 1, 1, 1, 1),
662 negate(src1, 1, 1, 1, 1), 0);
663
664 i915_emit_arith(p,
665 A0_MOV,
666 get_result_vector(p, &inst->Dst[0]),
667 flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
668 break;
669
670 case TGSI_OPCODE_MOV:
671 emit_simple_arith(p, inst, A0_MOV, 1);
672 break;
673
674 case TGSI_OPCODE_MUL:
675 emit_simple_arith(p, inst, A0_MUL, 2);
676 break;
677
678 case TGSI_OPCODE_POW:
679 src0 = src_vector(p, &inst->Src[0]);
680 src1 = src_vector(p, &inst->Src[1]);
681 tmp = i915_get_utemp(p);
682 flags = get_result_flags(inst);
683
684 /* XXX: masking on intermediate values, here and elsewhere.
685 */
686 i915_emit_arith(p,
687 A0_LOG,
688 tmp, A0_DEST_CHANNEL_X, 0,
689 swizzle(src0, X, X, X, X), 0, 0);
690
691 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0);
692
693 i915_emit_arith(p,
694 A0_EXP,
695 get_result_vector(p, &inst->Dst[0]),
696 flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
697 break;
698
699 case TGSI_OPCODE_RET:
700 /* XXX: no-op? */
701 break;
702
703 case TGSI_OPCODE_RCP:
704 src0 = src_vector(p, &inst->Src[0]);
705
706 i915_emit_arith(p,
707 A0_RCP,
708 get_result_vector(p, &inst->Dst[0]),
709 get_result_flags(inst), 0,
710 swizzle(src0, X, X, X, X), 0, 0);
711 break;
712
713 case TGSI_OPCODE_RSQ:
714 src0 = src_vector(p, &inst->Src[0]);
715
716 i915_emit_arith(p,
717 A0_RSQ,
718 get_result_vector(p, &inst->Dst[0]),
719 get_result_flags(inst), 0,
720 swizzle(src0, X, X, X, X), 0, 0);
721 break;
722
723 case TGSI_OPCODE_SCS:
724 src0 = src_vector(p, &inst->Src[0]);
725 tmp = i915_get_utemp(p);
726
727 /*
728 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
729 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
730 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
731 * scs.x = DP4 t1, sin_constants
732 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
733 * scs.y = DP4 t1, cos_constants
734 */
735 i915_emit_arith(p,
736 A0_MUL,
737 tmp, A0_DEST_CHANNEL_XY, 0,
738 swizzle(src0, X, X, ONE, ONE),
739 swizzle(src0, X, ONE, ONE, ONE), 0);
740
741 i915_emit_arith(p,
742 A0_MUL,
743 tmp, A0_DEST_CHANNEL_ALL, 0,
744 swizzle(tmp, X, Y, X, Y),
745 swizzle(tmp, X, X, ONE, ONE), 0);
746
747 writemask = inst->Dst[0].Register.WriteMask;
748
749 if (writemask & TGSI_WRITEMASK_Y) {
750 uint tmp1;
751
752 if (writemask & TGSI_WRITEMASK_X)
753 tmp1 = i915_get_utemp(p);
754 else
755 tmp1 = tmp;
756
757 i915_emit_arith(p,
758 A0_MUL,
759 tmp1, A0_DEST_CHANNEL_ALL, 0,
760 swizzle(tmp, X, Y, Y, W),
761 swizzle(tmp, X, Z, ONE, ONE), 0);
762
763 i915_emit_arith(p,
764 A0_DP4,
765 get_result_vector(p, &inst->Dst[0]),
766 A0_DEST_CHANNEL_Y, 0,
767 swizzle(tmp1, W, Z, Y, X),
768 i915_emit_const4fv(p, sin_constants), 0);
769 }
770
771 if (writemask & TGSI_WRITEMASK_X) {
772 i915_emit_arith(p,
773 A0_MUL,
774 tmp, A0_DEST_CHANNEL_XYZ, 0,
775 swizzle(tmp, X, X, Z, ONE),
776 swizzle(tmp, Z, ONE, ONE, ONE), 0);
777
778 i915_emit_arith(p,
779 A0_DP4,
780 get_result_vector(p, &inst->Dst[0]),
781 A0_DEST_CHANNEL_X, 0,
782 swizzle(tmp, ONE, Z, Y, X),
783 i915_emit_const4fv(p, cos_constants), 0);
784 }
785 break;
786
787 case TGSI_OPCODE_SGE:
788 emit_simple_arith(p, inst, A0_SGE, 2);
789 break;
790
791 case TGSI_OPCODE_SLE:
792 /* like SGE, but swap reg0, reg1 */
793 emit_simple_arith_swap2(p, inst, A0_SGE, 2);
794 break;
795
796 case TGSI_OPCODE_SIN:
797 src0 = src_vector(p, &inst->Src[0]);
798 tmp = i915_get_utemp(p);
799
800 i915_emit_arith(p,
801 A0_MUL,
802 tmp, A0_DEST_CHANNEL_X, 0,
803 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
804
805 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
806
807 /* By choosing different taylor constants, could get rid of this mul:
808 */
809 i915_emit_arith(p,
810 A0_MUL,
811 tmp, A0_DEST_CHANNEL_X, 0,
812 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
813
814 /*
815 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
816 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
817 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
818 * result = DP4 t1.wzyx, sin_constants
819 */
820 i915_emit_arith(p,
821 A0_MUL,
822 tmp, A0_DEST_CHANNEL_XY, 0,
823 swizzle(tmp, X, X, ONE, ONE),
824 swizzle(tmp, X, ONE, ONE, ONE), 0);
825
826 i915_emit_arith(p,
827 A0_MUL,
828 tmp, A0_DEST_CHANNEL_ALL, 0,
829 swizzle(tmp, X, Y, X, Y),
830 swizzle(tmp, X, X, ONE, ONE), 0);
831
832 i915_emit_arith(p,
833 A0_MUL,
834 tmp, A0_DEST_CHANNEL_ALL, 0,
835 swizzle(tmp, X, Y, Y, W),
836 swizzle(tmp, X, Z, ONE, ONE), 0);
837
838 i915_emit_arith(p,
839 A0_DP4,
840 get_result_vector(p, &inst->Dst[0]),
841 get_result_flags(inst), 0,
842 swizzle(tmp, W, Z, Y, X),
843 i915_emit_const4fv(p, sin_constants), 0);
844 break;
845
846 case TGSI_OPCODE_SLT:
847 emit_simple_arith(p, inst, A0_SLT, 2);
848 break;
849
850 case TGSI_OPCODE_SGT:
851 /* like SLT, but swap reg0, reg1 */
852 emit_simple_arith_swap2(p, inst, A0_SLT, 2);
853 break;
854
855 case TGSI_OPCODE_SUB:
856 src0 = src_vector(p, &inst->Src[0]);
857 src1 = src_vector(p, &inst->Src[1]);
858
859 i915_emit_arith(p,
860 A0_ADD,
861 get_result_vector(p, &inst->Dst[0]),
862 get_result_flags(inst), 0,
863 src0, negate(src1, 1, 1, 1, 1), 0);
864 break;
865
866 case TGSI_OPCODE_TEX:
867 emit_tex(p, inst, T0_TEXLD);
868 break;
869
870 case TGSI_OPCODE_TXB:
871 emit_tex(p, inst, T0_TEXLDB);
872 break;
873
874 case TGSI_OPCODE_TXP:
875 emit_tex(p, inst, T0_TEXLDP);
876 break;
877
878 case TGSI_OPCODE_XPD:
879 /* Cross product:
880 * result.x = src0.y * src1.z - src0.z * src1.y;
881 * result.y = src0.z * src1.x - src0.x * src1.z;
882 * result.z = src0.x * src1.y - src0.y * src1.x;
883 * result.w = undef;
884 */
885 src0 = src_vector(p, &inst->Src[0]);
886 src1 = src_vector(p, &inst->Src[1]);
887 tmp = i915_get_utemp(p);
888
889 i915_emit_arith(p,
890 A0_MUL,
891 tmp, A0_DEST_CHANNEL_ALL, 0,
892 swizzle(src0, Z, X, Y, ONE),
893 swizzle(src1, Y, Z, X, ONE), 0);
894
895 i915_emit_arith(p,
896 A0_MAD,
897 get_result_vector(p, &inst->Dst[0]),
898 get_result_flags(inst), 0,
899 swizzle(src0, Y, Z, X, ONE),
900 swizzle(src1, Z, X, Y, ONE),
901 negate(tmp, 1, 1, 1, 0));
902 break;
903
904 default:
905 i915_program_error(p, "bad opcode %d", inst->Instruction.Opcode);
906 p->error = 1;
907 return;
908 }
909
910 i915_release_utemps(p);
911 }
912
913
914 /**
915 * Translate TGSI fragment shader into i915 hardware instructions.
916 * \param p the translation state
917 * \param tokens the TGSI token array
918 */
919 static void
920 i915_translate_instructions(struct i915_fp_compile *p,
921 const struct tgsi_token *tokens)
922 {
923 struct i915_fragment_shader *ifs = p->shader;
924 struct tgsi_parse_context parse;
925
926 tgsi_parse_init( &parse, tokens );
927
928 while( !tgsi_parse_end_of_tokens( &parse ) ) {
929
930 tgsi_parse_token( &parse );
931
932 switch( parse.FullToken.Token.Type ) {
933 case TGSI_TOKEN_TYPE_PROPERTY:
934 /*
935 * We only support one cbuf, but we still need to ignore the property
936 * correctly so we don't hit the assert at the end of the switch case.
937 */
938 assert(parse.FullToken.FullProperty.Property.PropertyName ==
939 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS);
940 break;
941 case TGSI_TOKEN_TYPE_DECLARATION:
942 if (parse.FullToken.FullDeclaration.Declaration.File
943 == TGSI_FILE_CONSTANT) {
944 uint i;
945 for (i = parse.FullToken.FullDeclaration.Range.First;
946 i <= parse.FullToken.FullDeclaration.Range.Last;
947 i++) {
948 assert(ifs->constant_flags[i] == 0x0);
949 ifs->constant_flags[i] = I915_CONSTFLAG_USER;
950 ifs->num_constants = MAX2(ifs->num_constants, i + 1);
951 }
952 }
953 else if (parse.FullToken.FullDeclaration.Declaration.File
954 == TGSI_FILE_TEMPORARY) {
955 uint i;
956 for (i = parse.FullToken.FullDeclaration.Range.First;
957 i <= parse.FullToken.FullDeclaration.Range.Last;
958 i++) {
959 assert(i < I915_MAX_TEMPORARY);
960 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
961 p->temp_flag |= (1 << i); /* mark temp as used */
962 }
963 }
964 break;
965
966 case TGSI_TOKEN_TYPE_IMMEDIATE:
967 {
968 const struct tgsi_full_immediate *imm
969 = &parse.FullToken.FullImmediate;
970 const uint pos = p->num_immediates++;
971 uint j;
972 assert( imm->Immediate.NrTokens <= 4 + 1 );
973 for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
974 p->immediates[pos][j] = imm->u[j].Float;
975 }
976 }
977 break;
978
979 case TGSI_TOKEN_TYPE_INSTRUCTION:
980 if (p->first_instruction) {
981 /* resolve location of immediates */
982 uint i, j;
983 for (i = 0; i < p->num_immediates; i++) {
984 /* find constant slot for this immediate */
985 for (j = 0; j < I915_MAX_CONSTANT; j++) {
986 if (ifs->constant_flags[j] == 0x0) {
987 memcpy(ifs->constants[j],
988 p->immediates[i],
989 4 * sizeof(float));
990 /*printf("immediate %d maps to const %d\n", i, j);*/
991 ifs->constant_flags[j] = 0xf; /* all four comps used */
992 p->immediates_map[i] = j;
993 ifs->num_constants = MAX2(ifs->num_constants, j + 1);
994 break;
995 }
996 }
997 }
998
999 p->first_instruction = FALSE;
1000 }
1001
1002 i915_translate_instruction(p, &parse.FullToken.FullInstruction);
1003 break;
1004
1005 default:
1006 assert( 0 );
1007 }
1008
1009 } /* while */
1010
1011 tgsi_parse_free (&parse);
1012 }
1013
1014
1015 static struct i915_fp_compile *
1016 i915_init_compile(struct i915_context *i915,
1017 struct i915_fragment_shader *ifs)
1018 {
1019 struct i915_fp_compile *p = CALLOC_STRUCT(i915_fp_compile);
1020
1021 p->shader = ifs;
1022
1023 /* Put new constants at end of const buffer, growing downward.
1024 * The problem is we don't know how many user-defined constants might
1025 * be specified with pipe->set_constant_buffer().
1026 * Should pre-scan the user's program to determine the highest-numbered
1027 * constant referenced.
1028 */
1029 ifs->num_constants = 0;
1030 memset(ifs->constant_flags, 0, sizeof(ifs->constant_flags));
1031
1032 p->first_instruction = TRUE;
1033
1034 p->nr_tex_indirect = 1; /* correct? */
1035 p->nr_tex_insn = 0;
1036 p->nr_alu_insn = 0;
1037 p->nr_decl_insn = 0;
1038
1039 p->csr = p->program;
1040 p->decl = p->declarations;
1041 p->decl_s = 0;
1042 p->decl_t = 0;
1043 p->temp_flag = ~0x0 << I915_MAX_TEMPORARY;
1044 p->utemp_flag = ~0x7;
1045
1046 p->wpos_tex = -1;
1047
1048 /* initialize the first program word */
1049 *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM;
1050
1051 return p;
1052 }
1053
1054
1055 /* Copy compile results to the fragment program struct and destroy the
1056 * compilation context.
1057 */
1058 static void
1059 i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p)
1060 {
1061 struct i915_fragment_shader *ifs = p->shader;
1062 unsigned long program_size = (unsigned long) (p->csr - p->program);
1063 unsigned long decl_size = (unsigned long) (p->decl - p->declarations);
1064
1065 if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
1066 i915_program_error(p, "Exceeded max nr indirect texture lookups");
1067
1068 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
1069 i915_program_error(p, "Exceeded max TEX instructions");
1070
1071 if (p->nr_alu_insn > I915_MAX_ALU_INSN)
1072 i915_program_error(p, "Exceeded max ALU instructions");
1073
1074 if (p->nr_decl_insn > I915_MAX_DECL_INSN)
1075 i915_program_error(p, "Exceeded max DECL instructions");
1076
1077 if (p->error) {
1078 p->NumNativeInstructions = 0;
1079 p->NumNativeAluInstructions = 0;
1080 p->NumNativeTexInstructions = 0;
1081 p->NumNativeTexIndirections = 0;
1082
1083 i915_use_passthrough_shader(ifs);
1084 }
1085 else {
1086 p->NumNativeInstructions
1087 = p->nr_alu_insn + p->nr_tex_insn + p->nr_decl_insn;
1088 p->NumNativeAluInstructions = p->nr_alu_insn;
1089 p->NumNativeTexInstructions = p->nr_tex_insn;
1090 p->NumNativeTexIndirections = p->nr_tex_indirect;
1091
1092 /* patch in the program length */
1093 p->declarations[0] |= program_size + decl_size - 2;
1094
1095 /* Copy compilation results to fragment program struct:
1096 */
1097 assert(!ifs->program);
1098 ifs->program
1099 = (uint *) MALLOC((program_size + decl_size) * sizeof(uint));
1100 if (ifs->program) {
1101 ifs->program_len = program_size + decl_size;
1102
1103 memcpy(ifs->program,
1104 p->declarations,
1105 decl_size * sizeof(uint));
1106
1107 memcpy(ifs->program + decl_size,
1108 p->program,
1109 program_size * sizeof(uint));
1110 }
1111 }
1112
1113 /* Release the compilation struct:
1114 */
1115 FREE(p);
1116 }
1117
1118
1119 /**
1120 * Find an unused texture coordinate slot to use for fragment WPOS.
1121 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1122 */
1123 static void
1124 i915_find_wpos_space(struct i915_fp_compile *p)
1125 {
1126 #if 0
1127 const uint inputs
1128 = p->shader->inputs_read | (1 << TGSI_ATTRIB_POS); /*XXX hack*/
1129 uint i;
1130
1131 p->wpos_tex = -1;
1132
1133 if (inputs & (1 << TGSI_ATTRIB_POS)) {
1134 for (i = 0; i < I915_TEX_UNITS; i++) {
1135 if ((inputs & (1 << (TGSI_ATTRIB_TEX0 + i))) == 0) {
1136 p->wpos_tex = i;
1137 return;
1138 }
1139 }
1140
1141 i915_program_error(p, "No free texcoord for wpos value");
1142 }
1143 #else
1144 if (p->shader->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1145 /* frag shader using the fragment position input */
1146 #if 0
1147 assert(0);
1148 #endif
1149 }
1150 #endif
1151 }
1152
1153
1154
1155
1156 /**
1157 * Rather than trying to intercept and jiggle depth writes during
1158 * emit, just move the value into its correct position at the end of
1159 * the program:
1160 */
1161 static void
1162 i915_fixup_depth_write(struct i915_fp_compile *p)
1163 {
1164 /* XXX assuming pos/depth is always in output[0] */
1165 if (p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1166 const uint depth = UREG(REG_TYPE_OD, 0);
1167
1168 i915_emit_arith(p,
1169 A0_MOV, /* opcode */
1170 depth, /* dest reg */
1171 A0_DEST_CHANNEL_W, /* write mask */
1172 0, /* saturate? */
1173 swizzle(depth, X, Y, Z, Z), /* src0 */
1174 0, 0 /* src1, src2 */);
1175 }
1176 }
1177
1178
1179 void
1180 i915_translate_fragment_program( struct i915_context *i915,
1181 struct i915_fragment_shader *fs)
1182 {
1183 struct i915_fp_compile *p;
1184 const struct tgsi_token *tokens = fs->state.tokens;
1185
1186 #if 0
1187 tgsi_dump(tokens, 0);
1188 #endif
1189
1190 /* hw doesn't seem to like empty frag programs, even when the depth write
1191 * fixup gets emitted below - may that one is fishy, too? */
1192 if (fs->info.num_instructions == 1) {
1193 i915_use_passthrough_shader(fs);
1194
1195 return;
1196 }
1197
1198 p = i915_init_compile(i915, fs);
1199 i915_find_wpos_space(p);
1200
1201 i915_translate_instructions(p, tokens);
1202 i915_fixup_depth_write(p);
1203
1204 i915_fini_compile(i915, p);
1205 }