1 /**************************************************************************
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
32 #include "i915_context.h"
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
42 #include "draw/draw_vertex.h"
46 * Simple pass-through fragment shader to use when we don't have
47 * a real shader (or it fails to compile for some reason).
49 static unsigned passthrough
[] =
51 _3DSTATE_PIXEL_SHADER_PROGRAM
| ((2*3)-1),
53 /* declare input color:
56 (REG_TYPE_T
<< D0_TYPE_SHIFT
) |
57 (T_DIFFUSE
<< D0_NR_SHIFT
) |
62 /* move to output color:
65 (REG_TYPE_OC
<< A0_DEST_TYPE_SHIFT
) |
67 (REG_TYPE_T
<< A0_SRC0_TYPE_SHIFT
) |
68 (T_DIFFUSE
<< A0_SRC0_NR_SHIFT
)),
69 0x01230000, /* .xyzw */
74 /* 1, -1/3!, 1/5!, -1/7! */
75 static const float sin_constants
[4] = { 1.0,
77 1.0f
/ (5 * 4 * 3 * 2 * 1),
78 -1.0f
/ (7 * 6 * 5 * 4 * 3 * 2 * 1)
81 /* 1, -1/2!, 1/4!, -1/6! */
82 static const float cos_constants
[4] = { 1.0,
84 1.0f
/ (4 * 3 * 2 * 1),
85 -1.0f
/ (6 * 5 * 4 * 3 * 2 * 1)
91 * component-wise negation of ureg
94 negate(int reg
, int x
, int y
, int z
, int w
)
96 /* Another neat thing about the UREG representation */
97 return reg
^ (((x
& 1) << UREG_CHANNEL_X_NEGATE_SHIFT
) |
98 ((y
& 1) << UREG_CHANNEL_Y_NEGATE_SHIFT
) |
99 ((z
& 1) << UREG_CHANNEL_Z_NEGATE_SHIFT
) |
100 ((w
& 1) << UREG_CHANNEL_W_NEGATE_SHIFT
));
105 * In the event of a translation failure, we'll generate a simple color
106 * pass-through program.
109 i915_use_passthrough_shader(struct i915_fragment_shader
*fs
)
111 fs
->program
= (uint
*) MALLOC(sizeof(passthrough
));
113 memcpy(fs
->program
, passthrough
, sizeof(passthrough
));
114 fs
->program_len
= Elements(passthrough
);
116 fs
->num_constants
= 0;
121 i915_program_error(struct i915_fp_compile
*p
, const char *msg
, ...)
126 debug_printf("i915_program_error: ");
127 va_start( args
, msg
);
128 util_vsnprintf( buffer
, sizeof(buffer
), msg
, args
);
130 debug_printf("%s", buffer
);
139 * Construct a ureg for the given source register. Will emit
140 * constants, apply swizzling and negation as needed.
143 src_vector(struct i915_fp_compile
*p
,
144 const struct tgsi_full_src_register
*source
)
146 uint index
= source
->SrcRegister
.Index
;
147 uint src
= 0, sem_name
, sem_ind
;
149 switch (source
->SrcRegister
.File
) {
150 case TGSI_FILE_TEMPORARY
:
151 if (source
->SrcRegister
.Index
>= I915_MAX_TEMPORARY
) {
152 i915_program_error(p
, "Exceeded max temporary reg");
155 src
= UREG(REG_TYPE_R
, index
);
157 case TGSI_FILE_INPUT
:
158 /* XXX: Packing COL1, FOGC into a single attribute works for
159 * texenv programs, but will fail for real fragment programs
160 * that use these attributes and expect them to be a full 4
161 * components wide. Could use a texcoord to pass these
162 * attributes if necessary, but that won't work in the general
165 * We also use a texture coordinate to pass wpos when possible.
168 sem_name
= p
->shader
->info
.input_semantic_name
[index
];
169 sem_ind
= p
->shader
->info
.input_semantic_index
[index
];
172 case TGSI_SEMANTIC_POSITION
:
173 debug_printf("SKIP SEM POS\n");
175 assert(p->wpos_tex != -1);
176 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
179 case TGSI_SEMANTIC_COLOR
:
181 src
= i915_emit_decl(p
, REG_TYPE_T
, T_DIFFUSE
, D0_CHANNEL_ALL
);
184 /* secondary color */
185 assert(sem_ind
== 1);
186 src
= i915_emit_decl(p
, REG_TYPE_T
, T_SPECULAR
, D0_CHANNEL_XYZ
);
187 src
= swizzle(src
, X
, Y
, Z
, ONE
);
190 case TGSI_SEMANTIC_FOG
:
191 src
= i915_emit_decl(p
, REG_TYPE_T
, T_FOG_W
, D0_CHANNEL_W
);
192 src
= swizzle(src
, W
, W
, W
, W
);
194 case TGSI_SEMANTIC_GENERIC
:
195 /* usually a texcoord */
196 src
= i915_emit_decl(p
, REG_TYPE_T
, T_TEX0
+ sem_ind
, D0_CHANNEL_ALL
);
199 i915_program_error(p
, "Bad source->Index");
204 case TGSI_FILE_IMMEDIATE
:
205 assert(index
< p
->num_immediates
);
206 index
= p
->immediates_map
[index
];
208 case TGSI_FILE_CONSTANT
:
209 src
= UREG(REG_TYPE_CONST
, index
);
213 i915_program_error(p
, "Bad source->File");
218 source
->SrcRegister
.SwizzleX
,
219 source
->SrcRegister
.SwizzleY
,
220 source
->SrcRegister
.SwizzleZ
,
221 source
->SrcRegister
.SwizzleW
);
224 /* There's both negate-all-components and per-component negation.
225 * Try to handle both here.
228 int n
= source
->SrcRegister
.Negate
;
229 src
= negate(src
, n
, n
, n
, n
);
232 /* no abs() or post-abs negation */
234 /* XXX assertions disabled to allow arbfplight.c to run */
235 /* XXX enable these assertions, or fix things */
236 assert(!source
->SrcRegisterExtMod
.Absolute
);
237 assert(!source
->SrcRegisterExtMod
.Negate
);
244 * Construct a ureg for a destination register.
247 get_result_vector(struct i915_fp_compile
*p
,
248 const struct tgsi_full_dst_register
*dest
)
250 switch (dest
->DstRegister
.File
) {
251 case TGSI_FILE_OUTPUT
:
253 uint sem_name
= p
->shader
->info
.output_semantic_name
[dest
->DstRegister
.Index
];
255 case TGSI_SEMANTIC_POSITION
:
256 return UREG(REG_TYPE_OD
, 0);
257 case TGSI_SEMANTIC_COLOR
:
258 return UREG(REG_TYPE_OC
, 0);
260 i915_program_error(p
, "Bad inst->DstReg.Index/semantics");
264 case TGSI_FILE_TEMPORARY
:
265 return UREG(REG_TYPE_R
, dest
->DstRegister
.Index
);
267 i915_program_error(p
, "Bad inst->DstReg.File");
274 * Compute flags for saturation and writemask.
277 get_result_flags(const struct tgsi_full_instruction
*inst
)
280 = inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
283 if (inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
284 flags
|= A0_DEST_SATURATE
;
286 if (writeMask
& TGSI_WRITEMASK_X
)
287 flags
|= A0_DEST_CHANNEL_X
;
288 if (writeMask
& TGSI_WRITEMASK_Y
)
289 flags
|= A0_DEST_CHANNEL_Y
;
290 if (writeMask
& TGSI_WRITEMASK_Z
)
291 flags
|= A0_DEST_CHANNEL_Z
;
292 if (writeMask
& TGSI_WRITEMASK_W
)
293 flags
|= A0_DEST_CHANNEL_W
;
300 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
303 translate_tex_src_target(struct i915_fp_compile
*p
, uint tex
)
306 case TGSI_TEXTURE_SHADOW1D
:
308 case TGSI_TEXTURE_1D
:
309 return D0_SAMPLE_TYPE_2D
;
311 case TGSI_TEXTURE_SHADOW2D
:
313 case TGSI_TEXTURE_2D
:
314 return D0_SAMPLE_TYPE_2D
;
316 case TGSI_TEXTURE_SHADOWRECT
:
318 case TGSI_TEXTURE_RECT
:
319 return D0_SAMPLE_TYPE_2D
;
321 case TGSI_TEXTURE_3D
:
322 return D0_SAMPLE_TYPE_VOLUME
;
324 case TGSI_TEXTURE_CUBE
:
325 return D0_SAMPLE_TYPE_CUBE
;
328 i915_program_error(p
, "TexSrc type");
335 * Generate texel lookup instruction.
338 emit_tex(struct i915_fp_compile
*p
,
339 const struct tgsi_full_instruction
*inst
,
342 uint texture
= inst
->InstructionExtTexture
.Texture
;
343 uint unit
= inst
->FullSrcRegisters
[1].SrcRegister
.Index
;
344 uint tex
= translate_tex_src_target( p
, texture
);
345 uint sampler
= i915_emit_decl(p
, REG_TYPE_S
, unit
, tex
);
346 uint coord
= src_vector( p
, &inst
->FullSrcRegisters
[0]);
349 get_result_vector( p
, &inst
->FullDstRegisters
[0] ),
350 get_result_flags( inst
),
358 * Generate a simple arithmetic instruction
359 * \param opcode the i915 opcode
360 * \param numArgs the number of input/src arguments
363 emit_simple_arith(struct i915_fp_compile
*p
,
364 const struct tgsi_full_instruction
*inst
,
365 uint opcode
, uint numArgs
)
367 uint arg1
, arg2
, arg3
;
369 assert(numArgs
<= 3);
371 arg1
= (numArgs
< 1) ? 0 : src_vector( p
, &inst
->FullSrcRegisters
[0] );
372 arg2
= (numArgs
< 2) ? 0 : src_vector( p
, &inst
->FullSrcRegisters
[1] );
373 arg3
= (numArgs
< 3) ? 0 : src_vector( p
, &inst
->FullSrcRegisters
[2] );
377 get_result_vector( p
, &inst
->FullDstRegisters
[0]),
378 get_result_flags( inst
), 0,
385 /** As above, but swap the first two src regs */
387 emit_simple_arith_swap2(struct i915_fp_compile
*p
,
388 const struct tgsi_full_instruction
*inst
,
389 uint opcode
, uint numArgs
)
391 struct tgsi_full_instruction inst2
;
393 assert(numArgs
== 2);
395 /* transpose first two registers */
397 inst2
.FullSrcRegisters
[0] = inst
->FullSrcRegisters
[1];
398 inst2
.FullSrcRegisters
[1] = inst
->FullSrcRegisters
[0];
400 emit_simple_arith(p
, &inst2
, opcode
, numArgs
);
405 #define M_PI 3.14159265358979323846
409 * Translate TGSI instruction to i915 instruction.
413 * SIN, COS -- could use another taylor step?
414 * LIT -- results seem a little different to sw mesa
415 * LOG -- different to mesa on negative numbers, but this is conformant.
418 i915_translate_instruction(struct i915_fp_compile
*p
,
419 const struct tgsi_full_instruction
*inst
)
422 uint src0
, src1
, src2
, flags
;
425 switch (inst
->Instruction
.Opcode
) {
426 case TGSI_OPCODE_ABS
:
427 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
430 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
431 get_result_flags(inst
), 0,
432 src0
, negate(src0
, 1, 1, 1, 1), 0);
435 case TGSI_OPCODE_ADD
:
436 emit_simple_arith(p
, inst
, A0_ADD
, 2);
439 case TGSI_OPCODE_CMP
:
440 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
441 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
442 src2
= src_vector(p
, &inst
->FullSrcRegisters
[2]);
443 i915_emit_arith(p
, A0_CMP
,
444 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
445 get_result_flags(inst
),
446 0, src0
, src2
, src1
); /* NOTE: order of src2, src1 */
449 case TGSI_OPCODE_COS
:
450 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
451 tmp
= i915_get_utemp(p
);
455 tmp
, A0_DEST_CHANNEL_X
, 0,
456 src0
, i915_emit_const1f(p
, 1.0f
/ (float) (M_PI
* 2.0)), 0);
458 i915_emit_arith(p
, A0_MOD
, tmp
, A0_DEST_CHANNEL_X
, 0, tmp
, 0, 0);
460 /* By choosing different taylor constants, could get rid of this mul:
464 tmp
, A0_DEST_CHANNEL_X
, 0,
465 tmp
, i915_emit_const1f(p
, (float) (M_PI
* 2.0)), 0);
468 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
469 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
470 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
471 * result = DP4 t0, cos_constants
475 tmp
, A0_DEST_CHANNEL_XY
, 0,
476 swizzle(tmp
, X
, X
, ONE
, ONE
),
477 swizzle(tmp
, X
, ONE
, ONE
, ONE
), 0);
481 tmp
, A0_DEST_CHANNEL_XYZ
, 0,
482 swizzle(tmp
, X
, Y
, X
, ONE
),
483 swizzle(tmp
, X
, X
, ONE
, ONE
), 0);
487 tmp
, A0_DEST_CHANNEL_XYZ
, 0,
488 swizzle(tmp
, X
, X
, Z
, ONE
),
489 swizzle(tmp
, Z
, ONE
, ONE
, ONE
), 0);
493 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
494 get_result_flags(inst
), 0,
495 swizzle(tmp
, ONE
, Z
, Y
, X
),
496 i915_emit_const4fv(p
, cos_constants
), 0);
499 case TGSI_OPCODE_DP3
:
500 emit_simple_arith(p
, inst
, A0_DP3
, 2);
503 case TGSI_OPCODE_DP4
:
504 emit_simple_arith(p
, inst
, A0_DP4
, 2);
507 case TGSI_OPCODE_DPH
:
508 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
509 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
513 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
514 get_result_flags(inst
), 0,
515 swizzle(src0
, X
, Y
, Z
, ONE
), src1
, 0);
518 case TGSI_OPCODE_DST
:
519 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
520 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
522 /* result[0] = 1 * 1;
523 * result[1] = a[1] * b[1];
524 * result[2] = a[2] * 1;
525 * result[3] = 1 * b[3];
529 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
530 get_result_flags(inst
), 0,
531 swizzle(src0
, ONE
, Y
, Z
, ONE
),
532 swizzle(src1
, ONE
, Y
, ONE
, W
), 0);
535 case TGSI_OPCODE_END
:
539 case TGSI_OPCODE_EX2
:
540 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
544 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
545 get_result_flags(inst
), 0,
546 swizzle(src0
, X
, X
, X
, X
), 0, 0);
549 case TGSI_OPCODE_FLR
:
550 emit_simple_arith(p
, inst
, A0_FLR
, 1);
553 case TGSI_OPCODE_FRC
:
554 emit_simple_arith(p
, inst
, A0_FRC
, 1);
557 case TGSI_OPCODE_KIL
:
558 /* kill if src[0].x < 0 || src[0].y < 0 ... */
559 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
560 tmp
= i915_get_utemp(p
);
563 tmp
, /* dest reg: a dummy reg */
564 A0_DEST_CHANNEL_ALL
, /* dest writemask */
567 T0_TEXKILL
); /* opcode */
570 case TGSI_OPCODE_KILP
:
571 assert(0); /* not tested yet */
574 case TGSI_OPCODE_LG2
:
575 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
579 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
580 get_result_flags(inst
), 0,
581 swizzle(src0
, X
, X
, X
, X
), 0, 0);
584 case TGSI_OPCODE_LIT
:
585 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
586 tmp
= i915_get_utemp(p
);
588 /* tmp = max( a.xyzw, a.00zw )
589 * XXX: Clamp tmp.w to -128..128
591 * tmp.y = tmp.w * tmp.y
593 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
595 i915_emit_arith(p
, A0_MAX
, tmp
, A0_DEST_CHANNEL_ALL
, 0,
596 src0
, swizzle(src0
, ZERO
, ZERO
, Z
, W
), 0);
598 i915_emit_arith(p
, A0_LOG
, tmp
, A0_DEST_CHANNEL_Y
, 0,
599 swizzle(tmp
, Y
, Y
, Y
, Y
), 0, 0);
601 i915_emit_arith(p
, A0_MUL
, tmp
, A0_DEST_CHANNEL_Y
, 0,
602 swizzle(tmp
, ZERO
, Y
, ZERO
, ZERO
),
603 swizzle(tmp
, ZERO
, W
, ZERO
, ZERO
), 0);
605 i915_emit_arith(p
, A0_EXP
, tmp
, A0_DEST_CHANNEL_Y
, 0,
606 swizzle(tmp
, Y
, Y
, Y
, Y
), 0, 0);
608 i915_emit_arith(p
, A0_CMP
,
609 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
610 get_result_flags(inst
), 0,
611 negate(swizzle(tmp
, ONE
, ONE
, X
, ONE
), 0, 0, 1, 0),
612 swizzle(tmp
, ONE
, X
, ZERO
, ONE
),
613 swizzle(tmp
, ONE
, X
, Y
, ONE
));
617 case TGSI_OPCODE_LRP
:
618 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
619 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
620 src2
= src_vector(p
, &inst
->FullSrcRegisters
[2]);
621 flags
= get_result_flags(inst
);
622 tmp
= i915_get_utemp(p
);
629 * result = (-c)*a + tmp
631 i915_emit_arith(p
, A0_MAD
, tmp
,
632 flags
& A0_DEST_CHANNEL_ALL
, 0, src1
, src0
, src2
);
634 i915_emit_arith(p
, A0_MAD
,
635 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
636 flags
, 0, negate(src2
, 1, 1, 1, 1), src0
, tmp
);
639 case TGSI_OPCODE_MAD
:
640 emit_simple_arith(p
, inst
, A0_MAD
, 3);
643 case TGSI_OPCODE_MAX
:
644 emit_simple_arith(p
, inst
, A0_MAX
, 2);
647 case TGSI_OPCODE_MIN
:
648 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
649 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
650 tmp
= i915_get_utemp(p
);
651 flags
= get_result_flags(inst
);
655 tmp
, flags
& A0_DEST_CHANNEL_ALL
, 0,
656 negate(src0
, 1, 1, 1, 1),
657 negate(src1
, 1, 1, 1, 1), 0);
661 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
662 flags
, 0, negate(tmp
, 1, 1, 1, 1), 0, 0);
665 case TGSI_OPCODE_MOV
:
666 emit_simple_arith(p
, inst
, A0_MOV
, 1);
669 case TGSI_OPCODE_MUL
:
670 emit_simple_arith(p
, inst
, A0_MUL
, 2);
673 case TGSI_OPCODE_POW
:
674 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
675 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
676 tmp
= i915_get_utemp(p
);
677 flags
= get_result_flags(inst
);
679 /* XXX: masking on intermediate values, here and elsewhere.
683 tmp
, A0_DEST_CHANNEL_X
, 0,
684 swizzle(src0
, X
, X
, X
, X
), 0, 0);
686 i915_emit_arith(p
, A0_MUL
, tmp
, A0_DEST_CHANNEL_X
, 0, tmp
, src1
, 0);
690 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
691 flags
, 0, swizzle(tmp
, X
, X
, X
, X
), 0, 0);
694 case TGSI_OPCODE_RET
:
698 case TGSI_OPCODE_RCP
:
699 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
703 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
704 get_result_flags(inst
), 0,
705 swizzle(src0
, X
, X
, X
, X
), 0, 0);
708 case TGSI_OPCODE_RSQ
:
709 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
713 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
714 get_result_flags(inst
), 0,
715 swizzle(src0
, X
, X
, X
, X
), 0, 0);
718 case TGSI_OPCODE_SCS
:
719 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
720 tmp
= i915_get_utemp(p
);
723 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
724 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
725 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
726 * scs.x = DP4 t1, sin_constants
727 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
728 * scs.y = DP4 t1, cos_constants
732 tmp
, A0_DEST_CHANNEL_XY
, 0,
733 swizzle(src0
, X
, X
, ONE
, ONE
),
734 swizzle(src0
, X
, ONE
, ONE
, ONE
), 0);
738 tmp
, A0_DEST_CHANNEL_ALL
, 0,
739 swizzle(tmp
, X
, Y
, X
, Y
),
740 swizzle(tmp
, X
, X
, ONE
, ONE
), 0);
742 writemask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
744 if (writemask
& TGSI_WRITEMASK_Y
) {
747 if (writemask
& TGSI_WRITEMASK_X
)
748 tmp1
= i915_get_utemp(p
);
754 tmp1
, A0_DEST_CHANNEL_ALL
, 0,
755 swizzle(tmp
, X
, Y
, Y
, W
),
756 swizzle(tmp
, X
, Z
, ONE
, ONE
), 0);
760 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
761 A0_DEST_CHANNEL_Y
, 0,
762 swizzle(tmp1
, W
, Z
, Y
, X
),
763 i915_emit_const4fv(p
, sin_constants
), 0);
766 if (writemask
& TGSI_WRITEMASK_X
) {
769 tmp
, A0_DEST_CHANNEL_XYZ
, 0,
770 swizzle(tmp
, X
, X
, Z
, ONE
),
771 swizzle(tmp
, Z
, ONE
, ONE
, ONE
), 0);
775 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
776 A0_DEST_CHANNEL_X
, 0,
777 swizzle(tmp
, ONE
, Z
, Y
, X
),
778 i915_emit_const4fv(p
, cos_constants
), 0);
782 case TGSI_OPCODE_SGE
:
783 emit_simple_arith(p
, inst
, A0_SGE
, 2);
786 case TGSI_OPCODE_SLE
:
787 /* like SGE, but swap reg0, reg1 */
788 emit_simple_arith_swap2(p
, inst
, A0_SGE
, 2);
791 case TGSI_OPCODE_SIN
:
792 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
793 tmp
= i915_get_utemp(p
);
797 tmp
, A0_DEST_CHANNEL_X
, 0,
798 src0
, i915_emit_const1f(p
, 1.0f
/ (float) (M_PI
* 2.0)), 0);
800 i915_emit_arith(p
, A0_MOD
, tmp
, A0_DEST_CHANNEL_X
, 0, tmp
, 0, 0);
802 /* By choosing different taylor constants, could get rid of this mul:
806 tmp
, A0_DEST_CHANNEL_X
, 0,
807 tmp
, i915_emit_const1f(p
, (float) (M_PI
* 2.0)), 0);
810 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
811 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
812 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
813 * result = DP4 t1.wzyx, sin_constants
817 tmp
, A0_DEST_CHANNEL_XY
, 0,
818 swizzle(tmp
, X
, X
, ONE
, ONE
),
819 swizzle(tmp
, X
, ONE
, ONE
, ONE
), 0);
823 tmp
, A0_DEST_CHANNEL_ALL
, 0,
824 swizzle(tmp
, X
, Y
, X
, Y
),
825 swizzle(tmp
, X
, X
, ONE
, ONE
), 0);
829 tmp
, A0_DEST_CHANNEL_ALL
, 0,
830 swizzle(tmp
, X
, Y
, Y
, W
),
831 swizzle(tmp
, X
, Z
, ONE
, ONE
), 0);
835 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
836 get_result_flags(inst
), 0,
837 swizzle(tmp
, W
, Z
, Y
, X
),
838 i915_emit_const4fv(p
, sin_constants
), 0);
841 case TGSI_OPCODE_SLT
:
842 emit_simple_arith(p
, inst
, A0_SLT
, 2);
845 case TGSI_OPCODE_SGT
:
846 /* like SLT, but swap reg0, reg1 */
847 emit_simple_arith_swap2(p
, inst
, A0_SLT
, 2);
850 case TGSI_OPCODE_SUB
:
851 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
852 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
856 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
857 get_result_flags(inst
), 0,
858 src0
, negate(src1
, 1, 1, 1, 1), 0);
861 case TGSI_OPCODE_TEX
:
862 emit_tex(p
, inst
, T0_TEXLD
);
865 case TGSI_OPCODE_TXB
:
866 emit_tex(p
, inst
, T0_TEXLDB
);
869 case TGSI_OPCODE_TXP
:
870 emit_tex(p
, inst
, T0_TEXLDP
);
873 case TGSI_OPCODE_XPD
:
875 * result.x = src0.y * src1.z - src0.z * src1.y;
876 * result.y = src0.z * src1.x - src0.x * src1.z;
877 * result.z = src0.x * src1.y - src0.y * src1.x;
880 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
881 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
882 tmp
= i915_get_utemp(p
);
886 tmp
, A0_DEST_CHANNEL_ALL
, 0,
887 swizzle(src0
, Z
, X
, Y
, ONE
),
888 swizzle(src1
, Y
, Z
, X
, ONE
), 0);
892 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
893 get_result_flags(inst
), 0,
894 swizzle(src0
, Y
, Z
, X
, ONE
),
895 swizzle(src1
, Z
, X
, Y
, ONE
),
896 negate(tmp
, 1, 1, 1, 0));
900 i915_program_error(p
, "bad opcode %d", inst
->Instruction
.Opcode
);
905 i915_release_utemps(p
);
910 * Translate TGSI fragment shader into i915 hardware instructions.
911 * \param p the translation state
912 * \param tokens the TGSI token array
915 i915_translate_instructions(struct i915_fp_compile
*p
,
916 const struct tgsi_token
*tokens
)
918 struct i915_fragment_shader
*ifs
= p
->shader
;
919 struct tgsi_parse_context parse
;
921 tgsi_parse_init( &parse
, tokens
);
923 while( !tgsi_parse_end_of_tokens( &parse
) ) {
925 tgsi_parse_token( &parse
);
927 switch( parse
.FullToken
.Token
.Type
) {
928 case TGSI_TOKEN_TYPE_DECLARATION
:
929 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
930 == TGSI_FILE_CONSTANT
) {
932 for (i
= parse
.FullToken
.FullDeclaration
.DeclarationRange
.First
;
933 i
<= parse
.FullToken
.FullDeclaration
.DeclarationRange
.Last
;
935 assert(ifs
->constant_flags
[i
] == 0x0);
936 ifs
->constant_flags
[i
] = I915_CONSTFLAG_USER
;
937 ifs
->num_constants
= MAX2(ifs
->num_constants
, i
+ 1);
940 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
941 == TGSI_FILE_TEMPORARY
) {
943 for (i
= parse
.FullToken
.FullDeclaration
.DeclarationRange
.First
;
944 i
<= parse
.FullToken
.FullDeclaration
.DeclarationRange
.Last
;
946 assert(i
< I915_MAX_TEMPORARY
);
947 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
948 p
->temp_flag
|= (1 << i
); /* mark temp as used */
953 case TGSI_TOKEN_TYPE_IMMEDIATE
:
955 const struct tgsi_full_immediate
*imm
956 = &parse
.FullToken
.FullImmediate
;
957 const uint pos
= p
->num_immediates
++;
959 assert( imm
->Immediate
.NrTokens
<= 4 + 1 );
960 for (j
= 0; j
< imm
->Immediate
.NrTokens
- 1; j
++) {
961 p
->immediates
[pos
][j
] = imm
->u
[j
].Float
;
966 case TGSI_TOKEN_TYPE_INSTRUCTION
:
967 if (p
->first_instruction
) {
968 /* resolve location of immediates */
970 for (i
= 0; i
< p
->num_immediates
; i
++) {
971 /* find constant slot for this immediate */
972 for (j
= 0; j
< I915_MAX_CONSTANT
; j
++) {
973 if (ifs
->constant_flags
[j
] == 0x0) {
974 memcpy(ifs
->constants
[j
],
977 /*printf("immediate %d maps to const %d\n", i, j);*/
978 ifs
->constant_flags
[j
] = 0xf; /* all four comps used */
979 p
->immediates_map
[i
] = j
;
980 ifs
->num_constants
= MAX2(ifs
->num_constants
, j
+ 1);
986 p
->first_instruction
= FALSE
;
989 i915_translate_instruction(p
, &parse
.FullToken
.FullInstruction
);
998 tgsi_parse_free (&parse
);
1002 static struct i915_fp_compile
*
1003 i915_init_compile(struct i915_context
*i915
,
1004 struct i915_fragment_shader
*ifs
)
1006 struct i915_fp_compile
*p
= CALLOC_STRUCT(i915_fp_compile
);
1010 /* Put new constants at end of const buffer, growing downward.
1011 * The problem is we don't know how many user-defined constants might
1012 * be specified with pipe->set_constant_buffer().
1013 * Should pre-scan the user's program to determine the highest-numbered
1014 * constant referenced.
1016 ifs
->num_constants
= 0;
1017 memset(ifs
->constant_flags
, 0, sizeof(ifs
->constant_flags
));
1019 p
->first_instruction
= TRUE
;
1021 p
->nr_tex_indirect
= 1; /* correct? */
1024 p
->nr_decl_insn
= 0;
1026 p
->csr
= p
->program
;
1027 p
->decl
= p
->declarations
;
1030 p
->temp_flag
= ~0x0 << I915_MAX_TEMPORARY
;
1031 p
->utemp_flag
= ~0x7;
1035 /* initialize the first program word */
1036 *(p
->decl
++) = _3DSTATE_PIXEL_SHADER_PROGRAM
;
1042 /* Copy compile results to the fragment program struct and destroy the
1043 * compilation context.
1046 i915_fini_compile(struct i915_context
*i915
, struct i915_fp_compile
*p
)
1048 struct i915_fragment_shader
*ifs
= p
->shader
;
1049 unsigned long program_size
= (unsigned long) (p
->csr
- p
->program
);
1050 unsigned long decl_size
= (unsigned long) (p
->decl
- p
->declarations
);
1052 if (p
->nr_tex_indirect
> I915_MAX_TEX_INDIRECT
)
1053 i915_program_error(p
, "Exceeded max nr indirect texture lookups");
1055 if (p
->nr_tex_insn
> I915_MAX_TEX_INSN
)
1056 i915_program_error(p
, "Exceeded max TEX instructions");
1058 if (p
->nr_alu_insn
> I915_MAX_ALU_INSN
)
1059 i915_program_error(p
, "Exceeded max ALU instructions");
1061 if (p
->nr_decl_insn
> I915_MAX_DECL_INSN
)
1062 i915_program_error(p
, "Exceeded max DECL instructions");
1065 p
->NumNativeInstructions
= 0;
1066 p
->NumNativeAluInstructions
= 0;
1067 p
->NumNativeTexInstructions
= 0;
1068 p
->NumNativeTexIndirections
= 0;
1070 i915_use_passthrough_shader(ifs
);
1073 p
->NumNativeInstructions
1074 = p
->nr_alu_insn
+ p
->nr_tex_insn
+ p
->nr_decl_insn
;
1075 p
->NumNativeAluInstructions
= p
->nr_alu_insn
;
1076 p
->NumNativeTexInstructions
= p
->nr_tex_insn
;
1077 p
->NumNativeTexIndirections
= p
->nr_tex_indirect
;
1079 /* patch in the program length */
1080 p
->declarations
[0] |= program_size
+ decl_size
- 2;
1082 /* Copy compilation results to fragment program struct:
1084 assert(!ifs
->program
);
1086 = (uint
*) MALLOC((program_size
+ decl_size
) * sizeof(uint
));
1088 ifs
->program_len
= program_size
+ decl_size
;
1090 memcpy(ifs
->program
,
1092 decl_size
* sizeof(uint
));
1094 memcpy(ifs
->program
+ decl_size
,
1096 program_size
* sizeof(uint
));
1100 /* Release the compilation struct:
1107 * Find an unused texture coordinate slot to use for fragment WPOS.
1108 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1111 i915_find_wpos_space(struct i915_fp_compile
*p
)
1115 = p
->shader
->inputs_read
| (1 << TGSI_ATTRIB_POS
); /*XXX hack*/
1120 if (inputs
& (1 << TGSI_ATTRIB_POS
)) {
1121 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
1122 if ((inputs
& (1 << (TGSI_ATTRIB_TEX0
+ i
))) == 0) {
1128 i915_program_error(p
, "No free texcoord for wpos value");
1131 if (p
->shader
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
) {
1132 /* frag shader using the fragment position input */
1144 * Rather than trying to intercept and jiggle depth writes during
1145 * emit, just move the value into its correct position at the end of
1149 i915_fixup_depth_write(struct i915_fp_compile
*p
)
1151 /* XXX assuming pos/depth is always in output[0] */
1152 if (p
->shader
->info
.output_semantic_name
[0] == TGSI_SEMANTIC_POSITION
) {
1153 const uint depth
= UREG(REG_TYPE_OD
, 0);
1156 A0_MOV
, /* opcode */
1157 depth
, /* dest reg */
1158 A0_DEST_CHANNEL_W
, /* write mask */
1160 swizzle(depth
, X
, Y
, Z
, Z
), /* src0 */
1161 0, 0 /* src1, src2 */);
1167 i915_translate_fragment_program( struct i915_context
*i915
,
1168 struct i915_fragment_shader
*fs
)
1170 struct i915_fp_compile
*p
= i915_init_compile(i915
, fs
);
1171 const struct tgsi_token
*tokens
= fs
->state
.tokens
;
1173 i915_find_wpos_space(p
);
1176 tgsi_dump(tokens
, 0);
1179 i915_translate_instructions(p
, tokens
);
1180 i915_fixup_depth_write(p
);
1182 i915_fini_compile(i915
, p
);