1 /**************************************************************************
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
32 #include "i915_context.h"
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
42 #include "draw/draw_vertex.h"
46 * Simple pass-through fragment shader to use when we don't have
47 * a real shader (or it fails to compile for some reason).
49 static unsigned passthrough
[] =
51 _3DSTATE_PIXEL_SHADER_PROGRAM
| ((2*3)-1),
53 /* declare input color:
56 (REG_TYPE_T
<< D0_TYPE_SHIFT
) |
57 (T_DIFFUSE
<< D0_NR_SHIFT
) |
62 /* move to output color:
65 (REG_TYPE_OC
<< A0_DEST_TYPE_SHIFT
) |
67 (REG_TYPE_T
<< A0_SRC0_TYPE_SHIFT
) |
68 (T_DIFFUSE
<< A0_SRC0_NR_SHIFT
)),
69 0x01230000, /* .xyzw */
74 /* 1, -1/3!, 1/5!, -1/7! */
75 static const float sin_constants
[4] = { 1.0,
77 1.0f
/ (5 * 4 * 3 * 2 * 1),
78 -1.0f
/ (7 * 6 * 5 * 4 * 3 * 2 * 1)
81 /* 1, -1/2!, 1/4!, -1/6! */
82 static const float cos_constants
[4] = { 1.0,
84 1.0f
/ (4 * 3 * 2 * 1),
85 -1.0f
/ (6 * 5 * 4 * 3 * 2 * 1)
91 * component-wise negation of ureg
94 negate(int reg
, int x
, int y
, int z
, int w
)
96 /* Another neat thing about the UREG representation */
97 return reg
^ (((x
& 1) << UREG_CHANNEL_X_NEGATE_SHIFT
) |
98 ((y
& 1) << UREG_CHANNEL_Y_NEGATE_SHIFT
) |
99 ((z
& 1) << UREG_CHANNEL_Z_NEGATE_SHIFT
) |
100 ((w
& 1) << UREG_CHANNEL_W_NEGATE_SHIFT
));
105 * In the event of a translation failure, we'll generate a simple color
106 * pass-through program.
109 i915_use_passthrough_shader(struct i915_fragment_shader
*fs
)
111 fs
->program
= (uint
*) MALLOC(sizeof(passthrough
));
113 memcpy(fs
->program
, passthrough
, sizeof(passthrough
));
114 fs
->program_len
= Elements(passthrough
);
116 fs
->num_constants
= 0;
121 i915_program_error(struct i915_fp_compile
*p
, const char *msg
, ...)
126 debug_printf("i915_program_error: ");
127 va_start( args
, msg
);
128 util_vsnprintf( buffer
, sizeof(buffer
), msg
, args
);
130 debug_printf(buffer
);
139 * Construct a ureg for the given source register. Will emit
140 * constants, apply swizzling and negation as needed.
143 src_vector(struct i915_fp_compile
*p
,
144 const struct tgsi_full_src_register
*source
)
146 uint index
= source
->SrcRegister
.Index
;
147 uint src
= 0, sem_name
, sem_ind
;
149 switch (source
->SrcRegister
.File
) {
150 case TGSI_FILE_TEMPORARY
:
151 if (source
->SrcRegister
.Index
>= I915_MAX_TEMPORARY
) {
152 i915_program_error(p
, "Exceeded max temporary reg");
155 src
= UREG(REG_TYPE_R
, index
);
157 case TGSI_FILE_INPUT
:
158 /* XXX: Packing COL1, FOGC into a single attribute works for
159 * texenv programs, but will fail for real fragment programs
160 * that use these attributes and expect them to be a full 4
161 * components wide. Could use a texcoord to pass these
162 * attributes if necessary, but that won't work in the general
165 * We also use a texture coordinate to pass wpos when possible.
168 sem_name
= p
->shader
->info
.input_semantic_name
[index
];
169 sem_ind
= p
->shader
->info
.input_semantic_index
[index
];
172 case TGSI_SEMANTIC_POSITION
:
173 debug_printf("SKIP SEM POS\n");
175 assert(p->wpos_tex != -1);
176 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
179 case TGSI_SEMANTIC_COLOR
:
181 src
= i915_emit_decl(p
, REG_TYPE_T
, T_DIFFUSE
, D0_CHANNEL_ALL
);
184 /* secondary color */
185 assert(sem_ind
== 1);
186 src
= i915_emit_decl(p
, REG_TYPE_T
, T_SPECULAR
, D0_CHANNEL_XYZ
);
187 src
= swizzle(src
, X
, Y
, Z
, ONE
);
190 case TGSI_SEMANTIC_FOG
:
191 src
= i915_emit_decl(p
, REG_TYPE_T
, T_FOG_W
, D0_CHANNEL_W
);
192 src
= swizzle(src
, W
, W
, W
, W
);
194 case TGSI_SEMANTIC_GENERIC
:
195 /* usually a texcoord */
196 src
= i915_emit_decl(p
, REG_TYPE_T
, T_TEX0
+ sem_ind
, D0_CHANNEL_ALL
);
199 i915_program_error(p
, "Bad source->Index");
204 case TGSI_FILE_IMMEDIATE
:
205 assert(index
< p
->num_immediates
);
206 index
= p
->immediates_map
[index
];
208 case TGSI_FILE_CONSTANT
:
209 src
= UREG(REG_TYPE_CONST
, index
);
213 i915_program_error(p
, "Bad source->File");
217 if (source
->SrcRegister
.Extended
) {
219 source
->SrcRegisterExtSwz
.ExtSwizzleX
,
220 source
->SrcRegisterExtSwz
.ExtSwizzleY
,
221 source
->SrcRegisterExtSwz
.ExtSwizzleZ
,
222 source
->SrcRegisterExtSwz
.ExtSwizzleW
);
226 source
->SrcRegister
.SwizzleX
,
227 source
->SrcRegister
.SwizzleY
,
228 source
->SrcRegister
.SwizzleZ
,
229 source
->SrcRegister
.SwizzleW
);
233 /* There's both negate-all-components and per-component negation.
234 * Try to handle both here.
237 int nx
= source
->SrcRegisterExtSwz
.NegateX
;
238 int ny
= source
->SrcRegisterExtSwz
.NegateY
;
239 int nz
= source
->SrcRegisterExtSwz
.NegateZ
;
240 int nw
= source
->SrcRegisterExtSwz
.NegateW
;
241 if (source
->SrcRegister
.Negate
) {
247 src
= negate(src
, nx
, ny
, nz
, nw
);
250 /* no abs() or post-abs negation */
252 /* XXX assertions disabled to allow arbfplight.c to run */
253 /* XXX enable these assertions, or fix things */
254 assert(!source
->SrcRegisterExtMod
.Absolute
);
255 assert(!source
->SrcRegisterExtMod
.Negate
);
262 * Construct a ureg for a destination register.
265 get_result_vector(struct i915_fp_compile
*p
,
266 const struct tgsi_full_dst_register
*dest
)
268 switch (dest
->DstRegister
.File
) {
269 case TGSI_FILE_OUTPUT
:
271 uint sem_name
= p
->shader
->info
.output_semantic_name
[dest
->DstRegister
.Index
];
273 case TGSI_SEMANTIC_POSITION
:
274 return UREG(REG_TYPE_OD
, 0);
275 case TGSI_SEMANTIC_COLOR
:
276 return UREG(REG_TYPE_OC
, 0);
278 i915_program_error(p
, "Bad inst->DstReg.Index/semantics");
282 case TGSI_FILE_TEMPORARY
:
283 return UREG(REG_TYPE_R
, dest
->DstRegister
.Index
);
285 i915_program_error(p
, "Bad inst->DstReg.File");
292 * Compute flags for saturation and writemask.
295 get_result_flags(const struct tgsi_full_instruction
*inst
)
298 = inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
301 if (inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
302 flags
|= A0_DEST_SATURATE
;
304 if (writeMask
& TGSI_WRITEMASK_X
)
305 flags
|= A0_DEST_CHANNEL_X
;
306 if (writeMask
& TGSI_WRITEMASK_Y
)
307 flags
|= A0_DEST_CHANNEL_Y
;
308 if (writeMask
& TGSI_WRITEMASK_Z
)
309 flags
|= A0_DEST_CHANNEL_Z
;
310 if (writeMask
& TGSI_WRITEMASK_W
)
311 flags
|= A0_DEST_CHANNEL_W
;
318 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
321 translate_tex_src_target(struct i915_fp_compile
*p
, uint tex
)
324 case TGSI_TEXTURE_SHADOW1D
:
326 case TGSI_TEXTURE_1D
:
327 return D0_SAMPLE_TYPE_2D
;
329 case TGSI_TEXTURE_SHADOW2D
:
331 case TGSI_TEXTURE_2D
:
332 return D0_SAMPLE_TYPE_2D
;
334 case TGSI_TEXTURE_SHADOWRECT
:
336 case TGSI_TEXTURE_RECT
:
337 return D0_SAMPLE_TYPE_2D
;
339 case TGSI_TEXTURE_3D
:
340 return D0_SAMPLE_TYPE_VOLUME
;
342 case TGSI_TEXTURE_CUBE
:
343 return D0_SAMPLE_TYPE_CUBE
;
346 i915_program_error(p
, "TexSrc type");
353 * Generate texel lookup instruction.
356 emit_tex(struct i915_fp_compile
*p
,
357 const struct tgsi_full_instruction
*inst
,
360 uint texture
= inst
->InstructionExtTexture
.Texture
;
361 uint unit
= inst
->FullSrcRegisters
[1].SrcRegister
.Index
;
362 uint tex
= translate_tex_src_target( p
, texture
);
363 uint sampler
= i915_emit_decl(p
, REG_TYPE_S
, unit
, tex
);
364 uint coord
= src_vector( p
, &inst
->FullSrcRegisters
[0]);
367 get_result_vector( p
, &inst
->FullDstRegisters
[0] ),
368 get_result_flags( inst
),
376 * Generate a simple arithmetic instruction
377 * \param opcode the i915 opcode
378 * \param numArgs the number of input/src arguments
381 emit_simple_arith(struct i915_fp_compile
*p
,
382 const struct tgsi_full_instruction
*inst
,
383 uint opcode
, uint numArgs
)
385 uint arg1
, arg2
, arg3
;
387 assert(numArgs
<= 3);
389 arg1
= (numArgs
< 1) ? 0 : src_vector( p
, &inst
->FullSrcRegisters
[0] );
390 arg2
= (numArgs
< 2) ? 0 : src_vector( p
, &inst
->FullSrcRegisters
[1] );
391 arg3
= (numArgs
< 3) ? 0 : src_vector( p
, &inst
->FullSrcRegisters
[2] );
395 get_result_vector( p
, &inst
->FullDstRegisters
[0]),
396 get_result_flags( inst
), 0,
403 /** As above, but swap the first two src regs */
405 emit_simple_arith_swap2(struct i915_fp_compile
*p
,
406 const struct tgsi_full_instruction
*inst
,
407 uint opcode
, uint numArgs
)
409 struct tgsi_full_instruction inst2
;
411 assert(numArgs
== 2);
413 /* transpose first two registers */
415 inst2
.FullSrcRegisters
[0] = inst
->FullSrcRegisters
[1];
416 inst2
.FullSrcRegisters
[1] = inst
->FullSrcRegisters
[0];
418 emit_simple_arith(p
, &inst2
, opcode
, numArgs
);
423 #define M_PI 3.14159265358979323846
427 * Translate TGSI instruction to i915 instruction.
431 * SIN, COS -- could use another taylor step?
432 * LIT -- results seem a little different to sw mesa
433 * LOG -- different to mesa on negative numbers, but this is conformant.
436 i915_translate_instruction(struct i915_fp_compile
*p
,
437 const struct tgsi_full_instruction
*inst
)
440 uint src0
, src1
, src2
, flags
;
443 switch (inst
->Instruction
.Opcode
) {
444 case TGSI_OPCODE_ABS
:
445 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
448 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
449 get_result_flags(inst
), 0,
450 src0
, negate(src0
, 1, 1, 1, 1), 0);
453 case TGSI_OPCODE_ADD
:
454 emit_simple_arith(p
, inst
, A0_ADD
, 2);
457 case TGSI_OPCODE_CMP
:
458 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
459 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
460 src2
= src_vector(p
, &inst
->FullSrcRegisters
[2]);
461 i915_emit_arith(p
, A0_CMP
,
462 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
463 get_result_flags(inst
),
464 0, src0
, src2
, src1
); /* NOTE: order of src2, src1 */
467 case TGSI_OPCODE_COS
:
468 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
469 tmp
= i915_get_utemp(p
);
473 tmp
, A0_DEST_CHANNEL_X
, 0,
474 src0
, i915_emit_const1f(p
, 1.0f
/ (float) (M_PI
* 2.0)), 0);
476 i915_emit_arith(p
, A0_MOD
, tmp
, A0_DEST_CHANNEL_X
, 0, tmp
, 0, 0);
478 /* By choosing different taylor constants, could get rid of this mul:
482 tmp
, A0_DEST_CHANNEL_X
, 0,
483 tmp
, i915_emit_const1f(p
, (float) (M_PI
* 2.0)), 0);
486 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
487 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
488 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
489 * result = DP4 t0, cos_constants
493 tmp
, A0_DEST_CHANNEL_XY
, 0,
494 swizzle(tmp
, X
, X
, ONE
, ONE
),
495 swizzle(tmp
, X
, ONE
, ONE
, ONE
), 0);
499 tmp
, A0_DEST_CHANNEL_XYZ
, 0,
500 swizzle(tmp
, X
, Y
, X
, ONE
),
501 swizzle(tmp
, X
, X
, ONE
, ONE
), 0);
505 tmp
, A0_DEST_CHANNEL_XYZ
, 0,
506 swizzle(tmp
, X
, X
, Z
, ONE
),
507 swizzle(tmp
, Z
, ONE
, ONE
, ONE
), 0);
511 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
512 get_result_flags(inst
), 0,
513 swizzle(tmp
, ONE
, Z
, Y
, X
),
514 i915_emit_const4fv(p
, cos_constants
), 0);
517 case TGSI_OPCODE_DP3
:
518 emit_simple_arith(p
, inst
, A0_DP3
, 2);
521 case TGSI_OPCODE_DP4
:
522 emit_simple_arith(p
, inst
, A0_DP4
, 2);
525 case TGSI_OPCODE_DPH
:
526 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
527 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
531 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
532 get_result_flags(inst
), 0,
533 swizzle(src0
, X
, Y
, Z
, ONE
), src1
, 0);
536 case TGSI_OPCODE_DST
:
537 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
538 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
540 /* result[0] = 1 * 1;
541 * result[1] = a[1] * b[1];
542 * result[2] = a[2] * 1;
543 * result[3] = 1 * b[3];
547 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
548 get_result_flags(inst
), 0,
549 swizzle(src0
, ONE
, Y
, Z
, ONE
),
550 swizzle(src1
, ONE
, Y
, ONE
, W
), 0);
553 case TGSI_OPCODE_END
:
557 case TGSI_OPCODE_EX2
:
558 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
562 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
563 get_result_flags(inst
), 0,
564 swizzle(src0
, X
, X
, X
, X
), 0, 0);
567 case TGSI_OPCODE_FLR
:
568 emit_simple_arith(p
, inst
, A0_FLR
, 1);
571 case TGSI_OPCODE_FRC
:
572 emit_simple_arith(p
, inst
, A0_FRC
, 1);
575 case TGSI_OPCODE_KIL
:
576 /* kill if src[0].x < 0 || src[0].y < 0 ... */
577 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
578 tmp
= i915_get_utemp(p
);
581 tmp
, /* dest reg: a dummy reg */
582 A0_DEST_CHANNEL_ALL
, /* dest writemask */
585 T0_TEXKILL
); /* opcode */
588 case TGSI_OPCODE_KILP
:
589 assert(0); /* not tested yet */
592 case TGSI_OPCODE_LG2
:
593 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
597 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
598 get_result_flags(inst
), 0,
599 swizzle(src0
, X
, X
, X
, X
), 0, 0);
602 case TGSI_OPCODE_LIT
:
603 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
604 tmp
= i915_get_utemp(p
);
606 /* tmp = max( a.xyzw, a.00zw )
607 * XXX: Clamp tmp.w to -128..128
609 * tmp.y = tmp.w * tmp.y
611 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
613 i915_emit_arith(p
, A0_MAX
, tmp
, A0_DEST_CHANNEL_ALL
, 0,
614 src0
, swizzle(src0
, ZERO
, ZERO
, Z
, W
), 0);
616 i915_emit_arith(p
, A0_LOG
, tmp
, A0_DEST_CHANNEL_Y
, 0,
617 swizzle(tmp
, Y
, Y
, Y
, Y
), 0, 0);
619 i915_emit_arith(p
, A0_MUL
, tmp
, A0_DEST_CHANNEL_Y
, 0,
620 swizzle(tmp
, ZERO
, Y
, ZERO
, ZERO
),
621 swizzle(tmp
, ZERO
, W
, ZERO
, ZERO
), 0);
623 i915_emit_arith(p
, A0_EXP
, tmp
, A0_DEST_CHANNEL_Y
, 0,
624 swizzle(tmp
, Y
, Y
, Y
, Y
), 0, 0);
626 i915_emit_arith(p
, A0_CMP
,
627 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
628 get_result_flags(inst
), 0,
629 negate(swizzle(tmp
, ONE
, ONE
, X
, ONE
), 0, 0, 1, 0),
630 swizzle(tmp
, ONE
, X
, ZERO
, ONE
),
631 swizzle(tmp
, ONE
, X
, Y
, ONE
));
635 case TGSI_OPCODE_LRP
:
636 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
637 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
638 src2
= src_vector(p
, &inst
->FullSrcRegisters
[2]);
639 flags
= get_result_flags(inst
);
640 tmp
= i915_get_utemp(p
);
647 * result = (-c)*a + tmp
649 i915_emit_arith(p
, A0_MAD
, tmp
,
650 flags
& A0_DEST_CHANNEL_ALL
, 0, src1
, src0
, src2
);
652 i915_emit_arith(p
, A0_MAD
,
653 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
654 flags
, 0, negate(src2
, 1, 1, 1, 1), src0
, tmp
);
657 case TGSI_OPCODE_MAD
:
658 emit_simple_arith(p
, inst
, A0_MAD
, 3);
661 case TGSI_OPCODE_MAX
:
662 emit_simple_arith(p
, inst
, A0_MAX
, 2);
665 case TGSI_OPCODE_MIN
:
666 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
667 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
668 tmp
= i915_get_utemp(p
);
669 flags
= get_result_flags(inst
);
673 tmp
, flags
& A0_DEST_CHANNEL_ALL
, 0,
674 negate(src0
, 1, 1, 1, 1),
675 negate(src1
, 1, 1, 1, 1), 0);
679 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
680 flags
, 0, negate(tmp
, 1, 1, 1, 1), 0, 0);
683 case TGSI_OPCODE_MOV
:
684 case TGSI_OPCODE_SWZ
:
685 emit_simple_arith(p
, inst
, A0_MOV
, 1);
688 case TGSI_OPCODE_MUL
:
689 emit_simple_arith(p
, inst
, A0_MUL
, 2);
692 case TGSI_OPCODE_POW
:
693 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
694 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
695 tmp
= i915_get_utemp(p
);
696 flags
= get_result_flags(inst
);
698 /* XXX: masking on intermediate values, here and elsewhere.
702 tmp
, A0_DEST_CHANNEL_X
, 0,
703 swizzle(src0
, X
, X
, X
, X
), 0, 0);
705 i915_emit_arith(p
, A0_MUL
, tmp
, A0_DEST_CHANNEL_X
, 0, tmp
, src1
, 0);
709 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
710 flags
, 0, swizzle(tmp
, X
, X
, X
, X
), 0, 0);
713 case TGSI_OPCODE_RET
:
717 case TGSI_OPCODE_RCP
:
718 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
722 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
723 get_result_flags(inst
), 0,
724 swizzle(src0
, X
, X
, X
, X
), 0, 0);
727 case TGSI_OPCODE_RSQ
:
728 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
732 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
733 get_result_flags(inst
), 0,
734 swizzle(src0
, X
, X
, X
, X
), 0, 0);
737 case TGSI_OPCODE_SCS
:
738 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
739 tmp
= i915_get_utemp(p
);
742 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
743 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
744 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
745 * scs.x = DP4 t1, sin_constants
746 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
747 * scs.y = DP4 t1, cos_constants
751 tmp
, A0_DEST_CHANNEL_XY
, 0,
752 swizzle(src0
, X
, X
, ONE
, ONE
),
753 swizzle(src0
, X
, ONE
, ONE
, ONE
), 0);
757 tmp
, A0_DEST_CHANNEL_ALL
, 0,
758 swizzle(tmp
, X
, Y
, X
, Y
),
759 swizzle(tmp
, X
, X
, ONE
, ONE
), 0);
761 writemask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
763 if (writemask
& TGSI_WRITEMASK_Y
) {
766 if (writemask
& TGSI_WRITEMASK_X
)
767 tmp1
= i915_get_utemp(p
);
773 tmp1
, A0_DEST_CHANNEL_ALL
, 0,
774 swizzle(tmp
, X
, Y
, Y
, W
),
775 swizzle(tmp
, X
, Z
, ONE
, ONE
), 0);
779 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
780 A0_DEST_CHANNEL_Y
, 0,
781 swizzle(tmp1
, W
, Z
, Y
, X
),
782 i915_emit_const4fv(p
, sin_constants
), 0);
785 if (writemask
& TGSI_WRITEMASK_X
) {
788 tmp
, A0_DEST_CHANNEL_XYZ
, 0,
789 swizzle(tmp
, X
, X
, Z
, ONE
),
790 swizzle(tmp
, Z
, ONE
, ONE
, ONE
), 0);
794 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
795 A0_DEST_CHANNEL_X
, 0,
796 swizzle(tmp
, ONE
, Z
, Y
, X
),
797 i915_emit_const4fv(p
, cos_constants
), 0);
801 case TGSI_OPCODE_SGE
:
802 emit_simple_arith(p
, inst
, A0_SGE
, 2);
805 case TGSI_OPCODE_SLE
:
806 /* like SGE, but swap reg0, reg1 */
807 emit_simple_arith_swap2(p
, inst
, A0_SGE
, 2);
810 case TGSI_OPCODE_SIN
:
811 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
812 tmp
= i915_get_utemp(p
);
816 tmp
, A0_DEST_CHANNEL_X
, 0,
817 src0
, i915_emit_const1f(p
, 1.0f
/ (float) (M_PI
* 2.0)), 0);
819 i915_emit_arith(p
, A0_MOD
, tmp
, A0_DEST_CHANNEL_X
, 0, tmp
, 0, 0);
821 /* By choosing different taylor constants, could get rid of this mul:
825 tmp
, A0_DEST_CHANNEL_X
, 0,
826 tmp
, i915_emit_const1f(p
, (float) (M_PI
* 2.0)), 0);
829 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
830 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
831 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
832 * result = DP4 t1.wzyx, sin_constants
836 tmp
, A0_DEST_CHANNEL_XY
, 0,
837 swizzle(tmp
, X
, X
, ONE
, ONE
),
838 swizzle(tmp
, X
, ONE
, ONE
, ONE
), 0);
842 tmp
, A0_DEST_CHANNEL_ALL
, 0,
843 swizzle(tmp
, X
, Y
, X
, Y
),
844 swizzle(tmp
, X
, X
, ONE
, ONE
), 0);
848 tmp
, A0_DEST_CHANNEL_ALL
, 0,
849 swizzle(tmp
, X
, Y
, Y
, W
),
850 swizzle(tmp
, X
, Z
, ONE
, ONE
), 0);
854 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
855 get_result_flags(inst
), 0,
856 swizzle(tmp
, W
, Z
, Y
, X
),
857 i915_emit_const4fv(p
, sin_constants
), 0);
860 case TGSI_OPCODE_SLT
:
861 emit_simple_arith(p
, inst
, A0_SLT
, 2);
864 case TGSI_OPCODE_SGT
:
865 /* like SLT, but swap reg0, reg1 */
866 emit_simple_arith_swap2(p
, inst
, A0_SLT
, 2);
869 case TGSI_OPCODE_SUB
:
870 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
871 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
875 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
876 get_result_flags(inst
), 0,
877 src0
, negate(src1
, 1, 1, 1, 1), 0);
880 case TGSI_OPCODE_TEX
:
881 emit_tex(p
, inst
, T0_TEXLD
);
884 case TGSI_OPCODE_TXB
:
885 emit_tex(p
, inst
, T0_TEXLDB
);
888 case TGSI_OPCODE_TXP
:
889 emit_tex(p
, inst
, T0_TEXLDP
);
892 case TGSI_OPCODE_XPD
:
894 * result.x = src0.y * src1.z - src0.z * src1.y;
895 * result.y = src0.z * src1.x - src0.x * src1.z;
896 * result.z = src0.x * src1.y - src0.y * src1.x;
899 src0
= src_vector(p
, &inst
->FullSrcRegisters
[0]);
900 src1
= src_vector(p
, &inst
->FullSrcRegisters
[1]);
901 tmp
= i915_get_utemp(p
);
905 tmp
, A0_DEST_CHANNEL_ALL
, 0,
906 swizzle(src0
, Z
, X
, Y
, ONE
),
907 swizzle(src1
, Y
, Z
, X
, ONE
), 0);
911 get_result_vector(p
, &inst
->FullDstRegisters
[0]),
912 get_result_flags(inst
), 0,
913 swizzle(src0
, Y
, Z
, X
, ONE
),
914 swizzle(src1
, Z
, X
, Y
, ONE
),
915 negate(tmp
, 1, 1, 1, 0));
919 i915_program_error(p
, "bad opcode %d", inst
->Instruction
.Opcode
);
924 i915_release_utemps(p
);
929 * Translate TGSI fragment shader into i915 hardware instructions.
930 * \param p the translation state
931 * \param tokens the TGSI token array
934 i915_translate_instructions(struct i915_fp_compile
*p
,
935 const struct tgsi_token
*tokens
)
937 struct i915_fragment_shader
*ifs
= p
->shader
;
938 struct tgsi_parse_context parse
;
940 tgsi_parse_init( &parse
, tokens
);
942 while( !tgsi_parse_end_of_tokens( &parse
) ) {
944 tgsi_parse_token( &parse
);
946 switch( parse
.FullToken
.Token
.Type
) {
947 case TGSI_TOKEN_TYPE_DECLARATION
:
948 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
949 == TGSI_FILE_CONSTANT
) {
951 for (i
= parse
.FullToken
.FullDeclaration
.DeclarationRange
.First
;
952 i
<= parse
.FullToken
.FullDeclaration
.DeclarationRange
.Last
;
954 assert(ifs
->constant_flags
[i
] == 0x0);
955 ifs
->constant_flags
[i
] = I915_CONSTFLAG_USER
;
956 ifs
->num_constants
= MAX2(ifs
->num_constants
, i
+ 1);
959 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
960 == TGSI_FILE_TEMPORARY
) {
962 for (i
= parse
.FullToken
.FullDeclaration
.DeclarationRange
.First
;
963 i
<= parse
.FullToken
.FullDeclaration
.DeclarationRange
.Last
;
965 assert(i
< I915_MAX_TEMPORARY
);
966 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
967 p
->temp_flag
|= (1 << i
); /* mark temp as used */
972 case TGSI_TOKEN_TYPE_IMMEDIATE
:
974 const struct tgsi_full_immediate
*imm
975 = &parse
.FullToken
.FullImmediate
;
976 const uint pos
= p
->num_immediates
++;
978 assert( imm
->Immediate
.NrTokens
<= 4 + 1 );
979 for (j
= 0; j
< imm
->Immediate
.NrTokens
- 1; j
++) {
980 p
->immediates
[pos
][j
] = imm
->u
[j
].Float
;
985 case TGSI_TOKEN_TYPE_INSTRUCTION
:
986 if (p
->first_instruction
) {
987 /* resolve location of immediates */
989 for (i
= 0; i
< p
->num_immediates
; i
++) {
990 /* find constant slot for this immediate */
991 for (j
= 0; j
< I915_MAX_CONSTANT
; j
++) {
992 if (ifs
->constant_flags
[j
] == 0x0) {
993 memcpy(ifs
->constants
[j
],
996 /*printf("immediate %d maps to const %d\n", i, j);*/
997 ifs
->constant_flags
[j
] = 0xf; /* all four comps used */
998 p
->immediates_map
[i
] = j
;
999 ifs
->num_constants
= MAX2(ifs
->num_constants
, j
+ 1);
1005 p
->first_instruction
= FALSE
;
1008 i915_translate_instruction(p
, &parse
.FullToken
.FullInstruction
);
1017 tgsi_parse_free (&parse
);
1021 static struct i915_fp_compile
*
1022 i915_init_compile(struct i915_context
*i915
,
1023 struct i915_fragment_shader
*ifs
)
1025 struct i915_fp_compile
*p
= CALLOC_STRUCT(i915_fp_compile
);
1029 /* Put new constants at end of const buffer, growing downward.
1030 * The problem is we don't know how many user-defined constants might
1031 * be specified with pipe->set_constant_buffer().
1032 * Should pre-scan the user's program to determine the highest-numbered
1033 * constant referenced.
1035 ifs
->num_constants
= 0;
1036 memset(ifs
->constant_flags
, 0, sizeof(ifs
->constant_flags
));
1038 p
->first_instruction
= TRUE
;
1040 p
->nr_tex_indirect
= 1; /* correct? */
1043 p
->nr_decl_insn
= 0;
1045 p
->csr
= p
->program
;
1046 p
->decl
= p
->declarations
;
1049 p
->temp_flag
= ~0x0 << I915_MAX_TEMPORARY
;
1050 p
->utemp_flag
= ~0x7;
1054 /* initialize the first program word */
1055 *(p
->decl
++) = _3DSTATE_PIXEL_SHADER_PROGRAM
;
1061 /* Copy compile results to the fragment program struct and destroy the
1062 * compilation context.
1065 i915_fini_compile(struct i915_context
*i915
, struct i915_fp_compile
*p
)
1067 struct i915_fragment_shader
*ifs
= p
->shader
;
1068 unsigned long program_size
= (unsigned long) (p
->csr
- p
->program
);
1069 unsigned long decl_size
= (unsigned long) (p
->decl
- p
->declarations
);
1071 if (p
->nr_tex_indirect
> I915_MAX_TEX_INDIRECT
)
1072 i915_program_error(p
, "Exceeded max nr indirect texture lookups");
1074 if (p
->nr_tex_insn
> I915_MAX_TEX_INSN
)
1075 i915_program_error(p
, "Exceeded max TEX instructions");
1077 if (p
->nr_alu_insn
> I915_MAX_ALU_INSN
)
1078 i915_program_error(p
, "Exceeded max ALU instructions");
1080 if (p
->nr_decl_insn
> I915_MAX_DECL_INSN
)
1081 i915_program_error(p
, "Exceeded max DECL instructions");
1084 p
->NumNativeInstructions
= 0;
1085 p
->NumNativeAluInstructions
= 0;
1086 p
->NumNativeTexInstructions
= 0;
1087 p
->NumNativeTexIndirections
= 0;
1089 i915_use_passthrough_shader(ifs
);
1092 p
->NumNativeInstructions
1093 = p
->nr_alu_insn
+ p
->nr_tex_insn
+ p
->nr_decl_insn
;
1094 p
->NumNativeAluInstructions
= p
->nr_alu_insn
;
1095 p
->NumNativeTexInstructions
= p
->nr_tex_insn
;
1096 p
->NumNativeTexIndirections
= p
->nr_tex_indirect
;
1098 /* patch in the program length */
1099 p
->declarations
[0] |= program_size
+ decl_size
- 2;
1101 /* Copy compilation results to fragment program struct:
1103 assert(!ifs
->program
);
1105 = (uint
*) MALLOC((program_size
+ decl_size
) * sizeof(uint
));
1107 ifs
->program_len
= program_size
+ decl_size
;
1109 memcpy(ifs
->program
,
1111 decl_size
* sizeof(uint
));
1113 memcpy(ifs
->program
+ decl_size
,
1115 program_size
* sizeof(uint
));
1119 /* Release the compilation struct:
1126 * Find an unused texture coordinate slot to use for fragment WPOS.
1127 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1130 i915_find_wpos_space(struct i915_fp_compile
*p
)
1134 = p
->shader
->inputs_read
| (1 << TGSI_ATTRIB_POS
); /*XXX hack*/
1139 if (inputs
& (1 << TGSI_ATTRIB_POS
)) {
1140 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
1141 if ((inputs
& (1 << (TGSI_ATTRIB_TEX0
+ i
))) == 0) {
1147 i915_program_error(p
, "No free texcoord for wpos value");
1150 if (p
->shader
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
) {
1151 /* frag shader using the fragment position input */
1163 * Rather than trying to intercept and jiggle depth writes during
1164 * emit, just move the value into its correct position at the end of
1168 i915_fixup_depth_write(struct i915_fp_compile
*p
)
1170 /* XXX assuming pos/depth is always in output[0] */
1171 if (p
->shader
->info
.output_semantic_name
[0] == TGSI_SEMANTIC_POSITION
) {
1172 const uint depth
= UREG(REG_TYPE_OD
, 0);
1175 A0_MOV
, /* opcode */
1176 depth
, /* dest reg */
1177 A0_DEST_CHANNEL_W
, /* write mask */
1179 swizzle(depth
, X
, Y
, Z
, Z
), /* src0 */
1180 0, 0 /* src1, src2 */);
1186 i915_translate_fragment_program( struct i915_context
*i915
,
1187 struct i915_fragment_shader
*fs
)
1189 struct i915_fp_compile
*p
= i915_init_compile(i915
, fs
);
1190 const struct tgsi_token
*tokens
= fs
->state
.tokens
;
1192 i915_find_wpos_space(p
);
1195 tgsi_dump(tokens
, 0);
1198 i915_translate_instructions(p
, tokens
);
1199 i915_fixup_depth_write(p
);
1201 i915_fini_compile(i915
, p
);