bbc901eed846fd697f2cae620102e1064e08c856
[mesa.git] / src / gallium / drivers / i915 / i915_screen.c
1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "draw/draw_context.h"
30 #include "os/os_misc.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_inlines.h"
34 #include "util/u_memory.h"
35 #include "util/u_string.h"
36
37 #include "i915_reg.h"
38 #include "i915_debug.h"
39 #include "i915_context.h"
40 #include "i915_screen.h"
41 #include "i915_resource.h"
42 #include "i915_winsys.h"
43 #include "i915_public.h"
44
45
46 /*
47 * Probe functions
48 */
49
50
51 static const char *
52 i915_get_vendor(struct pipe_screen *screen)
53 {
54 return "Mesa Project";
55 }
56
57 static const char *
58 i915_get_name(struct pipe_screen *screen)
59 {
60 static char buffer[128];
61 const char *chipset;
62
63 switch (i915_screen(screen)->iws->pci_id) {
64 case PCI_CHIP_I915_G:
65 chipset = "915G";
66 break;
67 case PCI_CHIP_I915_GM:
68 chipset = "915GM";
69 break;
70 case PCI_CHIP_I945_G:
71 chipset = "945G";
72 break;
73 case PCI_CHIP_I945_GM:
74 chipset = "945GM";
75 break;
76 case PCI_CHIP_I945_GME:
77 chipset = "945GME";
78 break;
79 case PCI_CHIP_G33_G:
80 chipset = "G33";
81 break;
82 case PCI_CHIP_Q35_G:
83 chipset = "Q35";
84 break;
85 case PCI_CHIP_Q33_G:
86 chipset = "Q33";
87 break;
88 case PCI_CHIP_PINEVIEW_G:
89 chipset = "Pineview G";
90 break;
91 case PCI_CHIP_PINEVIEW_M:
92 chipset = "Pineview M";
93 break;
94 default:
95 chipset = "unknown";
96 break;
97 }
98
99 util_snprintf(buffer, sizeof(buffer), "i915 (chipset: %s)", chipset);
100 return buffer;
101 }
102
103 static int
104 i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap cap)
105 {
106 switch(shader) {
107 case PIPE_SHADER_VERTEX:
108 switch (cap) {
109 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
110 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
111 if (debug_get_bool_option("DRAW_USE_LLVM", TRUE))
112 return PIPE_MAX_SAMPLERS;
113 else
114 return 0;
115 default:
116 return draw_get_shader_param(shader, cap);
117 }
118 case PIPE_SHADER_FRAGMENT:
119 /* XXX: some of these are just shader model 2.0 values, fix this! */
120 switch(cap) {
121 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
122 return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
123 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
124 return I915_MAX_ALU_INSN;
125 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
126 return I915_MAX_TEX_INSN;
127 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
128 return 8;
129 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
130 return 0;
131 case PIPE_SHADER_CAP_MAX_INPUTS:
132 return 10;
133 case PIPE_SHADER_CAP_MAX_OUTPUTS:
134 return 1;
135 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
136 return 32 * sizeof(float[4]);
137 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
138 return 1;
139 case PIPE_SHADER_CAP_MAX_TEMPS:
140 return 12; /* XXX: 12 -> 32 ? */
141 case PIPE_SHADER_CAP_MAX_PREDS:
142 return 0;
143 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
144 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
145 return 0;
146 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
147 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
148 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
149 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
150 return 1;
151 case PIPE_SHADER_CAP_SUBROUTINES:
152 return 0;
153 case PIPE_SHADER_CAP_INTEGERS:
154 return 0;
155 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
156 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
157 return I915_TEX_UNITS;
158 default:
159 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
160 return 0;
161 }
162 break;
163 default:
164 return 0;
165 }
166
167 }
168
169 static int
170 i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
171 {
172 struct i915_screen *is = i915_screen(screen);
173
174 switch (cap) {
175 /* Supported features (boolean caps). */
176 case PIPE_CAP_ANISOTROPIC_FILTER:
177 case PIPE_CAP_NPOT_TEXTURES:
178 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
179 case PIPE_CAP_POINT_SPRITE:
180 case PIPE_CAP_PRIMITIVE_RESTART: /* draw module */
181 case PIPE_CAP_TEXTURE_SHADOW_MAP:
182 case PIPE_CAP_TWO_SIDED_STENCIL:
183 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
184 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
185 case PIPE_CAP_TGSI_INSTANCEID:
186 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
187 case PIPE_CAP_USER_VERTEX_BUFFERS:
188 case PIPE_CAP_USER_INDEX_BUFFERS:
189 case PIPE_CAP_USER_CONSTANT_BUFFERS:
190 return 1;
191
192 /* Unsupported features (boolean caps). */
193 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
194 case PIPE_CAP_DEPTH_CLIP_DISABLE:
195 case PIPE_CAP_INDEP_BLEND_ENABLE:
196 case PIPE_CAP_INDEP_BLEND_FUNC:
197 case PIPE_CAP_SHADER_STENCIL_EXPORT:
198 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
199 case PIPE_CAP_TEXTURE_SWIZZLE:
200 case PIPE_CAP_QUERY_TIME_ELAPSED:
201 case PIPE_CAP_SM3:
202 case PIPE_CAP_SEAMLESS_CUBE_MAP:
203 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
204 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
205 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
206 case PIPE_CAP_CONDITIONAL_RENDER:
207 case PIPE_CAP_TEXTURE_BARRIER:
208 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
209 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
210 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
211 case PIPE_CAP_START_INSTANCE:
212 case PIPE_CAP_QUERY_TIMESTAMP:
213 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
214 case PIPE_CAP_TEXTURE_MULTISAMPLE:
215 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
216 case PIPE_CAP_CUBE_MAP_ARRAY:
217 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
218 case PIPE_CAP_TGSI_TEXCOORD:
219 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
220 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
221 case PIPE_CAP_TEXTURE_GATHER_SM5:
222 case PIPE_CAP_FAKE_SW_MSAA:
223 case PIPE_CAP_TEXTURE_QUERY_LOD:
224 case PIPE_CAP_SAMPLE_SHADING:
225 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
226 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
227 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
228 case PIPE_CAP_CLIP_HALFZ:
229 case PIPE_CAP_VERTEXID_NOBASE:
230 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
231 return 0;
232
233 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
234 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
235 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
236 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
237 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
238 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
239 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
240 case PIPE_CAP_DRAW_INDIRECT:
241 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
242 case PIPE_CAP_SAMPLER_VIEW_TARGET:
243 return 0;
244
245 case PIPE_CAP_MAX_VIEWPORTS:
246 return 1;
247
248 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
249 return 64;
250
251 case PIPE_CAP_GLSL_FEATURE_LEVEL:
252 return 120;
253
254 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
255 return 16;
256
257 /* Features we can lie about (boolean caps). */
258 case PIPE_CAP_OCCLUSION_QUERY:
259 return is->debug.lie ? 1 : 0;
260
261 /* Texturing. */
262 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
263 return I915_MAX_TEXTURE_2D_LEVELS;
264 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
265 return I915_MAX_TEXTURE_3D_LEVELS;
266 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
267 return I915_MAX_TEXTURE_2D_LEVELS;
268 case PIPE_CAP_MIN_TEXEL_OFFSET:
269 case PIPE_CAP_MAX_TEXEL_OFFSET:
270 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
271 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
272 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
273 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
274 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
275 return 0;
276
277 /* Render targets. */
278 case PIPE_CAP_MAX_RENDER_TARGETS:
279 return 1;
280
281 /* Geometry shader output, unsupported. */
282 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
283 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
284 case PIPE_CAP_MAX_VERTEX_STREAMS:
285 return 0;
286
287 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
288 return 2048;
289
290 /* Fragment coordinate conventions. */
291 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
292 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
293 return 1;
294 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
295 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
296 return 0;
297 case PIPE_CAP_ENDIANNESS:
298 return PIPE_ENDIAN_LITTLE;
299
300 case PIPE_CAP_VENDOR_ID:
301 return 0x8086;
302 case PIPE_CAP_DEVICE_ID:
303 return is->iws->pci_id;
304 case PIPE_CAP_ACCELERATED:
305 return 1;
306 case PIPE_CAP_VIDEO_MEMORY: {
307 /* Once a batch uses more than 75% of the maximum mappable size, we
308 * assume that there's some fragmentation, and we start doing extra
309 * flushing, etc. That's the big cliff apps will care about.
310 */
311 const int gpu_mappable_megabytes = is->iws->aperture_size(is->iws) * 3 / 4;
312 uint64_t system_memory;
313
314 if (!os_get_total_physical_memory(&system_memory))
315 return 0;
316
317 return MIN2(gpu_mappable_megabytes, (int)(system_memory >> 20));
318 }
319 case PIPE_CAP_UMA:
320 return 1;
321
322 default:
323 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
324 return 0;
325 }
326 }
327
328 static float
329 i915_get_paramf(struct pipe_screen *screen, enum pipe_capf cap)
330 {
331 switch(cap) {
332 case PIPE_CAPF_MAX_LINE_WIDTH:
333 /* fall-through */
334 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
335 return 7.5;
336
337 case PIPE_CAPF_MAX_POINT_WIDTH:
338 /* fall-through */
339 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
340 return 255.0;
341
342 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
343 return 4.0;
344
345 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
346 return 16.0;
347
348 default:
349 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
350 return 0;
351 }
352 }
353
354 boolean
355 i915_is_format_supported(struct pipe_screen *screen,
356 enum pipe_format format,
357 enum pipe_texture_target target,
358 unsigned sample_count,
359 unsigned tex_usage)
360 {
361 static const enum pipe_format tex_supported[] = {
362 PIPE_FORMAT_B8G8R8A8_UNORM,
363 PIPE_FORMAT_B8G8R8A8_SRGB,
364 PIPE_FORMAT_B8G8R8X8_UNORM,
365 PIPE_FORMAT_R8G8B8A8_UNORM,
366 PIPE_FORMAT_R8G8B8X8_UNORM,
367 PIPE_FORMAT_B4G4R4A4_UNORM,
368 PIPE_FORMAT_B5G6R5_UNORM,
369 PIPE_FORMAT_B5G5R5A1_UNORM,
370 PIPE_FORMAT_B10G10R10A2_UNORM,
371 PIPE_FORMAT_L8_UNORM,
372 PIPE_FORMAT_A8_UNORM,
373 PIPE_FORMAT_I8_UNORM,
374 PIPE_FORMAT_L8A8_UNORM,
375 PIPE_FORMAT_UYVY,
376 PIPE_FORMAT_YUYV,
377 /* XXX why not?
378 PIPE_FORMAT_Z16_UNORM, */
379 PIPE_FORMAT_DXT1_RGB,
380 PIPE_FORMAT_DXT1_RGBA,
381 PIPE_FORMAT_DXT3_RGBA,
382 PIPE_FORMAT_DXT5_RGBA,
383 PIPE_FORMAT_Z24X8_UNORM,
384 PIPE_FORMAT_Z24_UNORM_S8_UINT,
385 PIPE_FORMAT_NONE /* list terminator */
386 };
387 static const enum pipe_format render_supported[] = {
388 PIPE_FORMAT_B8G8R8A8_UNORM,
389 PIPE_FORMAT_B8G8R8X8_UNORM,
390 PIPE_FORMAT_R8G8B8A8_UNORM,
391 PIPE_FORMAT_R8G8B8X8_UNORM,
392 PIPE_FORMAT_B5G6R5_UNORM,
393 PIPE_FORMAT_B5G5R5A1_UNORM,
394 PIPE_FORMAT_B4G4R4A4_UNORM,
395 PIPE_FORMAT_B10G10R10A2_UNORM,
396 PIPE_FORMAT_L8_UNORM,
397 PIPE_FORMAT_A8_UNORM,
398 PIPE_FORMAT_I8_UNORM,
399 PIPE_FORMAT_NONE /* list terminator */
400 };
401 static const enum pipe_format depth_supported[] = {
402 /* XXX why not?
403 PIPE_FORMAT_Z16_UNORM, */
404 PIPE_FORMAT_Z24X8_UNORM,
405 PIPE_FORMAT_Z24_UNORM_S8_UINT,
406 PIPE_FORMAT_NONE /* list terminator */
407 };
408 const enum pipe_format *list;
409 uint i;
410
411 if (!util_format_is_supported(format, tex_usage))
412 return FALSE;
413
414 if (sample_count > 1)
415 return FALSE;
416
417 if(tex_usage & PIPE_BIND_DEPTH_STENCIL)
418 list = depth_supported;
419 else if (tex_usage & PIPE_BIND_RENDER_TARGET)
420 list = render_supported;
421 else if (tex_usage & PIPE_BIND_SAMPLER_VIEW)
422 list = tex_supported;
423 else
424 return TRUE; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
425
426 for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
427 if (list[i] == format)
428 return TRUE;
429 }
430
431 return FALSE;
432 }
433
434
435 /*
436 * Fence functions
437 */
438
439
440 static void
441 i915_fence_reference(struct pipe_screen *screen,
442 struct pipe_fence_handle **ptr,
443 struct pipe_fence_handle *fence)
444 {
445 struct i915_screen *is = i915_screen(screen);
446
447 is->iws->fence_reference(is->iws, ptr, fence);
448 }
449
450 static boolean
451 i915_fence_signalled(struct pipe_screen *screen,
452 struct pipe_fence_handle *fence)
453 {
454 struct i915_screen *is = i915_screen(screen);
455
456 return is->iws->fence_signalled(is->iws, fence) == 1;
457 }
458
459 static boolean
460 i915_fence_finish(struct pipe_screen *screen,
461 struct pipe_fence_handle *fence,
462 uint64_t timeout)
463 {
464 struct i915_screen *is = i915_screen(screen);
465
466 return is->iws->fence_finish(is->iws, fence) == 1;
467 }
468
469
470 /*
471 * Generic functions
472 */
473
474
475 static void
476 i915_flush_frontbuffer(struct pipe_screen *screen,
477 struct pipe_resource *resource,
478 unsigned level, unsigned layer,
479 void *winsys_drawable_handle,
480 struct pipe_box *sub_box)
481 {
482 /* XXX: Dummy right now. */
483 (void)screen;
484 (void)resource;
485 (void)level;
486 (void)layer;
487 (void)winsys_drawable_handle;
488 (void)sub_box;
489 }
490
491 static void
492 i915_destroy_screen(struct pipe_screen *screen)
493 {
494 struct i915_screen *is = i915_screen(screen);
495
496 if (is->iws)
497 is->iws->destroy(is->iws);
498
499 FREE(is);
500 }
501
502 /**
503 * Create a new i915_screen object
504 */
505 struct pipe_screen *
506 i915_screen_create(struct i915_winsys *iws)
507 {
508 struct i915_screen *is = CALLOC_STRUCT(i915_screen);
509
510 if (!is)
511 return NULL;
512
513 switch (iws->pci_id) {
514 case PCI_CHIP_I915_G:
515 case PCI_CHIP_I915_GM:
516 is->is_i945 = FALSE;
517 break;
518
519 case PCI_CHIP_I945_G:
520 case PCI_CHIP_I945_GM:
521 case PCI_CHIP_I945_GME:
522 case PCI_CHIP_G33_G:
523 case PCI_CHIP_Q33_G:
524 case PCI_CHIP_Q35_G:
525 case PCI_CHIP_PINEVIEW_G:
526 case PCI_CHIP_PINEVIEW_M:
527 is->is_i945 = TRUE;
528 break;
529
530 default:
531 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
532 __FUNCTION__, iws->pci_id);
533 FREE(is);
534 return NULL;
535 }
536
537 is->iws = iws;
538
539 is->base.destroy = i915_destroy_screen;
540 is->base.flush_frontbuffer = i915_flush_frontbuffer;
541
542 is->base.get_name = i915_get_name;
543 is->base.get_vendor = i915_get_vendor;
544 is->base.get_param = i915_get_param;
545 is->base.get_shader_param = i915_get_shader_param;
546 is->base.get_paramf = i915_get_paramf;
547 is->base.is_format_supported = i915_is_format_supported;
548
549 is->base.context_create = i915_create_context;
550
551 is->base.fence_reference = i915_fence_reference;
552 is->base.fence_signalled = i915_fence_signalled;
553 is->base.fence_finish = i915_fence_finish;
554
555 i915_init_screen_resource_functions(is);
556
557 i915_debug_init(is);
558
559 util_format_s3tc_init();
560
561 return &is->base;
562 }