nv50,nvc0: implement blit
[mesa.git] / src / gallium / drivers / i915 / i915_state_sampler.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "pipe/p_context.h"
29 #include "pipe/p_state.h"
30
31 #include "i915_state_inlines.h"
32 #include "i915_context.h"
33 #include "i915_reg.h"
34 #include "i915_state.h"
35 #include "i915_resource.h"
36
37
38 /*
39 * A note about min_lod & max_lod.
40 *
41 * There is a circular dependancy between the sampler state
42 * and the map state to be submitted to hw.
43 *
44 * Two condition must be meet:
45 * min_lod =< max_lod == true
46 * max_lod =< last_level == true
47 *
48 *
49 * This is all fine and dandy if it were for the fact that max_lod
50 * is set on the map state instead of the sampler state. That is
51 * the max_lod we submit on map is:
52 * max_lod = MIN2(last_level, max_lod);
53 *
54 * So we need to update the map state when we change samplers and
55 * we need to change the sampler state when map state is changed.
56 * The first part is done by calling update_texture in update_samplers
57 * and the second part is done else where in code tracking the state
58 * changes.
59 */
60
61 static void update_map(struct i915_context *i915,
62 uint unit,
63 const struct i915_texture *tex,
64 const struct i915_sampler_state *sampler,
65 const struct pipe_sampler_view* view,
66 uint state[2]);
67
68
69
70 /***********************************************************************
71 * Samplers
72 */
73
74 /**
75 * Compute i915 texture sampling state.
76 *
77 * Recalculate all state from scratch. Perhaps not the most
78 * efficient, but this has gotten complex enough that we need
79 * something which is understandable and reliable.
80 * \param state returns the 3 words of compute state
81 */
82 static void update_sampler(struct i915_context *i915,
83 uint unit,
84 const struct i915_sampler_state *sampler,
85 const struct i915_texture *tex,
86 unsigned state[3])
87 {
88 const struct pipe_resource *pt = &tex->b.b;
89 unsigned minlod, lastlod;
90
91 state[0] = sampler->state[0];
92 state[1] = sampler->state[1];
93 state[2] = sampler->state[2];
94
95 if (pt->format == PIPE_FORMAT_UYVY ||
96 pt->format == PIPE_FORMAT_YUYV)
97 state[0] |= SS2_COLORSPACE_CONVERSION;
98
99 /* 3D textures don't seem to respect the border color.
100 * Fallback if there's ever a danger that they might refer to
101 * it.
102 *
103 * Effectively this means fallback on 3D clamp or
104 * clamp_to_border.
105 *
106 * XXX: Check if this is true on i945.
107 * XXX: Check if this bug got fixed in release silicon.
108 */
109 #if 0
110 {
111 const unsigned ws = sampler->templ->wrap_s;
112 const unsigned wt = sampler->templ->wrap_t;
113 const unsigned wr = sampler->templ->wrap_r;
114 if (pt->target == PIPE_TEXTURE_3D &&
115 (sampler->templ->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
116 sampler->templ->mag_img_filter != PIPE_TEX_FILTER_NEAREST) &&
117 (ws == PIPE_TEX_WRAP_CLAMP ||
118 wt == PIPE_TEX_WRAP_CLAMP ||
119 wr == PIPE_TEX_WRAP_CLAMP ||
120 ws == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
121 wt == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
122 wr == PIPE_TEX_WRAP_CLAMP_TO_BORDER)) {
123 if (i915->conformance_mode > 0) {
124 assert(0);
125 /* sampler->fallback = true; */
126 /* TODO */
127 }
128 }
129 }
130 #endif
131
132 /* See note at the top of file */
133 minlod = sampler->minlod;
134 lastlod = pt->last_level << 4;
135
136 if (lastlod < minlod) {
137 minlod = lastlod;
138 }
139
140 state[1] |= (sampler->minlod << SS3_MIN_LOD_SHIFT);
141 state[1] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT);
142 }
143
144 static void update_samplers(struct i915_context *i915)
145 {
146 uint unit;
147
148 i915->current.sampler_enable_nr = 0;
149 i915->current.sampler_enable_flags = 0x0;
150
151 for (unit = 0; unit < i915->num_fragment_sampler_views && unit < i915->num_samplers;
152 unit++) {
153 /* determine unit enable/disable by looking for a bound texture */
154 /* could also examine the fragment program? */
155 if (i915->fragment_sampler_views[unit]) {
156 struct i915_texture *texture = i915_texture(i915->fragment_sampler_views[unit]->texture);
157
158 update_sampler(i915,
159 unit,
160 i915->sampler[unit], /* sampler state */
161 texture, /* texture */
162 i915->current.sampler[unit]); /* the result */
163 update_map(i915,
164 unit,
165 texture, /* texture */
166 i915->sampler[unit], /* sampler state */
167 i915->fragment_sampler_views[unit], /* sampler view */
168 i915->current.texbuffer[unit]); /* the result */
169
170 i915->current.sampler_enable_nr++;
171 i915->current.sampler_enable_flags |= (1 << unit);
172 }
173 }
174
175 i915->hardware_dirty |= I915_HW_SAMPLER | I915_HW_MAP;
176 }
177
178 struct i915_tracked_state i915_hw_samplers = {
179 "samplers",
180 update_samplers,
181 I915_NEW_SAMPLER | I915_NEW_SAMPLER_VIEW
182 };
183
184
185 /***********************************************************************
186 * Sampler views
187 */
188
189 static uint translate_texture_format(enum pipe_format pipeFormat,
190 const struct pipe_sampler_view* view)
191 {
192 if ( (view->swizzle_r != PIPE_SWIZZLE_RED ||
193 view->swizzle_g != PIPE_SWIZZLE_GREEN ||
194 view->swizzle_b != PIPE_SWIZZLE_BLUE ||
195 view->swizzle_a != PIPE_SWIZZLE_ALPHA ) &&
196 pipeFormat != PIPE_FORMAT_Z24_UNORM_S8_UINT &&
197 pipeFormat != PIPE_FORMAT_Z24X8_UNORM )
198 debug_printf("i915: unsupported texture swizzle for format %d\n", pipeFormat);
199
200 switch (pipeFormat) {
201 case PIPE_FORMAT_L8_UNORM:
202 return MAPSURF_8BIT | MT_8BIT_L8;
203 case PIPE_FORMAT_I8_UNORM:
204 return MAPSURF_8BIT | MT_8BIT_I8;
205 case PIPE_FORMAT_A8_UNORM:
206 return MAPSURF_8BIT | MT_8BIT_A8;
207 case PIPE_FORMAT_L8A8_UNORM:
208 return MAPSURF_16BIT | MT_16BIT_AY88;
209 case PIPE_FORMAT_B5G6R5_UNORM:
210 return MAPSURF_16BIT | MT_16BIT_RGB565;
211 case PIPE_FORMAT_B5G5R5A1_UNORM:
212 return MAPSURF_16BIT | MT_16BIT_ARGB1555;
213 case PIPE_FORMAT_B4G4R4A4_UNORM:
214 return MAPSURF_16BIT | MT_16BIT_ARGB4444;
215 case PIPE_FORMAT_B10G10R10A2_UNORM:
216 return MAPSURF_32BIT | MT_32BIT_ARGB2101010;
217 case PIPE_FORMAT_B8G8R8A8_UNORM:
218 case PIPE_FORMAT_B8G8R8A8_SRGB:
219 return MAPSURF_32BIT | MT_32BIT_ARGB8888;
220 case PIPE_FORMAT_B8G8R8X8_UNORM:
221 return MAPSURF_32BIT | MT_32BIT_XRGB8888;
222 case PIPE_FORMAT_R8G8B8A8_UNORM:
223 return MAPSURF_32BIT | MT_32BIT_ABGR8888;
224 case PIPE_FORMAT_R8G8B8X8_UNORM:
225 return MAPSURF_32BIT | MT_32BIT_XBGR8888;
226 case PIPE_FORMAT_YUYV:
227 return (MAPSURF_422 | MT_422_YCRCB_NORMAL);
228 case PIPE_FORMAT_UYVY:
229 return (MAPSURF_422 | MT_422_YCRCB_SWAPY);
230 #if 0
231 case PIPE_FORMAT_RGB_FXT1:
232 case PIPE_FORMAT_RGBA_FXT1:
233 return (MAPSURF_COMPRESSED | MT_COMPRESS_FXT1);
234 #endif
235 case PIPE_FORMAT_Z16_UNORM:
236 return (MAPSURF_16BIT | MT_16BIT_L16);
237 case PIPE_FORMAT_DXT1_RGBA:
238 case PIPE_FORMAT_DXT1_RGB:
239 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
240 case PIPE_FORMAT_DXT3_RGBA:
241 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT2_3);
242 case PIPE_FORMAT_DXT5_RGBA:
243 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT4_5);
244 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
245 case PIPE_FORMAT_Z24X8_UNORM:
246 {
247 if ( view->swizzle_r == PIPE_SWIZZLE_RED &&
248 view->swizzle_g == PIPE_SWIZZLE_RED &&
249 view->swizzle_b == PIPE_SWIZZLE_RED &&
250 view->swizzle_a == PIPE_SWIZZLE_ONE)
251 return (MAPSURF_32BIT | MT_32BIT_xA824);
252 if ( view->swizzle_r == PIPE_SWIZZLE_RED &&
253 view->swizzle_g == PIPE_SWIZZLE_RED &&
254 view->swizzle_b == PIPE_SWIZZLE_RED &&
255 view->swizzle_a == PIPE_SWIZZLE_RED)
256 return (MAPSURF_32BIT | MT_32BIT_xI824);
257 if ( view->swizzle_r == PIPE_SWIZZLE_ZERO &&
258 view->swizzle_g == PIPE_SWIZZLE_ZERO &&
259 view->swizzle_b == PIPE_SWIZZLE_ZERO &&
260 view->swizzle_a == PIPE_SWIZZLE_RED)
261 return (MAPSURF_32BIT | MT_32BIT_xL824);
262 debug_printf("i915: unsupported depth swizzle %d %d %d %d\n",
263 view->swizzle_r,
264 view->swizzle_g,
265 view->swizzle_b,
266 view->swizzle_a);
267 return (MAPSURF_32BIT | MT_32BIT_xL824);
268 }
269 default:
270 debug_printf("i915: translate_texture_format() bad image format %x\n",
271 pipeFormat);
272 assert(0);
273 return 0;
274 }
275 }
276
277 static inline uint32_t
278 ms3_tiling_bits(enum i915_winsys_buffer_tile tiling)
279 {
280 uint32_t tiling_bits = 0;
281
282 switch (tiling) {
283 case I915_TILE_Y:
284 tiling_bits |= MS3_TILE_WALK_Y;
285 case I915_TILE_X:
286 tiling_bits |= MS3_TILED_SURFACE;
287 case I915_TILE_NONE:
288 break;
289 }
290
291 return tiling_bits;
292 }
293
294 static void update_map(struct i915_context *i915,
295 uint unit,
296 const struct i915_texture *tex,
297 const struct i915_sampler_state *sampler,
298 const struct pipe_sampler_view* view,
299 uint state[2])
300 {
301 const struct pipe_resource *pt = &tex->b.b;
302 uint format, pitch;
303 const uint width = pt->width0, height = pt->height0, depth = pt->depth0;
304 const uint num_levels = pt->last_level;
305 unsigned max_lod = num_levels * 4;
306
307 assert(tex);
308 assert(width);
309 assert(height);
310 assert(depth);
311
312 format = translate_texture_format(pt->format, view);
313 i915->current.sampler_srgb[unit] = ( pt->format == PIPE_FORMAT_B8G8R8A8_SRGB ||
314 pt->format == PIPE_FORMAT_L8_SRGB );
315 pitch = tex->stride;
316
317 assert(format);
318 assert(pitch);
319
320 /* MS3 state */
321 state[0] =
322 (((height - 1) << MS3_HEIGHT_SHIFT)
323 | ((width - 1) << MS3_WIDTH_SHIFT)
324 | format
325 | ms3_tiling_bits(tex->tiling));
326
327 /*
328 * XXX When min_filter != mag_filter and there's just one mipmap level,
329 * set max_lod = 1 to make sure i915 chooses between min/mag filtering.
330 */
331
332 /* See note at the top of file */
333 if (max_lod > (sampler->maxlod >> 2))
334 max_lod = sampler->maxlod >> 2;
335
336 /* MS4 state */
337 state[1] =
338 ((((pitch / 4) - 1) << MS4_PITCH_SHIFT)
339 | MS4_CUBE_FACE_ENA_MASK
340 | ((max_lod) << MS4_MAX_LOD_SHIFT)
341 | ((depth - 1) << MS4_VOLUME_DEPTH_SHIFT));
342 }
343
344 static void update_maps(struct i915_context *i915)
345 {
346 uint unit;
347
348 for (unit = 0; unit < i915->num_fragment_sampler_views && unit < i915->num_samplers;
349 unit++) {
350 /* determine unit enable/disable by looking for a bound texture */
351 /* could also examine the fragment program? */
352 if (i915->fragment_sampler_views[unit]) {
353 struct i915_texture *texture = i915_texture(i915->fragment_sampler_views[unit]->texture);
354
355 update_map(i915,
356 unit,
357 texture, /* texture */
358 i915->sampler[unit], /* sampler state */
359 i915->fragment_sampler_views[unit], /* sampler view */
360 i915->current.texbuffer[unit]);
361 }
362 }
363
364 i915->hardware_dirty |= I915_HW_MAP;
365 }
366
367 struct i915_tracked_state i915_hw_sampler_views = {
368 "sampler_views",
369 update_maps,
370 I915_NEW_SAMPLER_VIEW
371 };