Merge branch 'xa_branch'
[mesa.git] / src / gallium / drivers / i915 / i915_state_static.c
1 /**************************************************************************
2 *
3 * Copyright © 2010 Jakob Bornecrantz
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 **************************************************************************/
25
26
27 #include "i915_reg.h"
28 #include "i915_context.h"
29 #include "i915_state.h"
30 #include "i915_resource.h"
31 #include "i915_screen.h"
32
33
34
35 /***********************************************************************
36 * Update framebuffer state
37 */
38 static unsigned translate_format(enum pipe_format format)
39 {
40 switch (format) {
41 case PIPE_FORMAT_B8G8R8A8_UNORM:
42 return COLOR_BUF_ARGB8888;
43 case PIPE_FORMAT_B5G6R5_UNORM:
44 return COLOR_BUF_RGB565;
45 case PIPE_FORMAT_B5G5R5A1_UNORM:
46 return COLOR_BUF_ARGB1555;
47 case PIPE_FORMAT_R8G8B8A8_UNORM:
48 return COLOR_BUF_ARGB8888;
49 case PIPE_FORMAT_B4G4R4A4_UNORM:
50 return COLOR_BUF_ARGB4444;
51 case PIPE_FORMAT_B10G10R10A2_UNORM:
52 return COLOR_BUF_ARGB2101010;
53 case PIPE_FORMAT_L8_UNORM:
54 case PIPE_FORMAT_A8_UNORM:
55 case PIPE_FORMAT_I8_UNORM:
56 return COLOR_BUF_8BIT;
57 default:
58 assert(0);
59 return 0;
60 }
61 }
62
63 static unsigned translate_depth_format(enum pipe_format zformat)
64 {
65 switch (zformat) {
66 case PIPE_FORMAT_Z24X8_UNORM:
67 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
68 return DEPTH_FRMT_24_FIXED_8_OTHER;
69 case PIPE_FORMAT_Z16_UNORM:
70 return DEPTH_FRMT_16_FIXED;
71 default:
72 assert(0);
73 return 0;
74 }
75 }
76
77 static inline uint32_t
78 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling)
79 {
80 uint32_t tiling_bits = 0;
81
82 switch (tiling) {
83 case I915_TILE_Y:
84 tiling_bits |= BUF_3D_TILE_WALK_Y;
85 case I915_TILE_X:
86 tiling_bits |= BUF_3D_TILED_SURFACE;
87 case I915_TILE_NONE:
88 break;
89 }
90
91 return tiling_bits;
92 }
93
94 static void update_framebuffer(struct i915_context *i915)
95 {
96 struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
97 struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
98 unsigned x, y;
99 int layer;
100 uint32_t draw_offset, draw_size;
101
102 if (cbuf_surface) {
103 struct i915_texture *tex = i915_texture(cbuf_surface->texture);
104 assert(tex);
105
106 i915->current.cbuf_bo = tex->buffer;
107 i915->current.cbuf_flags = BUF_3D_ID_COLOR_BACK |
108 BUF_3D_PITCH(tex->stride) | /* pitch in bytes */
109 buf_3d_tiling_bits(tex->tiling);
110
111 layer = cbuf_surface->u.tex.first_layer;
112
113 x = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksx;
114 y = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksy;
115 } else {
116 i915->current.cbuf_bo = NULL;
117 x = y = 0;
118 }
119 i915->static_dirty |= I915_DST_BUF_COLOR;
120
121 /* What happens if no zbuf??
122 */
123 if (depth_surface) {
124 struct i915_texture *tex = i915_texture(depth_surface->texture);
125 unsigned offset = i915_texture_offset(tex, depth_surface->u.tex.level,
126 depth_surface->u.tex.first_layer);
127 assert(tex);
128 assert(offset == 0);
129
130 i915->current.depth_bo = tex->buffer;
131 i915->current.depth_flags = BUF_3D_ID_DEPTH |
132 BUF_3D_PITCH(tex->stride) | /* pitch in bytes */
133 buf_3d_tiling_bits(tex->tiling);
134 } else
135 i915->current.depth_bo = NULL;
136 i915->static_dirty |= I915_DST_BUF_DEPTH;
137
138 /* drawing rect calculations */
139 draw_offset = x | (y << 16);
140 draw_size = (i915->framebuffer.width - 1 + x) |
141 ((i915->framebuffer.height - 1 + y) << 16);
142 if (i915->current.draw_offset != draw_offset) {
143 i915->current.draw_offset = draw_offset;
144 i915_set_flush_dirty(i915, I915_PIPELINE_FLUSH);
145 i915->static_dirty |= I915_DST_RECT;
146 }
147 if (i915->current.draw_size != draw_size) {
148 i915->current.draw_size = draw_size;
149 i915->static_dirty |= I915_DST_RECT;
150 }
151
152 /* we also send a new program to make sure the fixup for RGBA surfaces happens */
153 i915->hardware_dirty |= I915_HW_STATIC | I915_HW_PROGRAM;
154
155 /* flush the cache in case we sample from the old renderbuffers */
156 i915_set_flush_dirty(i915, I915_FLUSH_CACHE);
157 }
158
159 struct i915_tracked_state i915_hw_framebuffer = {
160 "framebuffer",
161 update_framebuffer,
162 I915_NEW_FRAMEBUFFER
163 };
164
165 static void update_dst_buf_vars(struct i915_context *i915)
166 {
167 struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
168 struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
169 uint32_t dst_buf_vars, cformat, zformat;
170 uint32_t early_z = 0;
171
172 if (cbuf_surface)
173 cformat = cbuf_surface->format;
174 else
175 cformat = PIPE_FORMAT_B8G8R8A8_UNORM; /* arbitrary */
176 cformat = translate_format(cformat);
177
178 if (depth_surface) {
179 struct i915_texture *tex = i915_texture(depth_surface->texture);
180 struct i915_screen *is = i915_screen(i915->base.screen);
181
182 zformat = translate_depth_format(depth_surface->format);
183
184 if (is->is_i945 && tex->tiling != I915_TILE_NONE
185 && !i915->fs->info.writes_z)
186 early_z = CLASSIC_EARLY_DEPTH;
187 } else
188 zformat = 0;
189
190 dst_buf_vars = DSTORG_HORT_BIAS(0x8) | /* .5 */
191 DSTORG_VERT_BIAS(0x8) | /* .5 */
192 LOD_PRECLAMP_OGL |
193 TEX_DEFAULT_COLOR_OGL |
194 cformat |
195 zformat |
196 early_z;
197
198 if (i915->current.dst_buf_vars != dst_buf_vars) {
199 if (early_z != (i915->current.dst_buf_vars & CLASSIC_EARLY_DEPTH))
200 i915_set_flush_dirty(i915, I915_PIPELINE_FLUSH);
201
202 i915->current.dst_buf_vars = dst_buf_vars;
203 i915->static_dirty |= I915_DST_VARS;
204 i915->hardware_dirty |= I915_HW_STATIC;
205 }
206 }
207
208 struct i915_tracked_state i915_hw_dst_buf_vars = {
209 "dst buf vars",
210 update_dst_buf_vars,
211 I915_NEW_FRAMEBUFFER | I915_NEW_FS
212 };