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Merge tgsi/exec and tgsi/util directories.
[mesa.git] / src / gallium / drivers / i915simple / i915_fpc_translate.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdarg.h>
30
31 #include "i915_reg.h"
32 #include "i915_context.h"
33 #include "i915_fpc.h"
34
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_string.h"
37 #include "tgsi/tgsi_parse.h"
38 #include "tgsi/tgsi_dump.h"
39
40 #include "draw/draw_vertex.h"
41
42
43 /**
44 * Simple pass-through fragment shader to use when we don't have
45 * a real shader (or it fails to compile for some reason).
46 */
47 static unsigned passthrough[] =
48 {
49 _3DSTATE_PIXEL_SHADER_PROGRAM | ((2*3)-1),
50
51 /* declare input color:
52 */
53 (D0_DCL |
54 (REG_TYPE_T << D0_TYPE_SHIFT) |
55 (T_DIFFUSE << D0_NR_SHIFT) |
56 D0_CHANNEL_ALL),
57 0,
58 0,
59
60 /* move to output color:
61 */
62 (A0_MOV |
63 (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
64 A0_DEST_CHANNEL_ALL |
65 (REG_TYPE_T << A0_SRC0_TYPE_SHIFT) |
66 (T_DIFFUSE << A0_SRC0_NR_SHIFT)),
67 0x01230000, /* .xyzw */
68 0
69 };
70
71
72 /* 1, -1/3!, 1/5!, -1/7! */
73 static const float sin_constants[4] = { 1.0,
74 -1.0f / (3 * 2 * 1),
75 1.0f / (5 * 4 * 3 * 2 * 1),
76 -1.0f / (7 * 6 * 5 * 4 * 3 * 2 * 1)
77 };
78
79 /* 1, -1/2!, 1/4!, -1/6! */
80 static const float cos_constants[4] = { 1.0,
81 -1.0f / (2 * 1),
82 1.0f / (4 * 3 * 2 * 1),
83 -1.0f / (6 * 5 * 4 * 3 * 2 * 1)
84 };
85
86
87
88 /**
89 * component-wise negation of ureg
90 */
91 static INLINE int
92 negate(int reg, int x, int y, int z, int w)
93 {
94 /* Another neat thing about the UREG representation */
95 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
96 ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) |
97 ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) |
98 ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT));
99 }
100
101
102 /**
103 * In the event of a translation failure, we'll generate a simple color
104 * pass-through program.
105 */
106 static void
107 i915_use_passthrough_shader(struct i915_fragment_shader *fs)
108 {
109 fs->program = (uint *) MALLOC(sizeof(passthrough));
110 if (fs->program) {
111 memcpy(fs->program, passthrough, sizeof(passthrough));
112 fs->program_len = Elements(passthrough);
113 }
114 fs->num_constants = 0;
115 }
116
117
118 void
119 i915_program_error(struct i915_fp_compile *p, const char *msg, ...)
120 {
121 va_list args;
122 char buffer[1024];
123
124 debug_printf("i915_program_error: ");
125 va_start( args, msg );
126 util_vsnprintf( buffer, sizeof(buffer), msg, args );
127 va_end( args );
128 debug_printf(buffer);
129 debug_printf("\n");
130
131 p->error = 1;
132 }
133
134
135
136 /**
137 * Construct a ureg for the given source register. Will emit
138 * constants, apply swizzling and negation as needed.
139 */
140 static uint
141 src_vector(struct i915_fp_compile *p,
142 const struct tgsi_full_src_register *source)
143 {
144 uint index = source->SrcRegister.Index;
145 uint src, sem_name, sem_ind;
146
147 switch (source->SrcRegister.File) {
148 case TGSI_FILE_TEMPORARY:
149 if (source->SrcRegister.Index >= I915_MAX_TEMPORARY) {
150 i915_program_error(p, "Exceeded max temporary reg");
151 return 0;
152 }
153 src = UREG(REG_TYPE_R, index);
154 break;
155 case TGSI_FILE_INPUT:
156 /* XXX: Packing COL1, FOGC into a single attribute works for
157 * texenv programs, but will fail for real fragment programs
158 * that use these attributes and expect them to be a full 4
159 * components wide. Could use a texcoord to pass these
160 * attributes if necessary, but that won't work in the general
161 * case.
162 *
163 * We also use a texture coordinate to pass wpos when possible.
164 */
165
166 sem_name = p->shader->info.input_semantic_name[index];
167 sem_ind = p->shader->info.input_semantic_index[index];
168
169 switch (sem_name) {
170 case TGSI_SEMANTIC_POSITION:
171 debug_printf("SKIP SEM POS\n");
172 /*
173 assert(p->wpos_tex != -1);
174 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
175 */
176 break;
177 case TGSI_SEMANTIC_COLOR:
178 if (sem_ind == 0) {
179 src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
180 }
181 else {
182 /* secondary color */
183 assert(sem_ind == 1);
184 src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
185 src = swizzle(src, X, Y, Z, ONE);
186 }
187 break;
188 case TGSI_SEMANTIC_FOG:
189 src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
190 src = swizzle(src, W, W, W, W);
191 break;
192 case TGSI_SEMANTIC_GENERIC:
193 /* usually a texcoord */
194 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind, D0_CHANNEL_ALL);
195 break;
196 default:
197 i915_program_error(p, "Bad source->Index");
198 return 0;
199 }
200 break;
201
202 case TGSI_FILE_IMMEDIATE:
203 assert(index < p->num_immediates);
204 index = p->immediates_map[index];
205 /* fall-through */
206 case TGSI_FILE_CONSTANT:
207 src = UREG(REG_TYPE_CONST, index);
208 break;
209
210 default:
211 i915_program_error(p, "Bad source->File");
212 return 0;
213 }
214
215 if (source->SrcRegister.Extended) {
216 src = swizzle(src,
217 source->SrcRegisterExtSwz.ExtSwizzleX,
218 source->SrcRegisterExtSwz.ExtSwizzleY,
219 source->SrcRegisterExtSwz.ExtSwizzleZ,
220 source->SrcRegisterExtSwz.ExtSwizzleW);
221 }
222 else {
223 src = swizzle(src,
224 source->SrcRegister.SwizzleX,
225 source->SrcRegister.SwizzleY,
226 source->SrcRegister.SwizzleZ,
227 source->SrcRegister.SwizzleW);
228 }
229
230
231 /* There's both negate-all-components and per-component negation.
232 * Try to handle both here.
233 */
234 {
235 int nx = source->SrcRegisterExtSwz.NegateX;
236 int ny = source->SrcRegisterExtSwz.NegateY;
237 int nz = source->SrcRegisterExtSwz.NegateZ;
238 int nw = source->SrcRegisterExtSwz.NegateW;
239 if (source->SrcRegister.Negate) {
240 nx = !nx;
241 ny = !ny;
242 nz = !nz;
243 nw = !nw;
244 }
245 src = negate(src, nx, ny, nz, nw);
246 }
247
248 /* no abs() or post-abs negation */
249 #if 0
250 /* XXX assertions disabled to allow arbfplight.c to run */
251 /* XXX enable these assertions, or fix things */
252 assert(!source->SrcRegisterExtMod.Absolute);
253 assert(!source->SrcRegisterExtMod.Negate);
254 #endif
255 return src;
256 }
257
258
259 /**
260 * Construct a ureg for a destination register.
261 */
262 static uint
263 get_result_vector(struct i915_fp_compile *p,
264 const struct tgsi_full_dst_register *dest)
265 {
266 switch (dest->DstRegister.File) {
267 case TGSI_FILE_OUTPUT:
268 {
269 uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
270 switch (sem_name) {
271 case TGSI_SEMANTIC_POSITION:
272 return UREG(REG_TYPE_OD, 0);
273 case TGSI_SEMANTIC_COLOR:
274 return UREG(REG_TYPE_OC, 0);
275 default:
276 i915_program_error(p, "Bad inst->DstReg.Index/semantics");
277 return 0;
278 }
279 }
280 case TGSI_FILE_TEMPORARY:
281 return UREG(REG_TYPE_R, dest->DstRegister.Index);
282 default:
283 i915_program_error(p, "Bad inst->DstReg.File");
284 return 0;
285 }
286 }
287
288
289 /**
290 * Compute flags for saturation and writemask.
291 */
292 static uint
293 get_result_flags(const struct tgsi_full_instruction *inst)
294 {
295 const uint writeMask
296 = inst->FullDstRegisters[0].DstRegister.WriteMask;
297 uint flags = 0x0;
298
299 if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
300 flags |= A0_DEST_SATURATE;
301
302 if (writeMask & TGSI_WRITEMASK_X)
303 flags |= A0_DEST_CHANNEL_X;
304 if (writeMask & TGSI_WRITEMASK_Y)
305 flags |= A0_DEST_CHANNEL_Y;
306 if (writeMask & TGSI_WRITEMASK_Z)
307 flags |= A0_DEST_CHANNEL_Z;
308 if (writeMask & TGSI_WRITEMASK_W)
309 flags |= A0_DEST_CHANNEL_W;
310
311 return flags;
312 }
313
314
315 /**
316 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
317 */
318 static uint
319 translate_tex_src_target(struct i915_fp_compile *p, uint tex)
320 {
321 switch (tex) {
322 case TGSI_TEXTURE_1D:
323 return D0_SAMPLE_TYPE_2D;
324 case TGSI_TEXTURE_2D:
325 return D0_SAMPLE_TYPE_2D;
326 case TGSI_TEXTURE_RECT:
327 return D0_SAMPLE_TYPE_2D;
328 case TGSI_TEXTURE_3D:
329 return D0_SAMPLE_TYPE_VOLUME;
330 case TGSI_TEXTURE_CUBE:
331 return D0_SAMPLE_TYPE_CUBE;
332 default:
333 i915_program_error(p, "TexSrc type");
334 return 0;
335 }
336 }
337
338
339 /**
340 * Generate texel lookup instruction.
341 */
342 static void
343 emit_tex(struct i915_fp_compile *p,
344 const struct tgsi_full_instruction *inst,
345 uint opcode)
346 {
347 uint texture = inst->InstructionExtTexture.Texture;
348 uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
349 uint tex = translate_tex_src_target( p, texture );
350 uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
351 uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
352
353 i915_emit_texld( p,
354 get_result_vector( p, &inst->FullDstRegisters[0] ),
355 get_result_flags( inst ),
356 sampler,
357 coord,
358 opcode);
359 }
360
361
362 /**
363 * Generate a simple arithmetic instruction
364 * \param opcode the i915 opcode
365 * \param numArgs the number of input/src arguments
366 */
367 static void
368 emit_simple_arith(struct i915_fp_compile *p,
369 const struct tgsi_full_instruction *inst,
370 uint opcode, uint numArgs)
371 {
372 uint arg1, arg2, arg3;
373
374 assert(numArgs <= 3);
375
376 arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
377 arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
378 arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
379
380 i915_emit_arith( p,
381 opcode,
382 get_result_vector( p, &inst->FullDstRegisters[0]),
383 get_result_flags( inst ), 0,
384 arg1,
385 arg2,
386 arg3 );
387 }
388
389
390 /** As above, but swap the first two src regs */
391 static void
392 emit_simple_arith_swap2(struct i915_fp_compile *p,
393 const struct tgsi_full_instruction *inst,
394 uint opcode, uint numArgs)
395 {
396 struct tgsi_full_instruction inst2;
397
398 assert(numArgs == 2);
399
400 /* transpose first two registers */
401 inst2 = *inst;
402 inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
403 inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
404
405 emit_simple_arith(p, &inst2, opcode, numArgs);
406 }
407
408
409 #ifndef M_PI
410 #define M_PI 3.14159265358979323846
411 #endif
412
413 /*
414 * Translate TGSI instruction to i915 instruction.
415 *
416 * Possible concerns:
417 *
418 * SIN, COS -- could use another taylor step?
419 * LIT -- results seem a little different to sw mesa
420 * LOG -- different to mesa on negative numbers, but this is conformant.
421 */
422 static void
423 i915_translate_instruction(struct i915_fp_compile *p,
424 const struct tgsi_full_instruction *inst)
425 {
426 uint writemask;
427 uint src0, src1, src2, flags;
428 uint tmp = 0;
429
430 switch (inst->Instruction.Opcode) {
431 case TGSI_OPCODE_ABS:
432 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
433 i915_emit_arith(p,
434 A0_MAX,
435 get_result_vector(p, &inst->FullDstRegisters[0]),
436 get_result_flags(inst), 0,
437 src0, negate(src0, 1, 1, 1, 1), 0);
438 break;
439
440 case TGSI_OPCODE_ADD:
441 emit_simple_arith(p, inst, A0_ADD, 2);
442 break;
443
444 case TGSI_OPCODE_CMP:
445 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
446 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
447 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
448 i915_emit_arith(p, A0_CMP,
449 get_result_vector(p, &inst->FullDstRegisters[0]),
450 get_result_flags(inst),
451 0, src0, src2, src1); /* NOTE: order of src2, src1 */
452 break;
453
454 case TGSI_OPCODE_COS:
455 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
456 tmp = i915_get_utemp(p);
457
458 i915_emit_arith(p,
459 A0_MUL,
460 tmp, A0_DEST_CHANNEL_X, 0,
461 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
462
463 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
464
465 /* By choosing different taylor constants, could get rid of this mul:
466 */
467 i915_emit_arith(p,
468 A0_MUL,
469 tmp, A0_DEST_CHANNEL_X, 0,
470 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
471
472 /*
473 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
474 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
475 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
476 * result = DP4 t0, cos_constants
477 */
478 i915_emit_arith(p,
479 A0_MUL,
480 tmp, A0_DEST_CHANNEL_XY, 0,
481 swizzle(tmp, X, X, ONE, ONE),
482 swizzle(tmp, X, ONE, ONE, ONE), 0);
483
484 i915_emit_arith(p,
485 A0_MUL,
486 tmp, A0_DEST_CHANNEL_XYZ, 0,
487 swizzle(tmp, X, Y, X, ONE),
488 swizzle(tmp, X, X, ONE, ONE), 0);
489
490 i915_emit_arith(p,
491 A0_MUL,
492 tmp, A0_DEST_CHANNEL_XYZ, 0,
493 swizzle(tmp, X, X, Z, ONE),
494 swizzle(tmp, Z, ONE, ONE, ONE), 0);
495
496 i915_emit_arith(p,
497 A0_DP4,
498 get_result_vector(p, &inst->FullDstRegisters[0]),
499 get_result_flags(inst), 0,
500 swizzle(tmp, ONE, Z, Y, X),
501 i915_emit_const4fv(p, cos_constants), 0);
502 break;
503
504 case TGSI_OPCODE_DP3:
505 emit_simple_arith(p, inst, A0_DP3, 2);
506 break;
507
508 case TGSI_OPCODE_DP4:
509 emit_simple_arith(p, inst, A0_DP4, 2);
510 break;
511
512 case TGSI_OPCODE_DPH:
513 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
514 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
515
516 i915_emit_arith(p,
517 A0_DP4,
518 get_result_vector(p, &inst->FullDstRegisters[0]),
519 get_result_flags(inst), 0,
520 swizzle(src0, X, Y, Z, ONE), src1, 0);
521 break;
522
523 case TGSI_OPCODE_DST:
524 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
525 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
526
527 /* result[0] = 1 * 1;
528 * result[1] = a[1] * b[1];
529 * result[2] = a[2] * 1;
530 * result[3] = 1 * b[3];
531 */
532 i915_emit_arith(p,
533 A0_MUL,
534 get_result_vector(p, &inst->FullDstRegisters[0]),
535 get_result_flags(inst), 0,
536 swizzle(src0, ONE, Y, Z, ONE),
537 swizzle(src1, ONE, Y, ONE, W), 0);
538 break;
539
540 case TGSI_OPCODE_END:
541 /* no-op */
542 break;
543
544 case TGSI_OPCODE_EX2:
545 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
546
547 i915_emit_arith(p,
548 A0_EXP,
549 get_result_vector(p, &inst->FullDstRegisters[0]),
550 get_result_flags(inst), 0,
551 swizzle(src0, X, X, X, X), 0, 0);
552 break;
553
554 case TGSI_OPCODE_FLR:
555 emit_simple_arith(p, inst, A0_FLR, 1);
556 break;
557
558 case TGSI_OPCODE_FRC:
559 emit_simple_arith(p, inst, A0_FRC, 1);
560 break;
561
562 case TGSI_OPCODE_KIL:
563 /* unconditional kill */
564 assert(0); /* not tested yet */
565 #if 0
566 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
567 tmp = i915_get_utemp(p);
568
569 i915_emit_texld(p, tmp, A0_DEST_CHANNEL_ALL, /* use a dummy dest reg */
570 0, src0, T0_TEXKILL);
571 #endif
572 break;
573
574 case TGSI_OPCODE_KILP:
575 /* kill if src[0].x < 0 || src[0].y < 0 ... */
576 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
577 tmp = i915_get_utemp(p);
578
579 i915_emit_texld(p,
580 tmp, /* dest reg: a dummy reg */
581 A0_DEST_CHANNEL_ALL, /* dest writemask */
582 0, /* sampler */
583 src0, /* coord*/
584 T0_TEXKILL); /* opcode */
585 break;
586
587 case TGSI_OPCODE_LG2:
588 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
589
590 i915_emit_arith(p,
591 A0_LOG,
592 get_result_vector(p, &inst->FullDstRegisters[0]),
593 get_result_flags(inst), 0,
594 swizzle(src0, X, X, X, X), 0, 0);
595 break;
596
597 case TGSI_OPCODE_LIT:
598 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
599 tmp = i915_get_utemp(p);
600
601 /* tmp = max( a.xyzw, a.00zw )
602 * XXX: Clamp tmp.w to -128..128
603 * tmp.y = log(tmp.y)
604 * tmp.y = tmp.w * tmp.y
605 * tmp.y = exp(tmp.y)
606 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
607 */
608 i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0,
609 src0, swizzle(src0, ZERO, ZERO, Z, W), 0);
610
611 i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0,
612 swizzle(tmp, Y, Y, Y, Y), 0, 0);
613
614 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0,
615 swizzle(tmp, ZERO, Y, ZERO, ZERO),
616 swizzle(tmp, ZERO, W, ZERO, ZERO), 0);
617
618 i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0,
619 swizzle(tmp, Y, Y, Y, Y), 0, 0);
620
621 i915_emit_arith(p, A0_CMP,
622 get_result_vector(p, &inst->FullDstRegisters[0]),
623 get_result_flags(inst), 0,
624 negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
625 swizzle(tmp, ONE, X, ZERO, ONE),
626 swizzle(tmp, ONE, X, Y, ONE));
627
628 break;
629
630 case TGSI_OPCODE_LRP:
631 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
632 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
633 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
634 flags = get_result_flags(inst);
635 tmp = i915_get_utemp(p);
636
637 /* b*a + c*(1-a)
638 *
639 * b*a + c - ca
640 *
641 * tmp = b*a + c,
642 * result = (-c)*a + tmp
643 */
644 i915_emit_arith(p, A0_MAD, tmp,
645 flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
646
647 i915_emit_arith(p, A0_MAD,
648 get_result_vector(p, &inst->FullDstRegisters[0]),
649 flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
650 break;
651
652 case TGSI_OPCODE_MAD:
653 emit_simple_arith(p, inst, A0_MAD, 3);
654 break;
655
656 case TGSI_OPCODE_MAX:
657 emit_simple_arith(p, inst, A0_MAX, 2);
658 break;
659
660 case TGSI_OPCODE_MIN:
661 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
662 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
663 tmp = i915_get_utemp(p);
664 flags = get_result_flags(inst);
665
666 i915_emit_arith(p,
667 A0_MAX,
668 tmp, flags & A0_DEST_CHANNEL_ALL, 0,
669 negate(src0, 1, 1, 1, 1),
670 negate(src1, 1, 1, 1, 1), 0);
671
672 i915_emit_arith(p,
673 A0_MOV,
674 get_result_vector(p, &inst->FullDstRegisters[0]),
675 flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
676 break;
677
678 case TGSI_OPCODE_MOV:
679 case TGSI_OPCODE_SWZ:
680 emit_simple_arith(p, inst, A0_MOV, 1);
681 break;
682
683 case TGSI_OPCODE_MUL:
684 emit_simple_arith(p, inst, A0_MUL, 2);
685 break;
686
687 case TGSI_OPCODE_POW:
688 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
689 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
690 tmp = i915_get_utemp(p);
691 flags = get_result_flags(inst);
692
693 /* XXX: masking on intermediate values, here and elsewhere.
694 */
695 i915_emit_arith(p,
696 A0_LOG,
697 tmp, A0_DEST_CHANNEL_X, 0,
698 swizzle(src0, X, X, X, X), 0, 0);
699
700 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0);
701
702 i915_emit_arith(p,
703 A0_EXP,
704 get_result_vector(p, &inst->FullDstRegisters[0]),
705 flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
706 break;
707
708 case TGSI_OPCODE_RET:
709 /* XXX: no-op? */
710 break;
711
712 case TGSI_OPCODE_RCP:
713 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
714
715 i915_emit_arith(p,
716 A0_RCP,
717 get_result_vector(p, &inst->FullDstRegisters[0]),
718 get_result_flags(inst), 0,
719 swizzle(src0, X, X, X, X), 0, 0);
720 break;
721
722 case TGSI_OPCODE_RSQ:
723 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
724
725 i915_emit_arith(p,
726 A0_RSQ,
727 get_result_vector(p, &inst->FullDstRegisters[0]),
728 get_result_flags(inst), 0,
729 swizzle(src0, X, X, X, X), 0, 0);
730 break;
731
732 case TGSI_OPCODE_SCS:
733 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
734 tmp = i915_get_utemp(p);
735
736 /*
737 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
738 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
739 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
740 * scs.x = DP4 t1, sin_constants
741 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
742 * scs.y = DP4 t1, cos_constants
743 */
744 i915_emit_arith(p,
745 A0_MUL,
746 tmp, A0_DEST_CHANNEL_XY, 0,
747 swizzle(src0, X, X, ONE, ONE),
748 swizzle(src0, X, ONE, ONE, ONE), 0);
749
750 i915_emit_arith(p,
751 A0_MUL,
752 tmp, A0_DEST_CHANNEL_ALL, 0,
753 swizzle(tmp, X, Y, X, Y),
754 swizzle(tmp, X, X, ONE, ONE), 0);
755
756 writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
757
758 if (writemask & TGSI_WRITEMASK_Y) {
759 uint tmp1;
760
761 if (writemask & TGSI_WRITEMASK_X)
762 tmp1 = i915_get_utemp(p);
763 else
764 tmp1 = tmp;
765
766 i915_emit_arith(p,
767 A0_MUL,
768 tmp1, A0_DEST_CHANNEL_ALL, 0,
769 swizzle(tmp, X, Y, Y, W),
770 swizzle(tmp, X, Z, ONE, ONE), 0);
771
772 i915_emit_arith(p,
773 A0_DP4,
774 get_result_vector(p, &inst->FullDstRegisters[0]),
775 A0_DEST_CHANNEL_Y, 0,
776 swizzle(tmp1, W, Z, Y, X),
777 i915_emit_const4fv(p, sin_constants), 0);
778 }
779
780 if (writemask & TGSI_WRITEMASK_X) {
781 i915_emit_arith(p,
782 A0_MUL,
783 tmp, A0_DEST_CHANNEL_XYZ, 0,
784 swizzle(tmp, X, X, Z, ONE),
785 swizzle(tmp, Z, ONE, ONE, ONE), 0);
786
787 i915_emit_arith(p,
788 A0_DP4,
789 get_result_vector(p, &inst->FullDstRegisters[0]),
790 A0_DEST_CHANNEL_X, 0,
791 swizzle(tmp, ONE, Z, Y, X),
792 i915_emit_const4fv(p, cos_constants), 0);
793 }
794 break;
795
796 case TGSI_OPCODE_SGE:
797 emit_simple_arith(p, inst, A0_SGE, 2);
798 break;
799
800 case TGSI_OPCODE_SLE:
801 /* like SGE, but swap reg0, reg1 */
802 emit_simple_arith_swap2(p, inst, A0_SGE, 2);
803 break;
804
805 case TGSI_OPCODE_SIN:
806 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
807 tmp = i915_get_utemp(p);
808
809 i915_emit_arith(p,
810 A0_MUL,
811 tmp, A0_DEST_CHANNEL_X, 0,
812 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
813
814 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
815
816 /* By choosing different taylor constants, could get rid of this mul:
817 */
818 i915_emit_arith(p,
819 A0_MUL,
820 tmp, A0_DEST_CHANNEL_X, 0,
821 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
822
823 /*
824 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
825 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
826 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
827 * result = DP4 t1.wzyx, sin_constants
828 */
829 i915_emit_arith(p,
830 A0_MUL,
831 tmp, A0_DEST_CHANNEL_XY, 0,
832 swizzle(tmp, X, X, ONE, ONE),
833 swizzle(tmp, X, ONE, ONE, ONE), 0);
834
835 i915_emit_arith(p,
836 A0_MUL,
837 tmp, A0_DEST_CHANNEL_ALL, 0,
838 swizzle(tmp, X, Y, X, Y),
839 swizzle(tmp, X, X, ONE, ONE), 0);
840
841 i915_emit_arith(p,
842 A0_MUL,
843 tmp, A0_DEST_CHANNEL_ALL, 0,
844 swizzle(tmp, X, Y, Y, W),
845 swizzle(tmp, X, Z, ONE, ONE), 0);
846
847 i915_emit_arith(p,
848 A0_DP4,
849 get_result_vector(p, &inst->FullDstRegisters[0]),
850 get_result_flags(inst), 0,
851 swizzle(tmp, W, Z, Y, X),
852 i915_emit_const4fv(p, sin_constants), 0);
853 break;
854
855 case TGSI_OPCODE_SLT:
856 emit_simple_arith(p, inst, A0_SLT, 2);
857 break;
858
859 case TGSI_OPCODE_SGT:
860 /* like SLT, but swap reg0, reg1 */
861 emit_simple_arith_swap2(p, inst, A0_SLT, 2);
862 break;
863
864 case TGSI_OPCODE_SUB:
865 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
866 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
867
868 i915_emit_arith(p,
869 A0_ADD,
870 get_result_vector(p, &inst->FullDstRegisters[0]),
871 get_result_flags(inst), 0,
872 src0, negate(src1, 1, 1, 1, 1), 0);
873 break;
874
875 case TGSI_OPCODE_TEX:
876 emit_tex(p, inst, T0_TEXLD);
877 break;
878
879 case TGSI_OPCODE_TXB:
880 emit_tex(p, inst, T0_TEXLDB);
881 break;
882
883 case TGSI_OPCODE_TXP:
884 emit_tex(p, inst, T0_TEXLDP);
885 break;
886
887 case TGSI_OPCODE_XPD:
888 /* Cross product:
889 * result.x = src0.y * src1.z - src0.z * src1.y;
890 * result.y = src0.z * src1.x - src0.x * src1.z;
891 * result.z = src0.x * src1.y - src0.y * src1.x;
892 * result.w = undef;
893 */
894 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
895 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
896 tmp = i915_get_utemp(p);
897
898 i915_emit_arith(p,
899 A0_MUL,
900 tmp, A0_DEST_CHANNEL_ALL, 0,
901 swizzle(src0, Z, X, Y, ONE),
902 swizzle(src1, Y, Z, X, ONE), 0);
903
904 i915_emit_arith(p,
905 A0_MAD,
906 get_result_vector(p, &inst->FullDstRegisters[0]),
907 get_result_flags(inst), 0,
908 swizzle(src0, Y, Z, X, ONE),
909 swizzle(src1, Z, X, Y, ONE),
910 negate(tmp, 1, 1, 1, 0));
911 break;
912
913 default:
914 i915_program_error(p, "bad opcode %d", inst->Instruction.Opcode);
915 p->error = 1;
916 return;
917 }
918
919 i915_release_utemps(p);
920 }
921
922
923 /**
924 * Translate TGSI fragment shader into i915 hardware instructions.
925 * \param p the translation state
926 * \param tokens the TGSI token array
927 */
928 static void
929 i915_translate_instructions(struct i915_fp_compile *p,
930 const struct tgsi_token *tokens)
931 {
932 struct i915_fragment_shader *ifs = p->shader;
933 struct tgsi_parse_context parse;
934
935 tgsi_parse_init( &parse, tokens );
936
937 while( !tgsi_parse_end_of_tokens( &parse ) ) {
938
939 tgsi_parse_token( &parse );
940
941 switch( parse.FullToken.Token.Type ) {
942 case TGSI_TOKEN_TYPE_DECLARATION:
943 if (parse.FullToken.FullDeclaration.Declaration.File
944 == TGSI_FILE_CONSTANT) {
945 uint i;
946 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
947 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
948 i++) {
949 assert(ifs->constant_flags[i] == 0x0);
950 ifs->constant_flags[i] = I915_CONSTFLAG_USER;
951 ifs->num_constants = MAX2(ifs->num_constants, i + 1);
952 }
953 }
954 else if (parse.FullToken.FullDeclaration.Declaration.File
955 == TGSI_FILE_TEMPORARY) {
956 uint i;
957 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
958 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
959 i++) {
960 assert(i < I915_MAX_TEMPORARY);
961 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
962 p->temp_flag |= (1 << i); /* mark temp as used */
963 }
964 }
965 break;
966
967 case TGSI_TOKEN_TYPE_IMMEDIATE:
968 {
969 const struct tgsi_full_immediate *imm
970 = &parse.FullToken.FullImmediate;
971 const uint pos = p->num_immediates++;
972 uint j;
973 for (j = 0; j < imm->Immediate.Size; j++) {
974 p->immediates[pos][j] = imm->u.ImmediateFloat32[j].Float;
975 }
976 }
977 break;
978
979 case TGSI_TOKEN_TYPE_INSTRUCTION:
980 if (p->first_instruction) {
981 /* resolve location of immediates */
982 uint i, j;
983 for (i = 0; i < p->num_immediates; i++) {
984 /* find constant slot for this immediate */
985 for (j = 0; j < I915_MAX_CONSTANT; j++) {
986 if (ifs->constant_flags[j] == 0x0) {
987 memcpy(ifs->constants[j],
988 p->immediates[i],
989 4 * sizeof(float));
990 /*printf("immediate %d maps to const %d\n", i, j);*/
991 ifs->constant_flags[j] = 0xf; /* all four comps used */
992 p->immediates_map[i] = j;
993 ifs->num_constants = MAX2(ifs->num_constants, j + 1);
994 break;
995 }
996 }
997 }
998
999 p->first_instruction = FALSE;
1000 }
1001
1002 i915_translate_instruction(p, &parse.FullToken.FullInstruction);
1003 break;
1004
1005 default:
1006 assert( 0 );
1007 }
1008
1009 } /* while */
1010
1011 tgsi_parse_free (&parse);
1012 }
1013
1014
1015 static struct i915_fp_compile *
1016 i915_init_compile(struct i915_context *i915,
1017 struct i915_fragment_shader *ifs)
1018 {
1019 struct i915_fp_compile *p = CALLOC_STRUCT(i915_fp_compile);
1020
1021 p->shader = ifs;
1022
1023 /* Put new constants at end of const buffer, growing downward.
1024 * The problem is we don't know how many user-defined constants might
1025 * be specified with pipe->set_constant_buffer().
1026 * Should pre-scan the user's program to determine the highest-numbered
1027 * constant referenced.
1028 */
1029 ifs->num_constants = 0;
1030 memset(ifs->constant_flags, 0, sizeof(ifs->constant_flags));
1031
1032 p->first_instruction = TRUE;
1033
1034 p->nr_tex_indirect = 1; /* correct? */
1035 p->nr_tex_insn = 0;
1036 p->nr_alu_insn = 0;
1037 p->nr_decl_insn = 0;
1038
1039 p->csr = p->program;
1040 p->decl = p->declarations;
1041 p->decl_s = 0;
1042 p->decl_t = 0;
1043 p->temp_flag = ~0x0 << I915_MAX_TEMPORARY;
1044 p->utemp_flag = ~0x7;
1045
1046 p->wpos_tex = -1;
1047
1048 /* initialize the first program word */
1049 *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM;
1050
1051 return p;
1052 }
1053
1054
1055 /* Copy compile results to the fragment program struct and destroy the
1056 * compilation context.
1057 */
1058 static void
1059 i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p)
1060 {
1061 struct i915_fragment_shader *ifs = p->shader;
1062 unsigned long program_size = (unsigned long) (p->csr - p->program);
1063 unsigned long decl_size = (unsigned long) (p->decl - p->declarations);
1064
1065 if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
1066 i915_program_error(p, "Exceeded max nr indirect texture lookups");
1067
1068 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
1069 i915_program_error(p, "Exceeded max TEX instructions");
1070
1071 if (p->nr_alu_insn > I915_MAX_ALU_INSN)
1072 i915_program_error(p, "Exceeded max ALU instructions");
1073
1074 if (p->nr_decl_insn > I915_MAX_DECL_INSN)
1075 i915_program_error(p, "Exceeded max DECL instructions");
1076
1077 if (p->error) {
1078 p->NumNativeInstructions = 0;
1079 p->NumNativeAluInstructions = 0;
1080 p->NumNativeTexInstructions = 0;
1081 p->NumNativeTexIndirections = 0;
1082
1083 i915_use_passthrough_shader(ifs);
1084 }
1085 else {
1086 p->NumNativeInstructions
1087 = p->nr_alu_insn + p->nr_tex_insn + p->nr_decl_insn;
1088 p->NumNativeAluInstructions = p->nr_alu_insn;
1089 p->NumNativeTexInstructions = p->nr_tex_insn;
1090 p->NumNativeTexIndirections = p->nr_tex_indirect;
1091
1092 /* patch in the program length */
1093 p->declarations[0] |= program_size + decl_size - 2;
1094
1095 /* Copy compilation results to fragment program struct:
1096 */
1097 assert(!ifs->program);
1098 ifs->program
1099 = (uint *) MALLOC((program_size + decl_size) * sizeof(uint));
1100 if (ifs->program) {
1101 ifs->program_len = program_size + decl_size;
1102
1103 memcpy(ifs->program,
1104 p->declarations,
1105 decl_size * sizeof(uint));
1106
1107 memcpy(ifs->program + decl_size,
1108 p->program,
1109 program_size * sizeof(uint));
1110 }
1111 }
1112
1113 /* Release the compilation struct:
1114 */
1115 FREE(p);
1116 }
1117
1118
1119 /**
1120 * Find an unused texture coordinate slot to use for fragment WPOS.
1121 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1122 */
1123 static void
1124 i915_find_wpos_space(struct i915_fp_compile *p)
1125 {
1126 #if 0
1127 const uint inputs
1128 = p->shader->inputs_read | (1 << TGSI_ATTRIB_POS); /*XXX hack*/
1129 uint i;
1130
1131 p->wpos_tex = -1;
1132
1133 if (inputs & (1 << TGSI_ATTRIB_POS)) {
1134 for (i = 0; i < I915_TEX_UNITS; i++) {
1135 if ((inputs & (1 << (TGSI_ATTRIB_TEX0 + i))) == 0) {
1136 p->wpos_tex = i;
1137 return;
1138 }
1139 }
1140
1141 i915_program_error(p, "No free texcoord for wpos value");
1142 }
1143 #else
1144 if (p->shader->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1145 /* frag shader using the fragment position input */
1146 #if 0
1147 assert(0);
1148 #endif
1149 }
1150 #endif
1151 }
1152
1153
1154
1155
1156 /**
1157 * Rather than trying to intercept and jiggle depth writes during
1158 * emit, just move the value into its correct position at the end of
1159 * the program:
1160 */
1161 static void
1162 i915_fixup_depth_write(struct i915_fp_compile *p)
1163 {
1164 /* XXX assuming pos/depth is always in output[0] */
1165 if (p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1166 const uint depth = UREG(REG_TYPE_OD, 0);
1167
1168 i915_emit_arith(p,
1169 A0_MOV, /* opcode */
1170 depth, /* dest reg */
1171 A0_DEST_CHANNEL_W, /* write mask */
1172 0, /* saturate? */
1173 swizzle(depth, X, Y, Z, Z), /* src0 */
1174 0, 0 /* src1, src2 */);
1175 }
1176 }
1177
1178
1179 void
1180 i915_translate_fragment_program( struct i915_context *i915,
1181 struct i915_fragment_shader *fs)
1182 {
1183 struct i915_fp_compile *p = i915_init_compile(i915, fs);
1184 const struct tgsi_token *tokens = fs->state.tokens;
1185
1186 i915_find_wpos_space(p);
1187
1188 #if 0
1189 tgsi_dump(tokens, 0);
1190 #endif
1191
1192 i915_translate_instructions(p, tokens);
1193 i915_fixup_depth_write(p);
1194
1195 i915_fini_compile(i915, p);
1196 }