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gallium/i915: Use tgsi_scan_shader() to collect shader info
[mesa.git] / src / gallium / drivers / i915simple / i915_fpc_translate.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdarg.h>
30
31 #include "i915_reg.h"
32 #include "i915_context.h"
33 #include "i915_fpc.h"
34
35 #include "pipe/p_shader_tokens.h"
36 #include "tgsi/util/tgsi_parse.h"
37 #include "tgsi/util/tgsi_dump.h"
38
39 #include "draw/draw_vertex.h"
40
41
42 /**
43 * Simple pass-through fragment shader to use when we don't have
44 * a real shader (or it fails to compile for some reason).
45 */
46 static unsigned passthrough[] =
47 {
48 _3DSTATE_PIXEL_SHADER_PROGRAM | ((2*3)-1),
49
50 /* declare input color:
51 */
52 (D0_DCL |
53 (REG_TYPE_T << D0_TYPE_SHIFT) |
54 (T_DIFFUSE << D0_NR_SHIFT) |
55 D0_CHANNEL_ALL),
56 0,
57 0,
58
59 /* move to output color:
60 */
61 (A0_MOV |
62 (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
63 A0_DEST_CHANNEL_ALL |
64 (REG_TYPE_T << A0_SRC0_TYPE_SHIFT) |
65 (T_DIFFUSE << A0_SRC0_NR_SHIFT)),
66 0x01230000, /* .xyzw */
67 0
68 };
69
70
71 /* 1, -1/3!, 1/5!, -1/7! */
72 static const float sin_constants[4] = { 1.0,
73 -1.0f / (3 * 2 * 1),
74 1.0f / (5 * 4 * 3 * 2 * 1),
75 -1.0f / (7 * 6 * 5 * 4 * 3 * 2 * 1)
76 };
77
78 /* 1, -1/2!, 1/4!, -1/6! */
79 static const float cos_constants[4] = { 1.0,
80 -1.0f / (2 * 1),
81 1.0f / (4 * 3 * 2 * 1),
82 -1.0f / (6 * 5 * 4 * 3 * 2 * 1)
83 };
84
85
86
87 /**
88 * component-wise negation of ureg
89 */
90 static INLINE int
91 negate(int reg, int x, int y, int z, int w)
92 {
93 /* Another neat thing about the UREG representation */
94 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
95 ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) |
96 ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) |
97 ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT));
98 }
99
100
101 /**
102 * In the event of a translation failure, we'll generate a simple color
103 * pass-through program.
104 */
105 static void
106 i915_use_passthrough_shader(struct i915_fragment_shader *fs)
107 {
108 fs->program = (uint *) MALLOC(sizeof(passthrough));
109 if (fs->program) {
110 memcpy(fs->program, passthrough, sizeof(passthrough));
111 fs->program_len = Elements(passthrough);
112 }
113 fs->num_constants = 0;
114 }
115
116
117 void
118 i915_program_error(struct i915_fp_compile *p, const char *msg, ...)
119 {
120 va_list args;
121 char buffer[1024];
122
123 debug_printf("i915_program_error: ");
124 va_start( args, msg );
125 vsprintf( buffer, msg, args );
126 va_end( args );
127 debug_printf(buffer);
128 debug_printf("\n");
129
130 p->error = 1;
131 }
132
133
134
135 /**
136 * Construct a ureg for the given source register. Will emit
137 * constants, apply swizzling and negation as needed.
138 */
139 static uint
140 src_vector(struct i915_fp_compile *p,
141 const struct tgsi_full_src_register *source)
142 {
143 uint index = source->SrcRegister.Index;
144 uint src, sem_name, sem_ind;
145
146 switch (source->SrcRegister.File) {
147 case TGSI_FILE_TEMPORARY:
148 if (source->SrcRegister.Index >= I915_MAX_TEMPORARY) {
149 i915_program_error(p, "Exceeded max temporary reg");
150 return 0;
151 }
152 src = UREG(REG_TYPE_R, index);
153 break;
154 case TGSI_FILE_INPUT:
155 /* XXX: Packing COL1, FOGC into a single attribute works for
156 * texenv programs, but will fail for real fragment programs
157 * that use these attributes and expect them to be a full 4
158 * components wide. Could use a texcoord to pass these
159 * attributes if necessary, but that won't work in the general
160 * case.
161 *
162 * We also use a texture coordinate to pass wpos when possible.
163 */
164
165 sem_name = p->shader->info.input_semantic_name[index];
166 sem_ind = p->shader->info.input_semantic_index[index];
167
168 switch (sem_name) {
169 case TGSI_SEMANTIC_POSITION:
170 debug_printf("SKIP SEM POS\n");
171 /*
172 assert(p->wpos_tex != -1);
173 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
174 */
175 break;
176 case TGSI_SEMANTIC_COLOR:
177 if (sem_ind == 0) {
178 src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
179 }
180 else {
181 /* secondary color */
182 assert(sem_ind == 1);
183 src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
184 src = swizzle(src, X, Y, Z, ONE);
185 }
186 break;
187 case TGSI_SEMANTIC_FOG:
188 src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
189 src = swizzle(src, W, W, W, W);
190 break;
191 case TGSI_SEMANTIC_GENERIC:
192 /* usually a texcoord */
193 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind, D0_CHANNEL_ALL);
194 break;
195 default:
196 i915_program_error(p, "Bad source->Index");
197 return 0;
198 }
199 break;
200
201 case TGSI_FILE_IMMEDIATE:
202 assert(index < p->num_immediates);
203 index = p->immediates_map[index];
204 /* fall-through */
205 case TGSI_FILE_CONSTANT:
206 src = UREG(REG_TYPE_CONST, index);
207 break;
208
209 default:
210 i915_program_error(p, "Bad source->File");
211 return 0;
212 }
213
214 if (source->SrcRegister.Extended) {
215 src = swizzle(src,
216 source->SrcRegisterExtSwz.ExtSwizzleX,
217 source->SrcRegisterExtSwz.ExtSwizzleY,
218 source->SrcRegisterExtSwz.ExtSwizzleZ,
219 source->SrcRegisterExtSwz.ExtSwizzleW);
220 }
221 else {
222 src = swizzle(src,
223 source->SrcRegister.SwizzleX,
224 source->SrcRegister.SwizzleY,
225 source->SrcRegister.SwizzleZ,
226 source->SrcRegister.SwizzleW);
227 }
228
229
230 /* There's both negate-all-components and per-component negation.
231 * Try to handle both here.
232 */
233 {
234 int nx = source->SrcRegisterExtSwz.NegateX;
235 int ny = source->SrcRegisterExtSwz.NegateY;
236 int nz = source->SrcRegisterExtSwz.NegateZ;
237 int nw = source->SrcRegisterExtSwz.NegateW;
238 if (source->SrcRegister.Negate) {
239 nx = !nx;
240 ny = !ny;
241 nz = !nz;
242 nw = !nw;
243 }
244 src = negate(src, nx, ny, nz, nw);
245 }
246
247 /* no abs() or post-abs negation */
248 #if 0
249 /* XXX assertions disabled to allow arbfplight.c to run */
250 /* XXX enable these assertions, or fix things */
251 assert(!source->SrcRegisterExtMod.Absolute);
252 assert(!source->SrcRegisterExtMod.Negate);
253 #endif
254 return src;
255 }
256
257
258 /**
259 * Construct a ureg for a destination register.
260 */
261 static uint
262 get_result_vector(struct i915_fp_compile *p,
263 const struct tgsi_full_dst_register *dest)
264 {
265 switch (dest->DstRegister.File) {
266 case TGSI_FILE_OUTPUT:
267 {
268 uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
269 switch (sem_name) {
270 case TGSI_SEMANTIC_POSITION:
271 return UREG(REG_TYPE_OD, 0);
272 case TGSI_SEMANTIC_COLOR:
273 return UREG(REG_TYPE_OC, 0);
274 default:
275 i915_program_error(p, "Bad inst->DstReg.Index/semantics");
276 return 0;
277 }
278 }
279 case TGSI_FILE_TEMPORARY:
280 return UREG(REG_TYPE_R, dest->DstRegister.Index);
281 default:
282 i915_program_error(p, "Bad inst->DstReg.File");
283 return 0;
284 }
285 }
286
287
288 /**
289 * Compute flags for saturation and writemask.
290 */
291 static uint
292 get_result_flags(const struct tgsi_full_instruction *inst)
293 {
294 const uint writeMask
295 = inst->FullDstRegisters[0].DstRegister.WriteMask;
296 uint flags = 0x0;
297
298 if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
299 flags |= A0_DEST_SATURATE;
300
301 if (writeMask & TGSI_WRITEMASK_X)
302 flags |= A0_DEST_CHANNEL_X;
303 if (writeMask & TGSI_WRITEMASK_Y)
304 flags |= A0_DEST_CHANNEL_Y;
305 if (writeMask & TGSI_WRITEMASK_Z)
306 flags |= A0_DEST_CHANNEL_Z;
307 if (writeMask & TGSI_WRITEMASK_W)
308 flags |= A0_DEST_CHANNEL_W;
309
310 return flags;
311 }
312
313
314 /**
315 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
316 */
317 static uint
318 translate_tex_src_target(struct i915_fp_compile *p, uint tex)
319 {
320 switch (tex) {
321 case TGSI_TEXTURE_1D:
322 return D0_SAMPLE_TYPE_2D;
323 case TGSI_TEXTURE_2D:
324 return D0_SAMPLE_TYPE_2D;
325 case TGSI_TEXTURE_RECT:
326 return D0_SAMPLE_TYPE_2D;
327 case TGSI_TEXTURE_3D:
328 return D0_SAMPLE_TYPE_VOLUME;
329 case TGSI_TEXTURE_CUBE:
330 return D0_SAMPLE_TYPE_CUBE;
331 default:
332 i915_program_error(p, "TexSrc type");
333 return 0;
334 }
335 }
336
337
338 /**
339 * Generate texel lookup instruction.
340 */
341 static void
342 emit_tex(struct i915_fp_compile *p,
343 const struct tgsi_full_instruction *inst,
344 uint opcode)
345 {
346 uint texture = inst->InstructionExtTexture.Texture;
347 uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
348 uint tex = translate_tex_src_target( p, texture );
349 uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
350 uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
351
352 i915_emit_texld( p,
353 get_result_vector( p, &inst->FullDstRegisters[0] ),
354 get_result_flags( inst ),
355 sampler,
356 coord,
357 opcode);
358 }
359
360
361 /**
362 * Generate a simple arithmetic instruction
363 * \param opcode the i915 opcode
364 * \param numArgs the number of input/src arguments
365 */
366 static void
367 emit_simple_arith(struct i915_fp_compile *p,
368 const struct tgsi_full_instruction *inst,
369 uint opcode, uint numArgs)
370 {
371 uint arg1, arg2, arg3;
372
373 assert(numArgs <= 3);
374
375 arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
376 arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
377 arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
378
379 i915_emit_arith( p,
380 opcode,
381 get_result_vector( p, &inst->FullDstRegisters[0]),
382 get_result_flags( inst ), 0,
383 arg1,
384 arg2,
385 arg3 );
386 }
387
388
389 /** As above, but swap the first two src regs */
390 static void
391 emit_simple_arith_swap2(struct i915_fp_compile *p,
392 const struct tgsi_full_instruction *inst,
393 uint opcode, uint numArgs)
394 {
395 struct tgsi_full_instruction inst2;
396
397 assert(numArgs == 2);
398
399 /* transpose first two registers */
400 inst2 = *inst;
401 inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
402 inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
403
404 emit_simple_arith(p, &inst2, opcode, numArgs);
405 }
406
407
408 #ifndef M_PI
409 #define M_PI 3.14159265358979323846
410 #endif
411
412 /*
413 * Translate TGSI instruction to i915 instruction.
414 *
415 * Possible concerns:
416 *
417 * SIN, COS -- could use another taylor step?
418 * LIT -- results seem a little different to sw mesa
419 * LOG -- different to mesa on negative numbers, but this is conformant.
420 */
421 static void
422 i915_translate_instruction(struct i915_fp_compile *p,
423 const struct tgsi_full_instruction *inst)
424 {
425 uint writemask;
426 uint src0, src1, src2, flags;
427 uint tmp = 0;
428
429 switch (inst->Instruction.Opcode) {
430 case TGSI_OPCODE_ABS:
431 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
432 i915_emit_arith(p,
433 A0_MAX,
434 get_result_vector(p, &inst->FullDstRegisters[0]),
435 get_result_flags(inst), 0,
436 src0, negate(src0, 1, 1, 1, 1), 0);
437 break;
438
439 case TGSI_OPCODE_ADD:
440 emit_simple_arith(p, inst, A0_ADD, 2);
441 break;
442
443 case TGSI_OPCODE_CMP:
444 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
445 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
446 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
447 i915_emit_arith(p, A0_CMP,
448 get_result_vector(p, &inst->FullDstRegisters[0]),
449 get_result_flags(inst),
450 0, src0, src2, src1); /* NOTE: order of src2, src1 */
451 break;
452
453 case TGSI_OPCODE_COS:
454 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
455 tmp = i915_get_utemp(p);
456
457 i915_emit_arith(p,
458 A0_MUL,
459 tmp, A0_DEST_CHANNEL_X, 0,
460 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
461
462 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
463
464 /* By choosing different taylor constants, could get rid of this mul:
465 */
466 i915_emit_arith(p,
467 A0_MUL,
468 tmp, A0_DEST_CHANNEL_X, 0,
469 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
470
471 /*
472 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
473 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
474 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
475 * result = DP4 t0, cos_constants
476 */
477 i915_emit_arith(p,
478 A0_MUL,
479 tmp, A0_DEST_CHANNEL_XY, 0,
480 swizzle(tmp, X, X, ONE, ONE),
481 swizzle(tmp, X, ONE, ONE, ONE), 0);
482
483 i915_emit_arith(p,
484 A0_MUL,
485 tmp, A0_DEST_CHANNEL_XYZ, 0,
486 swizzle(tmp, X, Y, X, ONE),
487 swizzle(tmp, X, X, ONE, ONE), 0);
488
489 i915_emit_arith(p,
490 A0_MUL,
491 tmp, A0_DEST_CHANNEL_XYZ, 0,
492 swizzle(tmp, X, X, Z, ONE),
493 swizzle(tmp, Z, ONE, ONE, ONE), 0);
494
495 i915_emit_arith(p,
496 A0_DP4,
497 get_result_vector(p, &inst->FullDstRegisters[0]),
498 get_result_flags(inst), 0,
499 swizzle(tmp, ONE, Z, Y, X),
500 i915_emit_const4fv(p, cos_constants), 0);
501 break;
502
503 case TGSI_OPCODE_DP3:
504 emit_simple_arith(p, inst, A0_DP3, 2);
505 break;
506
507 case TGSI_OPCODE_DP4:
508 emit_simple_arith(p, inst, A0_DP4, 2);
509 break;
510
511 case TGSI_OPCODE_DPH:
512 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
513 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
514
515 i915_emit_arith(p,
516 A0_DP4,
517 get_result_vector(p, &inst->FullDstRegisters[0]),
518 get_result_flags(inst), 0,
519 swizzle(src0, X, Y, Z, ONE), src1, 0);
520 break;
521
522 case TGSI_OPCODE_DST:
523 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
524 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
525
526 /* result[0] = 1 * 1;
527 * result[1] = a[1] * b[1];
528 * result[2] = a[2] * 1;
529 * result[3] = 1 * b[3];
530 */
531 i915_emit_arith(p,
532 A0_MUL,
533 get_result_vector(p, &inst->FullDstRegisters[0]),
534 get_result_flags(inst), 0,
535 swizzle(src0, ONE, Y, Z, ONE),
536 swizzle(src1, ONE, Y, ONE, W), 0);
537 break;
538
539 case TGSI_OPCODE_END:
540 /* no-op */
541 break;
542
543 case TGSI_OPCODE_EX2:
544 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
545
546 i915_emit_arith(p,
547 A0_EXP,
548 get_result_vector(p, &inst->FullDstRegisters[0]),
549 get_result_flags(inst), 0,
550 swizzle(src0, X, X, X, X), 0, 0);
551 break;
552
553 case TGSI_OPCODE_FLR:
554 emit_simple_arith(p, inst, A0_FLR, 1);
555 break;
556
557 case TGSI_OPCODE_FRC:
558 emit_simple_arith(p, inst, A0_FRC, 1);
559 break;
560
561 case TGSI_OPCODE_KIL:
562 /* unconditional kill */
563 assert(0); /* not tested yet */
564 #if 0
565 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
566 tmp = i915_get_utemp(p);
567
568 i915_emit_texld(p, tmp, A0_DEST_CHANNEL_ALL, /* use a dummy dest reg */
569 0, src0, T0_TEXKILL);
570 #endif
571 break;
572
573 case TGSI_OPCODE_KILP:
574 /* kill if src[0].x < 0 || src[0].y < 0 ... */
575 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
576 tmp = i915_get_utemp(p);
577
578 i915_emit_texld(p,
579 tmp, /* dest reg: a dummy reg */
580 A0_DEST_CHANNEL_ALL, /* dest writemask */
581 0, /* sampler */
582 src0, /* coord*/
583 T0_TEXKILL); /* opcode */
584 break;
585
586 case TGSI_OPCODE_LG2:
587 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
588
589 i915_emit_arith(p,
590 A0_LOG,
591 get_result_vector(p, &inst->FullDstRegisters[0]),
592 get_result_flags(inst), 0,
593 swizzle(src0, X, X, X, X), 0, 0);
594 break;
595
596 case TGSI_OPCODE_LIT:
597 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
598 tmp = i915_get_utemp(p);
599
600 /* tmp = max( a.xyzw, a.00zw )
601 * XXX: Clamp tmp.w to -128..128
602 * tmp.y = log(tmp.y)
603 * tmp.y = tmp.w * tmp.y
604 * tmp.y = exp(tmp.y)
605 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
606 */
607 i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0,
608 src0, swizzle(src0, ZERO, ZERO, Z, W), 0);
609
610 i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0,
611 swizzle(tmp, Y, Y, Y, Y), 0, 0);
612
613 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0,
614 swizzle(tmp, ZERO, Y, ZERO, ZERO),
615 swizzle(tmp, ZERO, W, ZERO, ZERO), 0);
616
617 i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0,
618 swizzle(tmp, Y, Y, Y, Y), 0, 0);
619
620 i915_emit_arith(p, A0_CMP,
621 get_result_vector(p, &inst->FullDstRegisters[0]),
622 get_result_flags(inst), 0,
623 negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
624 swizzle(tmp, ONE, X, ZERO, ONE),
625 swizzle(tmp, ONE, X, Y, ONE));
626
627 break;
628
629 case TGSI_OPCODE_LRP:
630 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
631 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
632 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
633 flags = get_result_flags(inst);
634 tmp = i915_get_utemp(p);
635
636 /* b*a + c*(1-a)
637 *
638 * b*a + c - ca
639 *
640 * tmp = b*a + c,
641 * result = (-c)*a + tmp
642 */
643 i915_emit_arith(p, A0_MAD, tmp,
644 flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
645
646 i915_emit_arith(p, A0_MAD,
647 get_result_vector(p, &inst->FullDstRegisters[0]),
648 flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
649 break;
650
651 case TGSI_OPCODE_MAD:
652 emit_simple_arith(p, inst, A0_MAD, 3);
653 break;
654
655 case TGSI_OPCODE_MAX:
656 emit_simple_arith(p, inst, A0_MAX, 2);
657 break;
658
659 case TGSI_OPCODE_MIN:
660 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
661 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
662 tmp = i915_get_utemp(p);
663 flags = get_result_flags(inst);
664
665 i915_emit_arith(p,
666 A0_MAX,
667 tmp, flags & A0_DEST_CHANNEL_ALL, 0,
668 negate(src0, 1, 1, 1, 1),
669 negate(src1, 1, 1, 1, 1), 0);
670
671 i915_emit_arith(p,
672 A0_MOV,
673 get_result_vector(p, &inst->FullDstRegisters[0]),
674 flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
675 break;
676
677 case TGSI_OPCODE_MOV:
678 /* aka TGSI_OPCODE_SWZ */
679 emit_simple_arith(p, inst, A0_MOV, 1);
680 break;
681
682 case TGSI_OPCODE_MUL:
683 emit_simple_arith(p, inst, A0_MUL, 2);
684 break;
685
686 case TGSI_OPCODE_POW:
687 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
688 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
689 tmp = i915_get_utemp(p);
690 flags = get_result_flags(inst);
691
692 /* XXX: masking on intermediate values, here and elsewhere.
693 */
694 i915_emit_arith(p,
695 A0_LOG,
696 tmp, A0_DEST_CHANNEL_X, 0,
697 swizzle(src0, X, X, X, X), 0, 0);
698
699 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0);
700
701 i915_emit_arith(p,
702 A0_EXP,
703 get_result_vector(p, &inst->FullDstRegisters[0]),
704 flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
705 break;
706
707 case TGSI_OPCODE_RET:
708 /* XXX: no-op? */
709 break;
710
711 case TGSI_OPCODE_RCP:
712 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
713
714 i915_emit_arith(p,
715 A0_RCP,
716 get_result_vector(p, &inst->FullDstRegisters[0]),
717 get_result_flags(inst), 0,
718 swizzle(src0, X, X, X, X), 0, 0);
719 break;
720
721 case TGSI_OPCODE_RSQ:
722 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
723
724 i915_emit_arith(p,
725 A0_RSQ,
726 get_result_vector(p, &inst->FullDstRegisters[0]),
727 get_result_flags(inst), 0,
728 swizzle(src0, X, X, X, X), 0, 0);
729 break;
730
731 case TGSI_OPCODE_SCS:
732 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
733 tmp = i915_get_utemp(p);
734
735 /*
736 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
737 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
738 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
739 * scs.x = DP4 t1, sin_constants
740 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
741 * scs.y = DP4 t1, cos_constants
742 */
743 i915_emit_arith(p,
744 A0_MUL,
745 tmp, A0_DEST_CHANNEL_XY, 0,
746 swizzle(src0, X, X, ONE, ONE),
747 swizzle(src0, X, ONE, ONE, ONE), 0);
748
749 i915_emit_arith(p,
750 A0_MUL,
751 tmp, A0_DEST_CHANNEL_ALL, 0,
752 swizzle(tmp, X, Y, X, Y),
753 swizzle(tmp, X, X, ONE, ONE), 0);
754
755 writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
756
757 if (writemask & TGSI_WRITEMASK_Y) {
758 uint tmp1;
759
760 if (writemask & TGSI_WRITEMASK_X)
761 tmp1 = i915_get_utemp(p);
762 else
763 tmp1 = tmp;
764
765 i915_emit_arith(p,
766 A0_MUL,
767 tmp1, A0_DEST_CHANNEL_ALL, 0,
768 swizzle(tmp, X, Y, Y, W),
769 swizzle(tmp, X, Z, ONE, ONE), 0);
770
771 i915_emit_arith(p,
772 A0_DP4,
773 get_result_vector(p, &inst->FullDstRegisters[0]),
774 A0_DEST_CHANNEL_Y, 0,
775 swizzle(tmp1, W, Z, Y, X),
776 i915_emit_const4fv(p, sin_constants), 0);
777 }
778
779 if (writemask & TGSI_WRITEMASK_X) {
780 i915_emit_arith(p,
781 A0_MUL,
782 tmp, A0_DEST_CHANNEL_XYZ, 0,
783 swizzle(tmp, X, X, Z, ONE),
784 swizzle(tmp, Z, ONE, ONE, ONE), 0);
785
786 i915_emit_arith(p,
787 A0_DP4,
788 get_result_vector(p, &inst->FullDstRegisters[0]),
789 A0_DEST_CHANNEL_X, 0,
790 swizzle(tmp, ONE, Z, Y, X),
791 i915_emit_const4fv(p, cos_constants), 0);
792 }
793 break;
794
795 case TGSI_OPCODE_SGE:
796 emit_simple_arith(p, inst, A0_SGE, 2);
797 break;
798
799 case TGSI_OPCODE_SLE:
800 /* like SGE, but swap reg0, reg1 */
801 emit_simple_arith_swap2(p, inst, A0_SGE, 2);
802 break;
803
804 case TGSI_OPCODE_SIN:
805 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
806 tmp = i915_get_utemp(p);
807
808 i915_emit_arith(p,
809 A0_MUL,
810 tmp, A0_DEST_CHANNEL_X, 0,
811 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
812
813 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
814
815 /* By choosing different taylor constants, could get rid of this mul:
816 */
817 i915_emit_arith(p,
818 A0_MUL,
819 tmp, A0_DEST_CHANNEL_X, 0,
820 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
821
822 /*
823 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
824 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
825 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
826 * result = DP4 t1.wzyx, sin_constants
827 */
828 i915_emit_arith(p,
829 A0_MUL,
830 tmp, A0_DEST_CHANNEL_XY, 0,
831 swizzle(tmp, X, X, ONE, ONE),
832 swizzle(tmp, X, ONE, ONE, ONE), 0);
833
834 i915_emit_arith(p,
835 A0_MUL,
836 tmp, A0_DEST_CHANNEL_ALL, 0,
837 swizzle(tmp, X, Y, X, Y),
838 swizzle(tmp, X, X, ONE, ONE), 0);
839
840 i915_emit_arith(p,
841 A0_MUL,
842 tmp, A0_DEST_CHANNEL_ALL, 0,
843 swizzle(tmp, X, Y, Y, W),
844 swizzle(tmp, X, Z, ONE, ONE), 0);
845
846 i915_emit_arith(p,
847 A0_DP4,
848 get_result_vector(p, &inst->FullDstRegisters[0]),
849 get_result_flags(inst), 0,
850 swizzle(tmp, W, Z, Y, X),
851 i915_emit_const4fv(p, sin_constants), 0);
852 break;
853
854 case TGSI_OPCODE_SLT:
855 emit_simple_arith(p, inst, A0_SLT, 2);
856 break;
857
858 case TGSI_OPCODE_SGT:
859 /* like SLT, but swap reg0, reg1 */
860 emit_simple_arith_swap2(p, inst, A0_SLT, 2);
861 break;
862
863 case TGSI_OPCODE_SUB:
864 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
865 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
866
867 i915_emit_arith(p,
868 A0_ADD,
869 get_result_vector(p, &inst->FullDstRegisters[0]),
870 get_result_flags(inst), 0,
871 src0, negate(src1, 1, 1, 1, 1), 0);
872 break;
873
874 case TGSI_OPCODE_TEX:
875 if (inst->FullSrcRegisters[0].SrcRegisterExtSwz.ExtDivide
876 == TGSI_EXTSWIZZLE_W) {
877 emit_tex(p, inst, T0_TEXLDP);
878 }
879 else {
880 emit_tex(p, inst, T0_TEXLD);
881 }
882 break;
883
884 case TGSI_OPCODE_TXB:
885 emit_tex(p, inst, T0_TEXLDB);
886 break;
887
888 case TGSI_OPCODE_XPD:
889 /* Cross product:
890 * result.x = src0.y * src1.z - src0.z * src1.y;
891 * result.y = src0.z * src1.x - src0.x * src1.z;
892 * result.z = src0.x * src1.y - src0.y * src1.x;
893 * result.w = undef;
894 */
895 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
896 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
897 tmp = i915_get_utemp(p);
898
899 i915_emit_arith(p,
900 A0_MUL,
901 tmp, A0_DEST_CHANNEL_ALL, 0,
902 swizzle(src0, Z, X, Y, ONE),
903 swizzle(src1, Y, Z, X, ONE), 0);
904
905 i915_emit_arith(p,
906 A0_MAD,
907 get_result_vector(p, &inst->FullDstRegisters[0]),
908 get_result_flags(inst), 0,
909 swizzle(src0, Y, Z, X, ONE),
910 swizzle(src1, Z, X, Y, ONE),
911 negate(tmp, 1, 1, 1, 0));
912 break;
913
914 default:
915 i915_program_error(p, "bad opcode %d", inst->Instruction.Opcode);
916 p->error = 1;
917 return;
918 }
919
920 i915_release_utemps(p);
921 }
922
923
924 /**
925 * Translate TGSI fragment shader into i915 hardware instructions.
926 * \param p the translation state
927 * \param tokens the TGSI token array
928 */
929 static void
930 i915_translate_instructions(struct i915_fp_compile *p,
931 const struct tgsi_token *tokens)
932 {
933 struct i915_fragment_shader *ifs = p->shader;
934 struct tgsi_parse_context parse;
935
936 tgsi_parse_init( &parse, tokens );
937
938 while( !tgsi_parse_end_of_tokens( &parse ) ) {
939
940 tgsi_parse_token( &parse );
941
942 switch( parse.FullToken.Token.Type ) {
943 case TGSI_TOKEN_TYPE_DECLARATION:
944 if (parse.FullToken.FullDeclaration.Declaration.File
945 == TGSI_FILE_CONSTANT) {
946 uint i;
947 for (i = parse.FullToken.FullDeclaration.u.DeclarationRange.First;
948 i <= parse.FullToken.FullDeclaration.u.DeclarationRange.Last;
949 i++) {
950 assert(ifs->constant_flags[i] == 0x0);
951 ifs->constant_flags[i] = I915_CONSTFLAG_USER;
952 ifs->num_constants = MAX2(ifs->num_constants, i + 1);
953 }
954 }
955 else if (parse.FullToken.FullDeclaration.Declaration.File
956 == TGSI_FILE_TEMPORARY) {
957 uint i;
958 for (i = parse.FullToken.FullDeclaration.u.DeclarationRange.First;
959 i <= parse.FullToken.FullDeclaration.u.DeclarationRange.Last;
960 i++) {
961 assert(i < I915_MAX_TEMPORARY);
962 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
963 p->temp_flag |= (1 << i); /* mark temp as used */
964 }
965 }
966 break;
967
968 case TGSI_TOKEN_TYPE_IMMEDIATE:
969 {
970 const struct tgsi_full_immediate *imm
971 = &parse.FullToken.FullImmediate;
972 const uint pos = p->num_immediates++;
973 uint j;
974 for (j = 0; j < imm->Immediate.Size; j++) {
975 p->immediates[pos][j] = imm->u.ImmediateFloat32[j].Float;
976 }
977 }
978 break;
979
980 case TGSI_TOKEN_TYPE_INSTRUCTION:
981 if (p->first_instruction) {
982 /* resolve location of immediates */
983 uint i, j;
984 for (i = 0; i < p->num_immediates; i++) {
985 /* find constant slot for this immediate */
986 for (j = 0; j < I915_MAX_CONSTANT; j++) {
987 if (ifs->constant_flags[j] == 0x0) {
988 memcpy(ifs->constants[j],
989 p->immediates[i],
990 4 * sizeof(float));
991 /*printf("immediate %d maps to const %d\n", i, j);*/
992 ifs->constant_flags[j] = 0xf; /* all four comps used */
993 p->immediates_map[i] = j;
994 ifs->num_constants = MAX2(ifs->num_constants, j + 1);
995 break;
996 }
997 }
998 }
999
1000 p->first_instruction = FALSE;
1001 }
1002
1003 i915_translate_instruction(p, &parse.FullToken.FullInstruction);
1004 break;
1005
1006 default:
1007 assert( 0 );
1008 }
1009
1010 } /* while */
1011
1012 tgsi_parse_free (&parse);
1013 }
1014
1015
1016 static struct i915_fp_compile *
1017 i915_init_compile(struct i915_context *i915,
1018 struct i915_fragment_shader *ifs)
1019 {
1020 struct i915_fp_compile *p = CALLOC_STRUCT(i915_fp_compile);
1021
1022 p->shader = ifs;
1023
1024 /* Put new constants at end of const buffer, growing downward.
1025 * The problem is we don't know how many user-defined constants might
1026 * be specified with pipe->set_constant_buffer().
1027 * Should pre-scan the user's program to determine the highest-numbered
1028 * constant referenced.
1029 */
1030 ifs->num_constants = 0;
1031 memset(ifs->constant_flags, 0, sizeof(ifs->constant_flags));
1032
1033 p->first_instruction = TRUE;
1034
1035 p->nr_tex_indirect = 1; /* correct? */
1036 p->nr_tex_insn = 0;
1037 p->nr_alu_insn = 0;
1038 p->nr_decl_insn = 0;
1039
1040 p->csr = p->program;
1041 p->decl = p->declarations;
1042 p->decl_s = 0;
1043 p->decl_t = 0;
1044 p->temp_flag = ~0x0 << I915_MAX_TEMPORARY;
1045 p->utemp_flag = ~0x7;
1046
1047 p->wpos_tex = -1;
1048
1049 /* initialize the first program word */
1050 *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM;
1051
1052 return p;
1053 }
1054
1055
1056 /* Copy compile results to the fragment program struct and destroy the
1057 * compilation context.
1058 */
1059 static void
1060 i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p)
1061 {
1062 struct i915_fragment_shader *ifs = p->shader;
1063 unsigned long program_size = (unsigned long) (p->csr - p->program);
1064 unsigned long decl_size = (unsigned long) (p->decl - p->declarations);
1065
1066 if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
1067 i915_program_error(p, "Exceeded max nr indirect texture lookups");
1068
1069 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
1070 i915_program_error(p, "Exceeded max TEX instructions");
1071
1072 if (p->nr_alu_insn > I915_MAX_ALU_INSN)
1073 i915_program_error(p, "Exceeded max ALU instructions");
1074
1075 if (p->nr_decl_insn > I915_MAX_DECL_INSN)
1076 i915_program_error(p, "Exceeded max DECL instructions");
1077
1078 if (p->error) {
1079 p->NumNativeInstructions = 0;
1080 p->NumNativeAluInstructions = 0;
1081 p->NumNativeTexInstructions = 0;
1082 p->NumNativeTexIndirections = 0;
1083
1084 i915_use_passthrough_shader(ifs);
1085 }
1086 else {
1087 p->NumNativeInstructions
1088 = p->nr_alu_insn + p->nr_tex_insn + p->nr_decl_insn;
1089 p->NumNativeAluInstructions = p->nr_alu_insn;
1090 p->NumNativeTexInstructions = p->nr_tex_insn;
1091 p->NumNativeTexIndirections = p->nr_tex_indirect;
1092
1093 /* patch in the program length */
1094 p->declarations[0] |= program_size + decl_size - 2;
1095
1096 /* Copy compilation results to fragment program struct:
1097 */
1098 assert(!ifs->program);
1099 ifs->program
1100 = (uint *) MALLOC((program_size + decl_size) * sizeof(uint));
1101 if (ifs->program) {
1102 ifs->program_len = program_size + decl_size;
1103
1104 memcpy(ifs->program,
1105 p->declarations,
1106 decl_size * sizeof(uint));
1107
1108 memcpy(ifs->program + decl_size,
1109 p->program,
1110 program_size * sizeof(uint));
1111 }
1112 }
1113
1114 /* Release the compilation struct:
1115 */
1116 FREE(p);
1117 }
1118
1119
1120 /**
1121 * Find an unused texture coordinate slot to use for fragment WPOS.
1122 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1123 */
1124 static void
1125 i915_find_wpos_space(struct i915_fp_compile *p)
1126 {
1127 #if 0
1128 const uint inputs
1129 = p->shader->inputs_read | (1 << TGSI_ATTRIB_POS); /*XXX hack*/
1130 uint i;
1131
1132 p->wpos_tex = -1;
1133
1134 if (inputs & (1 << TGSI_ATTRIB_POS)) {
1135 for (i = 0; i < I915_TEX_UNITS; i++) {
1136 if ((inputs & (1 << (TGSI_ATTRIB_TEX0 + i))) == 0) {
1137 p->wpos_tex = i;
1138 return;
1139 }
1140 }
1141
1142 i915_program_error(p, "No free texcoord for wpos value");
1143 }
1144 #else
1145 if (p->shader->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1146 /* frag shader using the fragment position input */
1147 #if 0
1148 assert(0);
1149 #endif
1150 }
1151 #endif
1152 }
1153
1154
1155
1156
1157 /**
1158 * Rather than trying to intercept and jiggle depth writes during
1159 * emit, just move the value into its correct position at the end of
1160 * the program:
1161 */
1162 static void
1163 i915_fixup_depth_write(struct i915_fp_compile *p)
1164 {
1165 /* XXX assuming pos/depth is always in output[0] */
1166 if (p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1167 const uint depth = UREG(REG_TYPE_OD, 0);
1168
1169 i915_emit_arith(p,
1170 A0_MOV, /* opcode */
1171 depth, /* dest reg */
1172 A0_DEST_CHANNEL_W, /* write mask */
1173 0, /* saturate? */
1174 swizzle(depth, X, Y, Z, Z), /* src0 */
1175 0, 0 /* src1, src2 */);
1176 }
1177 }
1178
1179
1180 void
1181 i915_translate_fragment_program( struct i915_context *i915,
1182 struct i915_fragment_shader *fs)
1183 {
1184 struct i915_fp_compile *p = i915_init_compile(i915, fs);
1185 const struct tgsi_token *tokens = fs->state.tokens;
1186
1187 i915_find_wpos_space(p);
1188
1189 #if 0
1190 tgsi_dump(tokens, 0);
1191 #endif
1192
1193 i915_translate_instructions(p, tokens);
1194 i915_fixup_depth_write(p);
1195
1196 i915_fini_compile(i915, p);
1197 }