src/gallium/drivers/i965/brw_clip.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_math.h"
  35
  36 #include "brw_screen.h"
  37 #include "brw_batchbuffer.h"
  38 #include "brw_defines.h"
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "brw_util.h"
  42 #include "brw_state.h"
  43 #include "brw_pipe_rast.h"
  44 #include "brw_clip.h"
  45
  46
  47 #define FRONT_UNFILLED_BIT  0x1
  48 #define BACK_UNFILLED_BIT   0x2
  49
  50
  51 static enum pipe_error
  52 compile_clip_prog( struct brw_context *brw,
  53                    struct brw_clip_prog_key *key,
  54                    struct brw_winsys_buffer **bo_out )
  55 {
  56    enum pipe_error ret;
  57    struct brw_clip_compile c;
  58    const GLuint *program;
  59    GLuint program_size;
  60    GLuint delta;
  61
  62    memset(&c, 0, sizeof(c));
  63
  64    /* Begin the compilation:
  65     */
  66    brw_init_compile(brw, &c.func);
  67
  68    c.func.single_program_flow = 1;
  69
  70    c.chipset = brw->chipset;
  71    c.key = *key;
  72    c.need_ff_sync = c.chipset.is_igdng;
  73
  74    /* Need to locate the two positions present in vertex + header.
  75     * These are currently hardcoded:
  76     */
  77    c.header_position_offset = ATTR_SIZE;
  78
  79    if (c.chipset.is_igdng)
  80        delta = 3 * REG_SIZE;
  81    else
  82        delta = REG_SIZE;
  83
  84    /* XXX: c.nr_attrs is very redundant:
  85     */
  86    c.nr_attrs = c.key.nr_attrs;
  87
  88    c.offset_hpos = delta + c.key.output_hpos * ATTR_SIZE;
  89
  90    if (c.key.output_color0)
  91       c.offset_color0 = delta + c.key.output_color0 * ATTR_SIZE;
  92
  93    if (c.key.output_color1)
  94       c.offset_color1 = delta + c.key.output_color1 * ATTR_SIZE;
  95
  96    if (c.key.output_bfc0)
  97       c.offset_bfc0 = delta + c.key.output_bfc0 * ATTR_SIZE;
  98
  99    if (c.key.output_bfc1)
 100       c.offset_bfc1 = delta + c.key.output_bfc1 * ATTR_SIZE;
 101
 102    if (c.key.output_edgeflag)
 103       c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
 104
 105    if (BRW_IS_IGDNG(brw))
 106        c.nr_regs = (c.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
 107    else
 108        c.nr_regs = (c.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
 109
 110    c.nr_bytes = c.nr_regs * REG_SIZE;
 111
 112    c.prog_data.clip_mode = c.key.clip_mode; /* XXX */
 113
 114    /* For some reason the thread is spawned with only 4 channels
 115     * unmasked.
 116     */
 117    brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
 118
 119
 120    /* Would ideally have the option of producing a program which could
 121     * do all three:
 122     */
 123    switch (key->primitive) {
 124    case PIPE_PRIM_TRIANGLES:
 125       if (key->do_unfilled)
 126          brw_emit_unfilled_clip( &c );
 127       else
 128          brw_emit_tri_clip( &c );
 129       break;
 130    case PIPE_PRIM_LINES:
 131       brw_emit_line_clip( &c );
 132       break;
 133    case PIPE_PRIM_POINTS:
 134       brw_emit_point_clip( &c );
 135       break;
 136    default:
 137       assert(0);
 138       return PIPE_ERROR_BAD_INPUT;
 139    }
 140
 141
 142
 143    /* get the program
 144     */
 145    ret = brw_get_program(&c.func, &program, &program_size);
 146    if (ret)
 147       return ret;
 148
 149    /* Upload
 150     */
 151    ret = brw_upload_cache( &brw->cache,
 152                            BRW_CLIP_PROG,
 153                            &c.key, sizeof(c.key),
 154                            NULL, 0,
 155                            program, program_size,
 156                            &c.prog_data,
 157                            &brw->clip.prog_data,
 158                            bo_out );
 159    if (ret)
 160       return ret;
 161
 162    return PIPE_OK;
 163 }
 164
 165 /* Calculate interpolants for triangle and line rasterization.
 166  */
 167 static enum pipe_error
 168 upload_clip_prog(struct brw_context *brw)
 169 {
 170    const struct brw_vertex_shader *vs = brw->curr.vertex_shader;
 171    struct brw_clip_prog_key key;
 172    enum pipe_error ret;
 173
 174    /* Populate the key, starting from the almost-complete version from
 175     * the rast state.
 176     */
 177
 178    /* PIPE_NEW_RAST */
 179    key = brw->curr.rast->clip_key;
 180
 181    /* BRW_NEW_REDUCED_PRIMITIVE */
 182    key.primitive = brw->reduced_primitive;
 183
 184    /* XXX: if edgeflag is moved to a proper TGSI vs output, can remove
 185     * dependency on CACHE_NEW_VS_PROG
 186     */
 187    /* CACHE_NEW_VS_PROG */
 188    key.nr_attrs        = brw->vs.prog_data->nr_outputs;
 189    key.output_edgeflag = brw->vs.prog_data->output_edgeflag;
 190
 191    /* PIPE_NEW_VS */
 192    key.output_hpos     = vs->output_hpos;
 193    key.output_color0   = vs->output_color0;
 194    key.output_color1   = vs->output_color1;
 195    key.output_bfc0     = vs->output_bfc0;
 196    key.output_bfc1     = vs->output_bfc1;
 197
 198    /* PIPE_NEW_CLIP */
 199    key.nr_userclip = brw->curr.ucp.nr;
 200
 201    /* Already cached?
 202     */
 203    if (brw_search_cache(&brw->cache, BRW_CLIP_PROG,
 204                         &key, sizeof(key),
 205                         NULL, 0,
 206                         &brw->clip.prog_data,
 207                         &brw->clip.prog_bo))
 208       return PIPE_OK;
 209
 210    /* Compile new program:
 211     */
 212    ret = compile_clip_prog( brw, &key, &brw->clip.prog_bo );
 213    if (ret)
 214       return ret;
 215
 216    return PIPE_OK;
 217 }
 218
 219
 220 const struct brw_tracked_state brw_clip_prog = {
 221    .dirty = {
 222       .mesa  = (PIPE_NEW_RAST |
 223                 PIPE_NEW_CLIP),
 224       .brw   = (BRW_NEW_REDUCED_PRIMITIVE),
 225       .cache = CACHE_NEW_VS_PROG
 226    },
 227    .prepare = upload_clip_prog
 228 };