src/gallium/drivers/i965/brw_clip.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_math.h"
  35
  36 #include "brw_screen.h"
  37 #include "brw_batchbuffer.h"
  38 #include "brw_defines.h"
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "brw_state.h"
  42 #include "brw_pipe_rast.h"
  43 #include "brw_clip.h"
  44
  45
  46 #define FRONT_UNFILLED_BIT  0x1
  47 #define BACK_UNFILLED_BIT   0x2
  48
  49
  50 static enum pipe_error
  51 compile_clip_prog( struct brw_context *brw,
  52                    struct brw_clip_prog_key *key,
  53                    struct brw_winsys_buffer **bo_out )
  54 {
  55    enum pipe_error ret;
  56    struct brw_clip_compile c;
  57    const GLuint *program;
  58    GLuint program_size;
  59    GLuint delta;
  60
  61    memset(&c, 0, sizeof(c));
  62
  63    /* Begin the compilation:
  64     */
  65    brw_init_compile(brw, &c.func);
  66
  67    c.func.single_program_flow = 1;
  68
  69    c.key = *key;
  70
  71    /* Need to locate the two positions present in vertex + header.
  72     * These are currently hardcoded:
  73     */
  74    c.header_position_offset = ATTR_SIZE;
  75
  76    if (brw->gen == 5)
  77        delta = 3 * REG_SIZE;
  78    else
  79        delta = REG_SIZE;
  80
  81    c.offset_hpos = delta + c.key.output_hpos * ATTR_SIZE;
  82
  83    if (c.key.output_color0 != BRW_OUTPUT_NOT_PRESENT)
  84       c.offset_color0 = delta + c.key.output_color0 * ATTR_SIZE;
  85
  86    if (c.key.output_color1 != BRW_OUTPUT_NOT_PRESENT)
  87       c.offset_color1 = delta + c.key.output_color1 * ATTR_SIZE;
  88
  89    if (c.key.output_bfc0 != BRW_OUTPUT_NOT_PRESENT)
  90       c.offset_bfc0 = delta + c.key.output_bfc0 * ATTR_SIZE;
  91
  92    if (c.key.output_bfc1 != BRW_OUTPUT_NOT_PRESENT)
  93       c.offset_bfc1 = delta + c.key.output_bfc1 * ATTR_SIZE;
  94
  95    if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT)
  96       c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
  97
  98    if (brw->gen == 5)
  99        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
 100    else
 101        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
 102
 103    c.nr_bytes = c.nr_regs * REG_SIZE;
 104
 105    c.prog_data.clip_mode = c.key.clip_mode; /* XXX */
 106
 107    /* For some reason the thread is spawned with only 4 channels
 108     * unmasked.
 109     */
 110    brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
 111
 112
 113    /* Would ideally have the option of producing a program which could
 114     * do all three:
 115     */
 116    switch (key->primitive) {
 117    case PIPE_PRIM_TRIANGLES:
 118       if (key->do_unfilled)
 119          brw_emit_unfilled_clip( &c );
 120       else
 121          brw_emit_tri_clip( &c );
 122       break;
 123    case PIPE_PRIM_LINES:
 124       brw_emit_line_clip( &c );
 125       break;
 126    case PIPE_PRIM_POINTS:
 127       brw_emit_point_clip( &c );
 128       break;
 129    default:
 130       assert(0);
 131       return PIPE_ERROR_BAD_INPUT;
 132    }
 133
 134
 135
 136    /* get the program
 137     */
 138    ret = brw_get_program(&c.func, &program, &program_size);
 139    if (ret)
 140       return ret;
 141
 142    /* Upload
 143     */
 144    ret = brw_upload_cache( &brw->cache,
 145                            BRW_CLIP_PROG,
 146                            &c.key, sizeof(c.key),
 147                            NULL, 0,
 148                            program, program_size,
 149                            &c.prog_data,
 150                            &brw->clip.prog_data,
 151                            bo_out );
 152    if (ret)
 153       return ret;
 154
 155    return PIPE_OK;
 156 }
 157
 158 /* Calculate interpolants for triangle and line rasterization.
 159  */
 160 static enum pipe_error
 161 upload_clip_prog(struct brw_context *brw)
 162 {
 163    const struct brw_vertex_shader *vs = brw->curr.vertex_shader;
 164    struct brw_clip_prog_key key;
 165    enum pipe_error ret;
 166
 167    /* Populate the key, starting from the almost-complete version from
 168     * the rast state.
 169     */
 170
 171    /* PIPE_NEW_RAST */
 172    key = brw->curr.rast->clip_key;
 173
 174    /* BRW_NEW_REDUCED_PRIMITIVE */
 175    key.primitive = brw->reduced_primitive;
 176
 177    /* XXX: if edgeflag is moved to a proper TGSI vs output, can remove
 178     * dependency on CACHE_NEW_VS_PROG
 179     */
 180    /* CACHE_NEW_VS_PROG */
 181    key.nr_attrs        = brw->vs.prog_data->nr_outputs;
 182
 183    /* PIPE_NEW_VS */
 184    key.output_hpos     = vs->output_hpos;
 185    key.output_color0   = vs->output_color0;
 186    key.output_color1   = vs->output_color1;
 187    key.output_bfc0     = vs->output_bfc0;
 188    key.output_bfc1     = vs->output_bfc1;
 189    key.output_edgeflag = vs->output_edgeflag;
 190
 191    /* PIPE_NEW_CLIP */
 192    key.nr_userclip = brw->curr.ucp.nr;
 193
 194    /* Already cached?
 195     */
 196    if (brw_search_cache(&brw->cache, BRW_CLIP_PROG,
 197                         &key, sizeof(key),
 198                         NULL, 0,
 199                         &brw->clip.prog_data,
 200                         &brw->clip.prog_bo))
 201       return PIPE_OK;
 202
 203    /* Compile new program:
 204     */
 205    ret = compile_clip_prog( brw, &key, &brw->clip.prog_bo );
 206    if (ret)
 207       return ret;
 208
 209    return PIPE_OK;
 210 }
 211
 212
 213 const struct brw_tracked_state brw_clip_prog = {
 214    .dirty = {
 215       .mesa  = (PIPE_NEW_RAST |
 216                 PIPE_NEW_CLIP),
 217       .brw   = (BRW_NEW_REDUCED_PRIMITIVE),
 218       .cache = CACHE_NEW_VS_PROG
 219    },
 220    .prepare = upload_clip_prog
 221 };