src/gallium/drivers/i965/brw_clip.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_math.h"
  35
  36 #include "brw_screen.h"
  37 #include "brw_batchbuffer.h"
  38 #include "brw_defines.h"
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "brw_state.h"
  42 #include "brw_pipe_rast.h"
  43 #include "brw_clip.h"
  44
  45
  46 #define FRONT_UNFILLED_BIT  0x1
  47 #define BACK_UNFILLED_BIT   0x2
  48
  49
  50 static enum pipe_error
  51 compile_clip_prog( struct brw_context *brw,
  52                    struct brw_clip_prog_key *key,
  53                    struct brw_winsys_buffer **bo_out )
  54 {
  55    enum pipe_error ret;
  56    struct brw_clip_compile c;
  57    const GLuint *program;
  58    GLuint program_size;
  59    GLuint delta;
  60
  61    memset(&c, 0, sizeof(c));
  62
  63    /* Begin the compilation:
  64     */
  65    brw_init_compile(brw, &c.func);
  66
  67    c.func.single_program_flow = 1;
  68
  69    c.chipset = brw->chipset;
  70    c.key = *key;
  71    c.need_ff_sync = c.chipset.is_igdng;
  72
  73    /* Need to locate the two positions present in vertex + header.
  74     * These are currently hardcoded:
  75     */
  76    c.header_position_offset = ATTR_SIZE;
  77
  78    if (c.chipset.is_igdng)
  79        delta = 3 * REG_SIZE;
  80    else
  81        delta = REG_SIZE;
  82
  83    c.offset_hpos = delta + c.key.output_hpos * ATTR_SIZE;
  84
  85    if (c.key.output_color0 != BRW_OUTPUT_NOT_PRESENT)
  86       c.offset_color0 = delta + c.key.output_color0 * ATTR_SIZE;
  87
  88    if (c.key.output_color1 != BRW_OUTPUT_NOT_PRESENT)
  89       c.offset_color1 = delta + c.key.output_color1 * ATTR_SIZE;
  90
  91    if (c.key.output_bfc0 != BRW_OUTPUT_NOT_PRESENT)
  92       c.offset_bfc0 = delta + c.key.output_bfc0 * ATTR_SIZE;
  93
  94    if (c.key.output_bfc1 != BRW_OUTPUT_NOT_PRESENT)
  95       c.offset_bfc1 = delta + c.key.output_bfc1 * ATTR_SIZE;
  96
  97    if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT)
  98       c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
  99
 100    if (BRW_IS_IGDNG(brw))
 101        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
 102    else
 103        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
 104
 105    c.nr_bytes = c.nr_regs * REG_SIZE;
 106
 107    c.prog_data.clip_mode = c.key.clip_mode; /* XXX */
 108
 109    /* For some reason the thread is spawned with only 4 channels
 110     * unmasked.
 111     */
 112    brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
 113
 114
 115    /* Would ideally have the option of producing a program which could
 116     * do all three:
 117     */
 118    switch (key->primitive) {
 119    case PIPE_PRIM_TRIANGLES:
 120       if (key->do_unfilled)
 121          brw_emit_unfilled_clip( &c );
 122       else
 123          brw_emit_tri_clip( &c );
 124       break;
 125    case PIPE_PRIM_LINES:
 126       brw_emit_line_clip( &c );
 127       break;
 128    case PIPE_PRIM_POINTS:
 129       brw_emit_point_clip( &c );
 130       break;
 131    default:
 132       assert(0);
 133       return PIPE_ERROR_BAD_INPUT;
 134    }
 135
 136
 137
 138    /* get the program
 139     */
 140    ret = brw_get_program(&c.func, &program, &program_size);
 141    if (ret)
 142       return ret;
 143
 144    /* Upload
 145     */
 146    ret = brw_upload_cache( &brw->cache,
 147                            BRW_CLIP_PROG,
 148                            &c.key, sizeof(c.key),
 149                            NULL, 0,
 150                            program, program_size,
 151                            &c.prog_data,
 152                            &brw->clip.prog_data,
 153                            bo_out );
 154    if (ret)
 155       return ret;
 156
 157    return PIPE_OK;
 158 }
 159
 160 /* Calculate interpolants for triangle and line rasterization.
 161  */
 162 static enum pipe_error
 163 upload_clip_prog(struct brw_context *brw)
 164 {
 165    const struct brw_vertex_shader *vs = brw->curr.vertex_shader;
 166    struct brw_clip_prog_key key;
 167    enum pipe_error ret;
 168
 169    /* Populate the key, starting from the almost-complete version from
 170     * the rast state.
 171     */
 172
 173    /* PIPE_NEW_RAST */
 174    key = brw->curr.rast->clip_key;
 175
 176    /* BRW_NEW_REDUCED_PRIMITIVE */
 177    key.primitive = brw->reduced_primitive;
 178
 179    /* XXX: if edgeflag is moved to a proper TGSI vs output, can remove
 180     * dependency on CACHE_NEW_VS_PROG
 181     */
 182    /* CACHE_NEW_VS_PROG */
 183    key.nr_attrs        = brw->vs.prog_data->nr_outputs;
 184
 185    /* PIPE_NEW_VS */
 186    key.output_hpos     = vs->output_hpos;
 187    key.output_color0   = vs->output_color0;
 188    key.output_color1   = vs->output_color1;
 189    key.output_bfc0     = vs->output_bfc0;
 190    key.output_bfc1     = vs->output_bfc1;
 191    key.output_edgeflag = vs->output_edgeflag;
 192
 193    /* PIPE_NEW_CLIP */
 194    key.nr_userclip = brw->curr.ucp.nr;
 195
 196    /* Already cached?
 197     */
 198    if (brw_search_cache(&brw->cache, BRW_CLIP_PROG,
 199                         &key, sizeof(key),
 200                         NULL, 0,
 201                         &brw->clip.prog_data,
 202                         &brw->clip.prog_bo))
 203       return PIPE_OK;
 204
 205    /* Compile new program:
 206     */
 207    ret = compile_clip_prog( brw, &key, &brw->clip.prog_bo );
 208    if (ret)
 209       return ret;
 210
 211    return PIPE_OK;
 212 }
 213
 214
 215 const struct brw_tracked_state brw_clip_prog = {
 216    .dirty = {
 217       .mesa  = (PIPE_NEW_RAST |
 218                 PIPE_NEW_CLIP),
 219       .brw   = (BRW_NEW_REDUCED_PRIMITIVE),
 220       .cache = CACHE_NEW_VS_PROG
 221    },
 222    .prepare = upload_clip_prog
 223 };