2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "pipe/p_state.h"
34 #include "util/u_math.h"
36 #include "brw_screen.h"
37 #include "brw_batchbuffer.h"
38 #include "brw_defines.h"
39 #include "brw_context.h"
41 #include "brw_state.h"
42 #include "brw_pipe_rast.h"
46 #define FRONT_UNFILLED_BIT 0x1
47 #define BACK_UNFILLED_BIT 0x2
50 static enum pipe_error
51 compile_clip_prog( struct brw_context
*brw
,
52 struct brw_clip_prog_key
*key
,
53 struct brw_winsys_buffer
**bo_out
)
56 struct brw_clip_compile c
;
57 const GLuint
*program
;
61 memset(&c
, 0, sizeof(c
));
63 /* Begin the compilation:
65 brw_init_compile(brw
, &c
.func
);
67 c
.func
.single_program_flow
= 1;
69 c
.chipset
= brw
->chipset
;
71 c
.need_ff_sync
= c
.chipset
.is_igdng
;
73 /* Need to locate the two positions present in vertex + header.
74 * These are currently hardcoded:
76 c
.header_position_offset
= ATTR_SIZE
;
78 if (c
.chipset
.is_igdng
)
83 c
.offset_hpos
= delta
+ c
.key
.output_hpos
* ATTR_SIZE
;
85 if (c
.key
.output_color0
!= BRW_OUTPUT_NOT_PRESENT
)
86 c
.offset_color0
= delta
+ c
.key
.output_color0
* ATTR_SIZE
;
88 if (c
.key
.output_color1
!= BRW_OUTPUT_NOT_PRESENT
)
89 c
.offset_color1
= delta
+ c
.key
.output_color1
* ATTR_SIZE
;
91 if (c
.key
.output_bfc0
!= BRW_OUTPUT_NOT_PRESENT
)
92 c
.offset_bfc0
= delta
+ c
.key
.output_bfc0
* ATTR_SIZE
;
94 if (c
.key
.output_bfc1
!= BRW_OUTPUT_NOT_PRESENT
)
95 c
.offset_bfc1
= delta
+ c
.key
.output_bfc1
* ATTR_SIZE
;
97 if (c
.key
.output_edgeflag
!= BRW_OUTPUT_NOT_PRESENT
)
98 c
.offset_edgeflag
= delta
+ c
.key
.output_edgeflag
* ATTR_SIZE
;
100 if (BRW_IS_IGDNG(brw
))
101 c
.nr_regs
= (c
.key
.nr_attrs
+ 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
103 c
.nr_regs
= (c
.key
.nr_attrs
+ 1) / 2 + 1; /* are vertices packed, or reg-aligned? */
105 c
.nr_bytes
= c
.nr_regs
* REG_SIZE
;
107 c
.prog_data
.clip_mode
= c
.key
.clip_mode
; /* XXX */
109 /* For some reason the thread is spawned with only 4 channels
112 brw_set_mask_control(&c
.func
, BRW_MASK_DISABLE
);
115 /* Would ideally have the option of producing a program which could
118 switch (key
->primitive
) {
119 case PIPE_PRIM_TRIANGLES
:
120 if (key
->do_unfilled
)
121 brw_emit_unfilled_clip( &c
);
123 brw_emit_tri_clip( &c
);
125 case PIPE_PRIM_LINES
:
126 brw_emit_line_clip( &c
);
128 case PIPE_PRIM_POINTS
:
129 brw_emit_point_clip( &c
);
133 return PIPE_ERROR_BAD_INPUT
;
140 ret
= brw_get_program(&c
.func
, &program
, &program_size
);
146 ret
= brw_upload_cache( &brw
->cache
,
148 &c
.key
, sizeof(c
.key
),
150 program
, program_size
,
152 &brw
->clip
.prog_data
,
160 /* Calculate interpolants for triangle and line rasterization.
162 static enum pipe_error
163 upload_clip_prog(struct brw_context
*brw
)
165 const struct brw_vertex_shader
*vs
= brw
->curr
.vertex_shader
;
166 struct brw_clip_prog_key key
;
169 /* Populate the key, starting from the almost-complete version from
174 key
= brw
->curr
.rast
->clip_key
;
176 /* BRW_NEW_REDUCED_PRIMITIVE */
177 key
.primitive
= brw
->reduced_primitive
;
179 /* XXX: if edgeflag is moved to a proper TGSI vs output, can remove
180 * dependency on CACHE_NEW_VS_PROG
182 /* CACHE_NEW_VS_PROG */
183 key
.nr_attrs
= brw
->vs
.prog_data
->nr_outputs
;
186 key
.output_hpos
= vs
->output_hpos
;
187 key
.output_color0
= vs
->output_color0
;
188 key
.output_color1
= vs
->output_color1
;
189 key
.output_bfc0
= vs
->output_bfc0
;
190 key
.output_bfc1
= vs
->output_bfc1
;
191 key
.output_edgeflag
= vs
->output_edgeflag
;
194 key
.nr_userclip
= brw
->curr
.ucp
.nr
;
198 if (brw_search_cache(&brw
->cache
, BRW_CLIP_PROG
,
201 &brw
->clip
.prog_data
,
205 /* Compile new program:
207 ret
= compile_clip_prog( brw
, &key
, &brw
->clip
.prog_bo
);
215 const struct brw_tracked_state brw_clip_prog
= {
217 .mesa
= (PIPE_NEW_RAST
|
219 .brw
= (BRW_NEW_REDUCED_PRIMITIVE
),
220 .cache
= CACHE_NEW_VS_PROG
222 .prepare
= upload_clip_prog