i965g: more work on compiling
[mesa.git] / src / gallium / drivers / i965 / brw_clip_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "util/u_math.h"
33
34 #include "brw_context.h"
35 #include "brw_clip.h"
36 #include "brw_state.h"
37 #include "brw_defines.h"
38 #include "brw_debug.h"
39
40 struct brw_clip_unit_key {
41 unsigned int total_grf;
42 unsigned int urb_entry_read_length;
43 unsigned int curb_entry_read_length;
44 unsigned int clip_mode;
45
46 unsigned int curbe_offset;
47
48 unsigned int nr_urb_entries, urb_size;
49
50 GLboolean depth_clamp;
51 };
52
53 static void
54 clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key)
55 {
56 memset(key, 0, sizeof(*key));
57
58 /* CACHE_NEW_CLIP_PROG */
59 key->total_grf = brw->clip.prog_data->total_grf;
60 key->urb_entry_read_length = brw->clip.prog_data->urb_read_length;
61 key->curb_entry_read_length = brw->clip.prog_data->curb_read_length;
62 key->clip_mode = brw->clip.prog_data->clip_mode;
63
64 /* BRW_NEW_CURBE_OFFSETS */
65 key->curbe_offset = brw->curbe.clip_start;
66
67 /* BRW_NEW_URB_FENCE */
68 key->nr_urb_entries = brw->urb.nr_clip_entries;
69 key->urb_size = brw->urb.vsize;
70
71 /* */
72 key->depth_clamp = 0; // XXX: add this to gallium: ctx->Transform.DepthClamp;
73 }
74
75 static struct brw_winsys_buffer *
76 clip_unit_create_from_key(struct brw_context *brw,
77 struct brw_clip_unit_key *key)
78 {
79 struct brw_clip_unit_state clip;
80 struct brw_winsys_buffer *bo;
81
82 memset(&clip, 0, sizeof(clip));
83
84 clip.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
85 /* reloc */
86 clip.thread0.kernel_start_pointer = brw->clip.prog_bo->offset >> 6;
87
88 clip.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
89 clip.thread1.single_program_flow = 1;
90
91 clip.thread3.urb_entry_read_length = key->urb_entry_read_length;
92 clip.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
93 clip.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
94 clip.thread3.dispatch_grf_start_reg = 1;
95 clip.thread3.urb_entry_read_offset = 0;
96
97 clip.thread4.nr_urb_entries = key->nr_urb_entries;
98 clip.thread4.urb_entry_allocation_size = key->urb_size - 1;
99 /* If we have enough clip URB entries to run two threads, do so.
100 */
101 if (key->nr_urb_entries >= 10) {
102 /* Half of the URB entries go to each thread, and it has to be an
103 * even number.
104 */
105 assert(key->nr_urb_entries % 2 == 0);
106
107 /* Although up to 16 concurrent Clip threads are allowed on IGDNG,
108 * only 2 threads can output VUEs at a time.
109 */
110 if (BRW_IS_IGDNG(brw))
111 clip.thread4.max_threads = 16 - 1;
112 else
113 clip.thread4.max_threads = 2 - 1;
114 } else {
115 assert(key->nr_urb_entries >= 5);
116 clip.thread4.max_threads = 1 - 1;
117 }
118
119 if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
120 clip.thread4.max_threads = 0;
121
122 if (BRW_DEBUG & DEBUG_STATS)
123 clip.thread4.stats_enable = 1;
124
125 clip.clip5.userclip_enable_flags = 0x7f;
126 clip.clip5.userclip_must_clip = 1;
127 clip.clip5.guard_band_enable = 0;
128 if (!key->depth_clamp)
129 clip.clip5.viewport_z_clip_enable = 1;
130 clip.clip5.viewport_xy_clip_enable = 1;
131 clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
132 clip.clip5.api_mode = BRW_CLIP_API_OGL;
133 clip.clip5.clip_mode = key->clip_mode;
134
135 if (BRW_IS_G4X(brw))
136 clip.clip5.negative_w_clip_test = 1;
137
138 clip.clip6.clipper_viewport_state_ptr = 0;
139 clip.viewport_xmin = -1;
140 clip.viewport_xmax = 1;
141 clip.viewport_ymin = -1;
142 clip.viewport_ymax = 1;
143
144 bo = brw_upload_cache(&brw->cache, BRW_CLIP_UNIT,
145 key, sizeof(*key),
146 &brw->clip.prog_bo, 1,
147 &clip, sizeof(clip),
148 NULL, NULL);
149
150 /* Emit clip program relocation */
151 assert(brw->clip.prog_bo);
152 brw->sws->bo_emit_reloc(bo,
153 I915_GEM_DOMAIN_INSTRUCTION,
154 0,
155 clip.thread0.grf_reg_count << 1,
156 offsetof(struct brw_clip_unit_state, thread0),
157 brw->clip.prog_bo);
158
159 return bo;
160 }
161
162 static void upload_clip_unit( struct brw_context *brw )
163 {
164 struct brw_clip_unit_key key;
165
166 clip_unit_populate_key(brw, &key);
167
168 brw->sws->bo_unreference(brw->clip.state_bo);
169 brw->clip.state_bo = brw_search_cache(&brw->cache, BRW_CLIP_UNIT,
170 &key, sizeof(key),
171 &brw->clip.prog_bo, 1,
172 NULL);
173 if (brw->clip.state_bo == NULL) {
174 brw->clip.state_bo = clip_unit_create_from_key(brw, &key);
175 }
176 }
177
178 const struct brw_tracked_state brw_clip_unit = {
179 .dirty = {
180 .mesa = 0,
181 .brw = (BRW_NEW_CURBE_OFFSETS |
182 BRW_NEW_URB_FENCE),
183 .cache = CACHE_NEW_CLIP_PROG
184 },
185 .prepare = upload_clip_unit,
186 };