2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_defines.h"
34 #include "brw_context.h"
42 struct brw_reg
get_tmp( struct brw_clip_compile
*c
)
44 struct brw_reg tmp
= brw_vec4_grf(c
->last_tmp
, 0);
46 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
47 c
->prog_data
.total_grf
= c
->last_tmp
;
52 static void release_tmp( struct brw_clip_compile
*c
, struct brw_reg tmp
)
54 if (tmp
.nr
== c
->last_tmp
-1)
59 static struct brw_reg
make_plane_ud(GLuint x
, GLuint y
, GLuint z
, GLuint w
)
61 return brw_imm_ud((w
<<24) | (z
<<16) | (y
<<8) | x
);
65 void brw_clip_init_planes( struct brw_clip_compile
*c
)
67 struct brw_compile
*p
= &c
->func
;
69 if (!c
->key
.nr_userclip
) {
70 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 0), make_plane_ud( 0, 0, 0xff, 1));
71 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 1), make_plane_ud( 0, 0, 1, 1));
72 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 2), make_plane_ud( 0, 0xff, 0, 1));
73 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 3), make_plane_ud( 0, 1, 0, 1));
74 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 4), make_plane_ud(0xff, 0, 0, 1));
75 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 5), make_plane_ud( 1, 0, 0, 1));
83 /* Project 'pos' to screen space (or back again), overwrite with results:
85 void brw_clip_project_position(struct brw_clip_compile
*c
, struct brw_reg pos
)
87 struct brw_compile
*p
= &c
->func
;
91 brw_math_invert(p
, get_element(pos
, W
), get_element(pos
, W
));
93 /* value.xyz *= value.rhw
95 brw_set_access_mode(p
, BRW_ALIGN_16
);
96 brw_MUL(p
, brw_writemask(pos
, WRITEMASK_XYZ
), pos
, brw_swizzle1(pos
, W
));
97 brw_set_access_mode(p
, BRW_ALIGN_1
);
101 static void brw_clip_project_vertex( struct brw_clip_compile
*c
,
102 struct brw_indirect vert_addr
)
104 struct brw_compile
*p
= &c
->func
;
105 struct brw_reg tmp
= get_tmp(c
);
107 /* Fixup position. Extract from the original vertex and re-project
110 brw_MOV(p
, tmp
, deref_4f(vert_addr
, c
->offset
[VERT_RESULT_HPOS
]));
111 brw_clip_project_position(c
, tmp
);
112 brw_MOV(p
, deref_4f(vert_addr
, c
->header_position_offset
), tmp
);
120 /* Interpolate between two vertices and put the result into a0.0.
121 * Increment a0.0 accordingly.
123 void brw_clip_interp_vertex( struct brw_clip_compile
*c
,
124 struct brw_indirect dest_ptr
,
125 struct brw_indirect v0_ptr
, /* from */
126 struct brw_indirect v1_ptr
, /* to */
128 GLboolean force_edgeflag
)
130 struct brw_compile
*p
= &c
->func
;
131 struct brw_reg tmp
= get_tmp(c
);
134 /* Just copy the vertex header:
137 * After CLIP stage, only first 256 bits of the VUE are read
138 * back on IGDNG, so needn't change it
140 brw_copy_indirect_to_indirect(p
, dest_ptr
, v0_ptr
, 1);
142 /* Iterate over each attribute (could be done in pairs?)
144 for (i
= 0; i
< c
->nr_attrs
; i
++) {
145 GLuint delta
= i
*16 + 32;
147 if (BRW_IS_IGDNG(p
->brw
))
148 delta
= i
* 16 + 32 * 3;
150 if (delta
== c
->offset
[VERT_RESULT_EDGE
]) {
152 brw_MOV(p
, deref_4f(dest_ptr
, delta
), brw_imm_f(1));
154 brw_MOV(p
, deref_4f(dest_ptr
, delta
), deref_4f(v0_ptr
, delta
));
159 * New = attr0 + t*attr1 - t*attr0
162 vec4(brw_null_reg()),
163 deref_4f(v1_ptr
, delta
),
168 negate(deref_4f(v0_ptr
, delta
)),
172 deref_4f(dest_ptr
, delta
),
173 deref_4f(v0_ptr
, delta
),
179 GLuint delta
= i
*16 + 32;
181 if (BRW_IS_IGDNG(p
->brw
))
182 delta
= i
* 16 + 32 * 3;
184 brw_MOV(p
, deref_4f(dest_ptr
, delta
), brw_imm_f(0));
189 /* Recreate the projected (NDC) coordinate in the new vertex
192 brw_clip_project_vertex(c
, dest_ptr
);
200 void brw_clip_emit_vue(struct brw_clip_compile
*c
,
201 struct brw_indirect vert
,
206 struct brw_compile
*p
= &c
->func
;
207 GLuint start
= c
->last_mrf
;
211 assert(!(allocate
&& eot
));
213 /* Cycle through mrf regs - probably futile as we have to wait for
214 * the allocation response anyway. Also, the order this function
215 * is invoked doesn't correspond to the order the instructions will
216 * be executed, so it won't have any effect in many cases.
219 if (start
+ c
->nr_regs
+ 1 >= MAX_MRF
)
222 c
->last_mrf
= start
+ c
->nr_regs
+ 1;
225 /* Copy the vertex from vertn into m1..mN+1:
227 brw_copy_from_indirect(p
, brw_message_reg(start
+1), vert
, c
->nr_regs
);
229 /* Overwrite PrimType and PrimStart in the message header, for
230 * each vertex in turn:
232 brw_MOV(p
, get_element_ud(c
->reg
.R0
, 2), brw_imm_ud(header
));
235 /* Send each vertex as a seperate write to the urb. This
236 * is different to the concept in brw_sf_emit.c, where
237 * subsequent writes are used to build up a single urb
238 * entry. Each of these writes instantiates a seperate
239 * urb entry - (I think... what about 'allocate'?)
242 allocate
? c
->reg
.R0
: retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
247 c
->nr_regs
+ 1, /* msg length */
248 allocate
? 1 : 0, /* response_length */
250 1, /* writes_complete */
252 BRW_URB_SWIZZLE_NONE
);
257 void brw_clip_kill_thread(struct brw_clip_compile
*c
)
259 struct brw_compile
*p
= &c
->func
;
262 /* Send an empty message to kill the thread and release any
263 * allocated urb entry:
266 retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
272 0, /* response len */
274 1, /* writes complete */
276 BRW_URB_SWIZZLE_NONE
);
282 struct brw_reg
brw_clip_plane0_address( struct brw_clip_compile
*c
)
284 return brw_address(c
->reg
.fixed_planes
);
288 struct brw_reg
brw_clip_plane_stride( struct brw_clip_compile
*c
)
290 if (c
->key
.nr_userclip
) {
291 return brw_imm_uw(16);
294 return brw_imm_uw(4);
299 /* If flatshading, distribute color from provoking vertex prior to
302 void brw_clip_copy_colors( struct brw_clip_compile
*c
,
303 GLuint to
, GLuint from
)
305 struct brw_compile
*p
= &c
->func
;
307 if (c
->offset
[VERT_RESULT_COL0
])
309 byte_offset(c
->reg
.vertex
[to
], c
->offset
[VERT_RESULT_COL0
]),
310 byte_offset(c
->reg
.vertex
[from
], c
->offset
[VERT_RESULT_COL0
]));
312 if (c
->offset
[VERT_RESULT_COL1
])
314 byte_offset(c
->reg
.vertex
[to
], c
->offset
[VERT_RESULT_COL1
]),
315 byte_offset(c
->reg
.vertex
[from
], c
->offset
[VERT_RESULT_COL1
]));
317 if (c
->offset
[VERT_RESULT_BFC0
])
319 byte_offset(c
->reg
.vertex
[to
], c
->offset
[VERT_RESULT_BFC0
]),
320 byte_offset(c
->reg
.vertex
[from
], c
->offset
[VERT_RESULT_BFC0
]));
322 if (c
->offset
[VERT_RESULT_BFC1
])
324 byte_offset(c
->reg
.vertex
[to
], c
->offset
[VERT_RESULT_BFC1
]),
325 byte_offset(c
->reg
.vertex
[from
], c
->offset
[VERT_RESULT_BFC1
]));
330 void brw_clip_init_clipmask( struct brw_clip_compile
*c
)
332 struct brw_compile
*p
= &c
->func
;
333 struct brw_reg incoming
= get_element_ud(c
->reg
.R0
, 2);
335 /* Shift so that lowest outcode bit is rightmost:
337 brw_SHR(p
, c
->reg
.planemask
, incoming
, brw_imm_ud(26));
339 if (c
->key
.nr_userclip
) {
340 struct brw_reg tmp
= retype(vec1(get_tmp(c
)), BRW_REGISTER_TYPE_UD
);
342 /* Rearrange userclip outcodes so that they come directly after
343 * the fixed plane bits.
345 brw_AND(p
, tmp
, incoming
, brw_imm_ud(0x3f<<14));
346 brw_SHR(p
, tmp
, tmp
, brw_imm_ud(8));
347 brw_OR(p
, c
->reg
.planemask
, c
->reg
.planemask
, tmp
);
353 void brw_clip_ff_sync(struct brw_clip_compile
*c
)
355 if (c
->need_ff_sync
) {
356 struct brw_compile
*p
= &c
->func
;
357 struct brw_instruction
*need_ff_sync
;
359 brw_set_conditionalmod(p
, BRW_CONDITIONAL_Z
);
360 brw_AND(p
, brw_null_reg(), c
->reg
.ff_sync
, brw_imm_ud(0x1));
361 need_ff_sync
= brw_IF(p
, BRW_EXECUTE_1
);
363 brw_OR(p
, c
->reg
.ff_sync
, c
->reg
.ff_sync
, brw_imm_ud(0x1));
371 1, /* response length */
373 1, /* write compelete */
375 BRW_URB_SWIZZLE_NONE
);
377 brw_ENDIF(p
, need_ff_sync
);
378 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
382 void brw_clip_init_ff_sync(struct brw_clip_compile
*c
)
384 if (c
->need_ff_sync
) {
385 struct brw_compile
*p
= &c
->func
;
387 brw_MOV(p
, c
->reg
.ff_sync
, brw_imm_ud(0));