2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_defines.h"
41 struct brw_reg
get_tmp( struct brw_clip_compile
*c
)
43 struct brw_reg tmp
= brw_vec4_grf(c
->last_tmp
, 0);
45 if (++c
->last_tmp
> c
->prog_data
.total_grf
)
46 c
->prog_data
.total_grf
= c
->last_tmp
;
51 static void release_tmp( struct brw_clip_compile
*c
, struct brw_reg tmp
)
53 if (tmp
.nr
== c
->last_tmp
-1)
58 static struct brw_reg
make_plane_ud(GLuint x
, GLuint y
, GLuint z
, GLuint w
)
60 return brw_imm_ud((w
<<24) | (z
<<16) | (y
<<8) | x
);
64 void brw_clip_init_planes( struct brw_clip_compile
*c
)
66 struct brw_compile
*p
= &c
->func
;
68 if (!c
->key
.nr_userclip
) {
69 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 0), make_plane_ud( 0, 0, 0xff, 1));
70 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 1), make_plane_ud( 0, 0, 1, 1));
71 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 2), make_plane_ud( 0, 0xff, 0, 1));
72 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 3), make_plane_ud( 0, 1, 0, 1));
73 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 4), make_plane_ud(0xff, 0, 0, 1));
74 brw_MOV(p
, get_element_ud(c
->reg
.fixed_planes
, 5), make_plane_ud( 1, 0, 0, 1));
82 /* Project 'pos' to screen space (or back again), overwrite with results:
84 void brw_clip_project_position(struct brw_clip_compile
*c
, struct brw_reg pos
)
86 struct brw_compile
*p
= &c
->func
;
90 brw_math_invert(p
, get_element(pos
, W
), get_element(pos
, W
));
92 /* value.xyz *= value.rhw
94 brw_set_access_mode(p
, BRW_ALIGN_16
);
95 brw_MUL(p
, brw_writemask(pos
, BRW_WRITEMASK_XYZ
), pos
, brw_swizzle1(pos
, W
));
96 brw_set_access_mode(p
, BRW_ALIGN_1
);
100 static void brw_clip_project_vertex( struct brw_clip_compile
*c
,
101 struct brw_indirect vert_addr
)
103 struct brw_compile
*p
= &c
->func
;
104 struct brw_reg tmp
= get_tmp(c
);
106 /* Fixup position. Extract from the original vertex and re-project
109 brw_MOV(p
, tmp
, deref_4f(vert_addr
, c
->offset_hpos
));
110 brw_clip_project_position(c
, tmp
);
111 brw_MOV(p
, deref_4f(vert_addr
, c
->header_position_offset
), tmp
);
119 /* Interpolate between two vertices and put the result into a0.0.
120 * Increment a0.0 accordingly.
122 void brw_clip_interp_vertex( struct brw_clip_compile
*c
,
123 struct brw_indirect dest_ptr
,
124 struct brw_indirect v0_ptr
, /* from */
125 struct brw_indirect v1_ptr
, /* to */
127 GLboolean force_edgeflag
)
129 struct brw_compile
*p
= &c
->func
;
130 struct brw_reg tmp
= get_tmp(c
);
133 /* Just copy the vertex header:
136 * After CLIP stage, only first 256 bits of the VUE are read
137 * back on IGDNG, so needn't change it
139 brw_copy_indirect_to_indirect(p
, dest_ptr
, v0_ptr
, 1);
141 /* Iterate over each attribute (could be done in pairs?)
143 for (i
= 0; i
< c
->key
.nr_attrs
; i
++) {
144 GLuint delta
= i
*16 + 32;
146 if (c
->chipset
.is_igdng
)
147 delta
= i
* 16 + 32 * 3;
149 if (delta
== c
->offset_edgeflag
) {
151 brw_MOV(p
, deref_4f(dest_ptr
, delta
), brw_imm_f(1));
153 brw_MOV(p
, deref_4f(dest_ptr
, delta
), deref_4f(v0_ptr
, delta
));
158 * New = attr0 + t*attr1 - t*attr0
161 vec4(brw_null_reg()),
162 deref_4f(v1_ptr
, delta
),
167 negate(deref_4f(v0_ptr
, delta
)),
171 deref_4f(dest_ptr
, delta
),
172 deref_4f(v0_ptr
, delta
),
178 GLuint delta
= i
*16 + 32;
180 if (c
->chipset
.is_igdng
)
181 delta
= i
* 16 + 32 * 3;
183 brw_MOV(p
, deref_4f(dest_ptr
, delta
), brw_imm_f(0));
188 /* Recreate the projected (NDC) coordinate in the new vertex
191 brw_clip_project_vertex(c
, dest_ptr
);
199 void brw_clip_emit_vue(struct brw_clip_compile
*c
,
200 struct brw_indirect vert
,
205 struct brw_compile
*p
= &c
->func
;
206 GLuint start
= c
->last_mrf
;
210 assert(!(allocate
&& eot
));
212 /* Cycle through mrf regs - probably futile as we have to wait for
213 * the allocation response anyway. Also, the order this function
214 * is invoked doesn't correspond to the order the instructions will
215 * be executed, so it won't have any effect in many cases.
218 if (start
+ c
->nr_regs
+ 1 >= MAX_MRF
)
221 c
->last_mrf
= start
+ c
->nr_regs
+ 1;
224 /* Copy the vertex from vertn into m1..mN+1:
226 brw_copy_from_indirect(p
, brw_message_reg(start
+1), vert
, c
->nr_regs
);
228 /* Overwrite PrimType and PrimStart in the message header, for
229 * each vertex in turn:
231 brw_MOV(p
, get_element_ud(c
->reg
.R0
, 2), brw_imm_ud(header
));
234 /* Send each vertex as a seperate write to the urb. This
235 * is different to the concept in brw_sf_emit.c, where
236 * subsequent writes are used to build up a single urb
237 * entry. Each of these writes instantiates a seperate
238 * urb entry - (I think... what about 'allocate'?)
241 allocate
? c
->reg
.R0
: retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
246 c
->nr_regs
+ 1, /* msg length */
247 allocate
? 1 : 0, /* response_length */
249 1, /* writes_complete */
251 BRW_URB_SWIZZLE_NONE
);
256 void brw_clip_kill_thread(struct brw_clip_compile
*c
)
258 struct brw_compile
*p
= &c
->func
;
261 /* Send an empty message to kill the thread and release any
262 * allocated urb entry:
265 retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
271 0, /* response len */
273 1, /* writes complete */
275 BRW_URB_SWIZZLE_NONE
);
281 struct brw_reg
brw_clip_plane0_address( struct brw_clip_compile
*c
)
283 return brw_address(c
->reg
.fixed_planes
);
287 struct brw_reg
brw_clip_plane_stride( struct brw_clip_compile
*c
)
289 if (c
->key
.nr_userclip
) {
290 return brw_imm_uw(16);
293 return brw_imm_uw(4);
298 /* If flatshading, distribute color from provoking vertex prior to
301 void brw_clip_copy_colors( struct brw_clip_compile
*c
,
302 GLuint to
, GLuint from
)
304 struct brw_compile
*p
= &c
->func
;
306 if (c
->offset_color0
)
308 byte_offset(c
->reg
.vertex
[to
], c
->offset_color0
),
309 byte_offset(c
->reg
.vertex
[from
], c
->offset_color0
));
311 if (c
->offset_color1
)
313 byte_offset(c
->reg
.vertex
[to
], c
->offset_color1
),
314 byte_offset(c
->reg
.vertex
[from
], c
->offset_color1
));
318 byte_offset(c
->reg
.vertex
[to
], c
->offset_bfc0
),
319 byte_offset(c
->reg
.vertex
[from
], c
->offset_bfc0
));
323 byte_offset(c
->reg
.vertex
[to
], c
->offset_bfc1
),
324 byte_offset(c
->reg
.vertex
[from
], c
->offset_bfc1
));
329 void brw_clip_init_clipmask( struct brw_clip_compile
*c
)
331 struct brw_compile
*p
= &c
->func
;
332 struct brw_reg incoming
= get_element_ud(c
->reg
.R0
, 2);
334 /* Shift so that lowest outcode bit is rightmost:
336 brw_SHR(p
, c
->reg
.planemask
, incoming
, brw_imm_ud(26));
338 if (c
->key
.nr_userclip
) {
339 struct brw_reg tmp
= retype(vec1(get_tmp(c
)), BRW_REGISTER_TYPE_UD
);
341 /* Rearrange userclip outcodes so that they come directly after
342 * the fixed plane bits.
344 brw_AND(p
, tmp
, incoming
, brw_imm_ud(0x3f<<14));
345 brw_SHR(p
, tmp
, tmp
, brw_imm_ud(8));
346 brw_OR(p
, c
->reg
.planemask
, c
->reg
.planemask
, tmp
);
352 void brw_clip_ff_sync(struct brw_clip_compile
*c
)
354 if (c
->need_ff_sync
) {
355 struct brw_compile
*p
= &c
->func
;
356 struct brw_instruction
*need_ff_sync
;
358 brw_set_conditionalmod(p
, BRW_CONDITIONAL_Z
);
359 brw_AND(p
, brw_null_reg(), c
->reg
.ff_sync
, brw_imm_ud(0x1));
360 need_ff_sync
= brw_IF(p
, BRW_EXECUTE_1
);
362 brw_OR(p
, c
->reg
.ff_sync
, c
->reg
.ff_sync
, brw_imm_ud(0x1));
370 1, /* response length */
372 1, /* write compelete */
374 BRW_URB_SWIZZLE_NONE
);
376 brw_ENDIF(p
, need_ff_sync
);
377 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
381 void brw_clip_init_ff_sync(struct brw_clip_compile
*c
)
383 if (c
->need_ff_sync
) {
384 struct brw_compile
*p
= &c
->func
;
386 brw_MOV(p
, c
->reg
.ff_sync
, brw_imm_ud(0));