i965g: still working on compilation
[mesa.git] / src / gallium / drivers / i965 / brw_context.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include "brw_structs.h"
37 #include "brw_winsys.h"
38 #include "brw_reg.h"
39 #include "pipe/p_state.h"
40 #include "pipe/p_context.h"
41 #include "tgsi/tgsi_scan.h"
42
43
44 /* Glossary:
45 *
46 * URB - uniform resource buffer. A mid-sized buffer which is
47 * partitioned between the fixed function units and used for passing
48 * values (vertices, primitives, constants) between them.
49 *
50 * CURBE - constant URB entry. An urb region (entry) used to hold
51 * constant values which the fixed function units can be instructed to
52 * preload into the GRF when spawning a thread.
53 *
54 * VUE - vertex URB entry. An urb entry holding a vertex and usually
55 * a vertex header. The header contains control information and
56 * things like primitive type, Begin/end flags and clip codes.
57 *
58 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
59 * unit holding rasterization and interpolation parameters.
60 *
61 * GRF - general register file. One of several register files
62 * addressable by programmed threads. The inputs (r0, payload, curbe,
63 * urb) of the thread are preloaded to this area before the thread is
64 * spawned. The registers are individually 8 dwords wide and suitable
65 * for general usage. Registers holding thread input values are not
66 * special and may be overwritten.
67 *
68 * MRF - message register file. Threads communicate (and terminate)
69 * by sending messages. Message parameters are placed in contiguous
70 * MRF registers. All program output is via these messages. URB
71 * entries are populated by sending a message to the shared URB
72 * function containing the new data, together with a control word,
73 * often an unmodified copy of R0.
74 *
75 * R0 - GRF register 0. Typically holds control information used when
76 * sending messages to other threads.
77 *
78 * EU or GEN4 EU: The name of the programmable subsystem of the
79 * i965 hardware. Threads are executed by the EU, the registers
80 * described above are part of the EU architecture.
81 *
82 * Fixed function units:
83 *
84 * CS - Command streamer. Notional first unit, little software
85 * interaction. Holds the URB entries used for constant data, ie the
86 * CURBEs.
87 *
88 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
89 * this unit is responsible for pulling vertices out of vertex buffers
90 * in vram and injecting them into the processing pipe as VUEs. If
91 * enabled, it first passes them to a VS thread which is a good place
92 * for the driver to implement any active vertex shader.
93 *
94 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
95 * enabled, incoming strips etc are passed to GS threads in individual
96 * line/triangle/point units. The GS thread may perform arbitary
97 * computation and emit whatever primtives with whatever vertices it
98 * chooses. This makes GS an excellent place to implement GL's
99 * unfilled polygon modes, though of course it is capable of much
100 * more. Additionally, GS is used to translate away primitives not
101 * handled by latter units, including Quads and Lineloops.
102 *
103 * CS - Clipper. Mesa's clipping algorithms are imported to run on
104 * this unit. The fixed function part performs cliptesting against
105 * the 6 fixed clipplanes and makes descisions on whether or not the
106 * incoming primitive needs to be passed to a thread for clipping.
107 * User clip planes are handled via cooperation with the VS thread.
108 *
109 * SF - Strips Fans or Setup: Triangles are prepared for
110 * rasterization. Interpolation coefficients are calculated.
111 * Flatshading and two-side lighting usually performed here.
112 *
113 * WM - Windower. Interpolation of vertex attributes performed here.
114 * Fragment shader implemented here. SIMD aspects of EU taken full
115 * advantage of, as pixels are processed in blocks of 16.
116 *
117 * CC - Color Calculator. No EU threads associated with this unit.
118 * Handles blending and (presumably) depth and stencil testing.
119 */
120
121 #define BRW_MAX_CURBE (32*16)
122
123 struct brw_context;
124
125 struct brw_depth_stencil_state {
126 //struct pipe_depth_stencil_alpha_state templ; /* for draw module */
127
128 /* Precalculated hardware state:
129 */
130 struct brw_cc0 cc0;
131 struct brw_cc1 cc1;
132 struct brw_cc2 cc2;
133 struct brw_cc3 cc3;
134 struct brw_cc7 cc7;
135 };
136
137
138 struct brw_blend_state {
139 //struct pipe_depth_stencil_alpha_state templ; /* for draw module */
140
141 /* Precalculated hardware state:
142 */
143 struct brw_cc2 cc2;
144 struct brw_cc3 cc3;
145 struct brw_cc5 cc5;
146 struct brw_cc6 cc6;
147 };
148
149
150 struct brw_rasterizer_state;
151
152
153 struct brw_vertex_shader {
154 const struct tgsi_token *tokens;
155 struct tgsi_shader_info info;
156
157 unsigned id;
158 struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */
159 GLboolean use_const_buffer;
160 };
161
162
163 struct brw_fragment_shader {
164 const struct tgsi_token *tokens;
165 struct tgsi_shader_info info;
166
167 GLboolean isGLSL;
168
169 unsigned id;
170 struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */
171 GLboolean use_const_buffer;
172 };
173
174
175
176 #define PIPE_NEW_DEPTH_STENCIL_ALPHA 0x1
177 #define PIPE_NEW_RAST 0x2
178 #define PIPE_NEW_BLEND 0x4
179 #define PIPE_NEW_VIEWPORT 0x8
180 #define PIPE_NEW_SAMPLERS 0x10
181 #define PIPE_NEW_VERTEX_BUFFER 0x20
182 #define PIPE_NEW_VERTEX_ELEMENT 0x40
183 #define PIPE_NEW_FRAGMENT_SHADER 0x80
184 #define PIPE_NEW_VERTEX_SHADER 0x100
185 #define PIPE_NEW_FRAGMENT_CONSTANTS 0x200
186 #define PIPE_NEW_VERTEX_CONSTANTS 0x400
187 #define PIPE_NEW_CLIP 0x800
188 #define PIPE_NEW_INDEX_BUFFER 0x1000
189 #define PIPE_NEW_INDEX_RANGE 0x2000
190 #define PIPE_NEW_BLEND_COLOR 0x4000
191 #define PIPE_NEW_POLYGON_STIPPLE 0x8000
192 #define PIPE_NEW_FRAMEBUFFER_DIMENSIONS 0x10000
193 #define PIPE_NEW_DEPTH_BUFFER 0x20000
194 #define PIPE_NEW_COLOR_BUFFERS 0x40000
195 #define PIPE_NEW_QUERY 0x80000
196 #define PIPE_NEW_SCISSOR 0x100000
197
198
199
200 #define BRW_NEW_URB_FENCE 0x1
201 #define BRW_NEW_FRAGMENT_PROGRAM 0x2
202 #define BRW_NEW_VERTEX_PROGRAM 0x4
203 #define BRW_NEW_INPUT_DIMENSIONS 0x8
204 #define BRW_NEW_CURBE_OFFSETS 0x10
205 #define BRW_NEW_REDUCED_PRIMITIVE 0x20
206 #define BRW_NEW_PRIMITIVE 0x40
207 #define BRW_NEW_CONTEXT 0x80
208 #define BRW_NEW_WM_INPUT_DIMENSIONS 0x100
209 #define BRW_NEW_PSP 0x800
210 #define BRW_NEW_WM_SURFACES 0x1000
211 #define BRW_NEW_xxx 0x2000 /* was FENCE */
212 #define BRW_NEW_INDICES 0x4000
213 #define BRW_NEW_VERTICES 0x8000
214 /**
215 * Used for any batch entry with a relocated pointer that will be used
216 * by any 3D rendering. Need to re-emit these fresh in each
217 * batchbuffer as the referenced buffers may be relocated in the
218 * meantime.
219 */
220 #define BRW_NEW_BATCH 0x10000
221 #define BRW_NEW_NR_WM_SURFACES 0x40000
222 #define BRW_NEW_NR_VS_SURFACES 0x80000
223 #define BRW_NEW_INDEX_BUFFER 0x100000
224
225 struct brw_state_flags {
226 /** State update flags signalled by mesa internals */
227 GLuint mesa;
228 /**
229 * State update flags signalled as the result of brw_tracked_state updates
230 */
231 GLuint brw;
232 /** State update flags signalled by brw_state_cache.c searches */
233 GLuint cache;
234 };
235
236
237
238 /* Data about a particular attempt to compile a program. Note that
239 * there can be many of these, each in a different GL state
240 * corresponding to a different brw_wm_prog_key struct, with different
241 * compiled programs:
242 */
243 struct brw_wm_prog_data {
244 GLuint curb_read_length;
245 GLuint urb_read_length;
246
247 GLuint first_curbe_grf;
248 GLuint total_grf;
249 GLuint total_scratch;
250
251 GLuint nr_params; /**< number of float params/constants */
252 GLboolean error;
253
254 /* Pointer to tracked values (only valid once
255 * _mesa_load_state_parameters has been called at runtime).
256 */
257 const GLfloat *param[BRW_MAX_CURBE];
258 };
259
260 struct brw_sf_prog_data {
261 GLuint urb_read_length;
262 GLuint total_grf;
263
264 /* Each vertex may have upto 12 attributes, 4 components each,
265 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
266 * rows.
267 *
268 * Actually we use 4 for each, so call it 12 rows.
269 */
270 GLuint urb_entry_size;
271 };
272
273
274 struct brw_clip_prog_data;
275
276 struct brw_gs_prog_data {
277 GLuint urb_read_length;
278 GLuint total_grf;
279 };
280
281 struct brw_vs_prog_data {
282 GLuint curb_read_length;
283 GLuint urb_read_length;
284 GLuint total_grf;
285
286 GLuint nr_outputs;
287 GLuint nr_inputs;
288
289 GLuint nr_params; /**< number of TGSI_FILE_CONSTANT's */
290
291 GLboolean copy_edgeflag;
292
293 /* Used for calculating urb partitions:
294 */
295 GLuint urb_entry_size;
296 };
297
298
299 /* Size == 0 if output either not written, or always [0,0,0,1]
300 */
301 struct brw_vs_ouput_sizes {
302 GLubyte output_size[PIPE_MAX_SHADER_OUTPUTS];
303 };
304
305
306 /** Number of texture sampler units */
307 #define BRW_MAX_TEX_UNIT 16
308
309 /**
310 * Size of our surface binding table for the WM.
311 * This contains pointers to the drawing surfaces and current texture
312 * objects and shader constant buffers (+2).
313 */
314 #define BRW_WM_MAX_SURF (PIPE_MAX_COLOR_BUFS + BRW_MAX_TEX_UNIT + 1)
315
316 /**
317 * Helpers to convert drawing buffers, textures and constant buffers
318 * to surface binding table indexes, for WM.
319 */
320 #define SURF_INDEX_DRAW(d) (d)
321 #define SURF_INDEX_FRAG_CONST_BUFFER (PIPE_MAX_COLOR_BUFS)
322 #define SURF_INDEX_TEXTURE(t) (PIPE_MAX_COLOR_BUFS + 1 + (t))
323
324 /**
325 * Size of surface binding table for the VS.
326 * Only one constant buffer for now.
327 */
328 #define BRW_VS_MAX_SURF 1
329
330 /**
331 * Only a VS constant buffer
332 */
333 #define SURF_INDEX_VERT_CONST_BUFFER 0
334
335
336 enum brw_cache_id {
337 BRW_CC_VP,
338 BRW_CC_UNIT,
339 BRW_WM_PROG,
340 BRW_SAMPLER_DEFAULT_COLOR,
341 BRW_SAMPLER,
342 BRW_WM_UNIT,
343 BRW_SF_PROG,
344 BRW_SF_VP,
345 BRW_SF_UNIT,
346 BRW_VS_UNIT,
347 BRW_VS_PROG,
348 BRW_GS_UNIT,
349 BRW_GS_PROG,
350 BRW_CLIP_VP,
351 BRW_CLIP_UNIT,
352 BRW_CLIP_PROG,
353 BRW_SS_SURFACE,
354 BRW_SS_SURF_BIND,
355
356 BRW_MAX_CACHE
357 };
358
359 struct brw_cache_item {
360 /**
361 * Effectively part of the key, cache_id identifies what kind of state
362 * buffer is involved, and also which brw->state.dirty.cache flag should
363 * be set when this cache item is chosen.
364 */
365 enum brw_cache_id cache_id;
366 /** 32-bit hash of the key data */
367 GLuint hash;
368 GLuint key_size; /* for variable-sized keys */
369 const void *key;
370 struct brw_winsys_buffer **reloc_bufs;
371 GLuint nr_reloc_bufs;
372
373 struct brw_winsys_buffer *bo;
374 GLuint data_size;
375
376 struct brw_cache_item *next;
377 };
378
379
380
381 struct brw_cache {
382 struct brw_context *brw;
383 struct brw_winsys_screen *sws;
384
385 struct brw_cache_item **items;
386 GLuint size, n_items;
387
388 GLuint key_size[BRW_MAX_CACHE]; /* for fixed-size keys */
389 GLuint aux_size[BRW_MAX_CACHE];
390 char *name[BRW_MAX_CACHE];
391
392
393 /* Record of the last BOs chosen for each cache_id. Used to set
394 * brw->state.dirty.cache when a new cache item is chosen.
395 */
396 struct brw_winsys_buffer *last_bo[BRW_MAX_CACHE];
397 };
398
399
400 struct brw_tracked_state {
401 struct brw_state_flags dirty;
402 int (*prepare)( struct brw_context *brw );
403 int (*emit)( struct brw_context *brw );
404 };
405
406 /* Flags for brw->state.cache.
407 */
408 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
409 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
410 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
411 #define CACHE_NEW_SAMPLER_DEFAULT_COLOR (1<<BRW_SAMPLER_DEFAULT_COLOR)
412 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
413 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
414 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
415 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
416 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
417 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
418 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
419 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
420 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
421 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
422 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
423 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
424 #define CACHE_NEW_SURFACE (1<<BRW_SS_SURFACE)
425 #define CACHE_NEW_SURF_BIND (1<<BRW_SS_SURF_BIND)
426
427 struct brw_cached_batch_item {
428 struct header *header;
429 GLuint sz;
430 struct brw_cached_batch_item *next;
431 };
432
433
434
435 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
436 * be easier if C allowed arrays of packed elements?
437 */
438 #define VS_INPUT_BITMASK_DWORDS ((PIPE_MAX_SHADER_INPUTS+31)/32)
439
440
441
442
443 struct brw_vertex_info {
444 GLuint sizes[VS_INPUT_BITMASK_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */
445 };
446
447
448 struct brw_query_object {
449 /** Doubly linked list of active query objects in the context. */
450 struct brw_query_object *prev, *next;
451
452 /** Last query BO associated with this query. */
453 struct brw_winsys_buffer *bo;
454 /** First index in bo with query data for this object. */
455 int first_index;
456 /** Last index in bo with query data for this object. */
457 int last_index;
458
459 /* Total count of pixels from previous BOs */
460 uint64_t result;
461 };
462
463
464 /**
465 * brw_context is derived from pipe_context
466 */
467 struct brw_context
468 {
469 struct pipe_context base;
470 struct brw_chipset chipset;
471
472 struct brw_screen *brw_screen;
473 struct brw_winsys_screen *sws;
474
475 struct brw_batchbuffer *batch;
476
477 GLuint primitive;
478 GLuint reduced_primitive;
479
480 /* Active state from the state tracker:
481 */
482 struct {
483 struct brw_vertex_shader *vertex_shader;
484 struct brw_fragment_shader *fragment_shader;
485 const struct brw_blend_state *blend;
486 const struct brw_rasterizer_state *rast;
487 const struct brw_depth_stencil_state *zstencil;
488
489 const struct pipe_texture *texture[PIPE_MAX_SAMPLERS];
490 const struct pipe_sampler *sampler[PIPE_MAX_SAMPLERS];
491 unsigned num_textures;
492 unsigned num_samplers;
493
494
495 struct pipe_vertex_element vertex_element[PIPE_MAX_ATTRIBS];
496 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
497 unsigned num_vertex_elements;
498 unsigned num_vertex_buffers;
499
500 struct pipe_scissor_state scissor;
501 struct pipe_framebuffer_state fb;
502 struct pipe_viewport_state vp;
503 struct pipe_clip_state ucp;
504 struct pipe_buffer *vertex_constants;
505 struct pipe_buffer *fragment_constants;
506
507 struct pipe_viewport_state viewport;
508 struct brw_blend_constant_color bcc;
509 struct brw_polygon_stipple bps;
510
511
512
513 /**
514 * Index buffer for this draw_prims call.
515 *
516 * Updates are signaled by PIPE_NEW_INDEX_BUFFER.
517 */
518 struct pipe_buffer *index_buffer;
519 unsigned index_size;
520
521 /* Updates are signalled by PIPE_NEW_INDEX_RANGE:
522 */
523 unsigned min_index;
524 unsigned max_index;
525
526 } curr;
527
528 struct {
529 struct brw_state_flags dirty;
530
531 /**
532 * List of buffers accumulated in brw_validate_state to receive
533 * dri_bo_check_aperture treatment before exec, so we can know if we
534 * should flush the batch and try again before emitting primitives.
535 *
536 * This can be a fixed number as we only have a limited number of
537 * objects referenced from the batchbuffer in a primitive emit,
538 * consisting of the vertex buffers, pipelined state pointers,
539 * the CURBE, the depth buffer, and a query BO.
540 */
541 struct brw_winsys_buffer *validated_bos[PIPE_MAX_SHADER_INPUTS + 16];
542 int validated_bo_count;
543 } state;
544
545 struct brw_cache cache; /** non-surface items */
546 struct brw_cache surface_cache; /* surface items */
547 struct brw_cached_batch_item *cached_batch_items;
548
549 struct {
550 struct u_upload_mgr *upload_vertex;
551 struct u_upload_mgr *upload_index;
552
553 /* Information on uploaded vertex buffers:
554 */
555 struct {
556 unsigned stride; /* in bytes between successive vertices */
557 unsigned offset; /* in bytes, of first vertex in bo */
558 unsigned vertex_count; /* count of valid vertices which may be accessed */
559 struct brw_winsys_buffer *bo;
560 } vb[PIPE_MAX_ATTRIBS];
561
562 struct {
563 } ve[PIPE_MAX_ATTRIBS];
564
565 unsigned nr_vb; /* currently the same as curr.num_vertex_buffers */
566 unsigned nr_ve; /* currently the same as curr.num_vertex_elements */
567 } vb;
568
569 struct {
570 /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */
571 struct brw_winsys_buffer *bo;
572 unsigned int offset;
573 unsigned int size;
574 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
575 * avoid re-uploading the IB packet over and over if we're actually
576 * referencing the same index buffer.
577 */
578 unsigned int start_vertex_offset;
579 } ib;
580
581
582 /* BRW_NEW_URB_ALLOCATIONS:
583 */
584 struct {
585 GLuint vsize; /* vertex size plus header in urb registers */
586 GLuint csize; /* constant buffer size in urb registers */
587 GLuint sfsize; /* setup data size in urb registers */
588
589 GLboolean constrained;
590
591 GLuint nr_vs_entries;
592 GLuint nr_gs_entries;
593 GLuint nr_clip_entries;
594 GLuint nr_sf_entries;
595 GLuint nr_cs_entries;
596
597 GLuint vs_start;
598 GLuint gs_start;
599 GLuint clip_start;
600 GLuint sf_start;
601 GLuint cs_start;
602 } urb;
603
604
605 /* BRW_NEW_CURBE_OFFSETS:
606 */
607 struct {
608 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
609 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
610 GLuint clip_start;
611 GLuint clip_size;
612 GLuint vs_start;
613 GLuint vs_size;
614 GLuint total_size;
615
616 struct brw_winsys_buffer *curbe_bo;
617 /** Offset within curbe_bo of space for current curbe entry */
618 GLuint curbe_offset;
619 /** Offset within curbe_bo of space for next curbe entry */
620 GLuint curbe_next_offset;
621
622 GLfloat *last_buf;
623 GLuint last_bufsz;
624 /**
625 * Whether we should create a new bo instead of reusing the old one
626 * (if we just dispatch the batch pointing at the old one.
627 */
628 GLboolean need_new_bo;
629 } curbe;
630
631 struct {
632 struct brw_vs_prog_data *prog_data;
633
634 struct brw_winsys_buffer *prog_bo;
635 struct brw_winsys_buffer *state_bo;
636
637 /** Binding table of pointers to surf_bo entries */
638 struct brw_winsys_buffer *bind_bo;
639 struct brw_winsys_buffer *surf_bo[BRW_VS_MAX_SURF];
640 GLuint nr_surfaces;
641 } vs;
642
643 struct {
644 struct brw_gs_prog_data *prog_data;
645
646 GLboolean prog_active;
647 struct brw_winsys_buffer *prog_bo;
648 struct brw_winsys_buffer *state_bo;
649 } gs;
650
651 struct {
652 struct brw_clip_prog_data *prog_data;
653
654 struct brw_winsys_buffer *prog_bo;
655 struct brw_winsys_buffer *state_bo;
656 struct brw_winsys_buffer *vp_bo;
657 } clip;
658
659
660 struct {
661 struct brw_sf_prog_data *prog_data;
662
663 struct brw_winsys_buffer *prog_bo;
664 struct brw_winsys_buffer *state_bo;
665 struct brw_winsys_buffer *vp_bo;
666 } sf;
667
668 struct {
669 struct brw_wm_prog_data *prog_data;
670 struct brw_wm_compile *compile_data;
671
672 /** Input sizes, calculated from active vertex program.
673 * One bit per fragment program input attribute.
674 */
675 //GLbitfield input_size_masks[4];
676
677 /** Array of surface default colors (texture border color) */
678 struct brw_winsys_buffer *sdc_bo[BRW_MAX_TEX_UNIT];
679
680 GLuint render_surf;
681 GLuint nr_surfaces;
682
683 GLuint max_threads;
684 struct brw_winsys_buffer *scratch_bo;
685
686 GLuint sampler_count;
687 struct brw_winsys_buffer *sampler_bo;
688
689 /** Binding table of pointers to surf_bo entries */
690 struct brw_winsys_buffer *bind_bo;
691 struct brw_winsys_buffer *surf_bo[PIPE_MAX_COLOR_BUFS];
692
693 struct brw_winsys_buffer *prog_bo;
694 struct brw_winsys_buffer *state_bo;
695 } wm;
696
697
698 struct {
699 struct brw_winsys_buffer *prog_bo;
700 struct brw_winsys_buffer *state_bo;
701 struct brw_winsys_buffer *vp_bo;
702 } cc;
703
704 struct {
705 struct brw_query_object active_head;
706 struct brw_winsys_buffer *bo;
707 int index;
708 GLboolean active;
709 int stats_wm;
710 } query;
711
712 struct {
713 unsigned always_emit_state:1;
714 unsigned always_flush_batch:1;
715 unsigned force_swtnl:1;
716 unsigned no_swtnl:1;
717 } flags;
718
719 /* Used to give every program string a unique id
720 */
721 GLuint program_id;
722 };
723
724
725
726 /*======================================================================
727 * brw_queryobj.c
728 */
729 void brw_init_query(struct brw_context *brw);
730 void brw_prepare_query_begin(struct brw_context *brw);
731 void brw_emit_query_begin(struct brw_context *brw);
732 void brw_emit_query_end(struct brw_context *brw);
733
734 /*======================================================================
735 * brw_state_dump.c
736 */
737 void brw_debug_batch(struct brw_context *intel);
738
739
740 /*======================================================================
741 * brw_pipe_*.c
742 */
743 void brw_pipe_blend_init( struct brw_context *brw );
744 void brw_pipe_depth_stencil_init( struct brw_context *brw );
745 void brw_pipe_framebuffer_init( struct brw_context *brw );
746 void brw_pipe_flush_init( struct brw_context *brw );
747 void brw_pipe_misc_init( struct brw_context *brw );
748 void brw_pipe_query_init( struct brw_context *brw );
749 void brw_pipe_rast_init( struct brw_context *brw );
750 void brw_pipe_sampler_init( struct brw_context *brw );
751 void brw_pipe_shader_init( struct brw_context *brw );
752 void brw_pipe_vertex_init( struct brw_context *brw );
753
754 void brw_pipe_blend_cleanup( struct brw_context *brw );
755 void brw_pipe_depth_stencil_cleanup( struct brw_context *brw );
756 void brw_pipe_framebuffer_cleanup( struct brw_context *brw );
757 void brw_pipe_flush_cleanup( struct brw_context *brw );
758 void brw_pipe_misc_cleanup( struct brw_context *brw );
759 void brw_pipe_query_cleanup( struct brw_context *brw );
760 void brw_pipe_rast_cleanup( struct brw_context *brw );
761 void brw_pipe_sampler_cleanup( struct brw_context *brw );
762 void brw_pipe_shader_cleanup( struct brw_context *brw );
763 void brw_pipe_vertex_cleanup( struct brw_context *brw );
764
765
766 /* brw_urb.c
767 */
768 int brw_upload_urb_fence(struct brw_context *brw);
769
770 /* brw_curbe.c
771 */
772 int brw_upload_cs_urb_state(struct brw_context *brw);
773
774 /* brw_disasm.c */
775 int brw_disasm (FILE *file, struct brw_instruction *inst);
776
777 /*======================================================================
778 * Inline conversion functions. These are better-typed than the
779 * macros used previously:
780 */
781 static INLINE struct brw_context *
782 brw_context( struct pipe_context *ctx )
783 {
784 return (struct brw_context *)ctx;
785 }
786
787
788 #define BRW_IS_965(brw) ((brw)->chipset.is_965)
789 #define BRW_IS_IGDNG(brw) ((brw)->chipset.is_igdng)
790 #define BRW_IS_G4X(brw) ((brw)->chipset.is_g4x)
791
792
793 #endif
794