i965g: more files compiling
[mesa.git] / src / gallium / drivers / i965 / brw_context.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include "brw_structs.h"
37 #include "brw_winsys.h"
38 #include "brw_reg.h"
39 #include "pipe/p_state.h"
40 #include "pipe/p_context.h"
41 #include "tgsi/tgsi_scan.h"
42
43
44 /* Glossary:
45 *
46 * URB - uniform resource buffer. A mid-sized buffer which is
47 * partitioned between the fixed function units and used for passing
48 * values (vertices, primitives, constants) between them.
49 *
50 * CURBE - constant URB entry. An urb region (entry) used to hold
51 * constant values which the fixed function units can be instructed to
52 * preload into the GRF when spawning a thread.
53 *
54 * VUE - vertex URB entry. An urb entry holding a vertex and usually
55 * a vertex header. The header contains control information and
56 * things like primitive type, Begin/end flags and clip codes.
57 *
58 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
59 * unit holding rasterization and interpolation parameters.
60 *
61 * GRF - general register file. One of several register files
62 * addressable by programmed threads. The inputs (r0, payload, curbe,
63 * urb) of the thread are preloaded to this area before the thread is
64 * spawned. The registers are individually 8 dwords wide and suitable
65 * for general usage. Registers holding thread input values are not
66 * special and may be overwritten.
67 *
68 * MRF - message register file. Threads communicate (and terminate)
69 * by sending messages. Message parameters are placed in contiguous
70 * MRF registers. All program output is via these messages. URB
71 * entries are populated by sending a message to the shared URB
72 * function containing the new data, together with a control word,
73 * often an unmodified copy of R0.
74 *
75 * R0 - GRF register 0. Typically holds control information used when
76 * sending messages to other threads.
77 *
78 * EU or GEN4 EU: The name of the programmable subsystem of the
79 * i965 hardware. Threads are executed by the EU, the registers
80 * described above are part of the EU architecture.
81 *
82 * Fixed function units:
83 *
84 * CS - Command streamer. Notional first unit, little software
85 * interaction. Holds the URB entries used for constant data, ie the
86 * CURBEs.
87 *
88 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
89 * this unit is responsible for pulling vertices out of vertex buffers
90 * in vram and injecting them into the processing pipe as VUEs. If
91 * enabled, it first passes them to a VS thread which is a good place
92 * for the driver to implement any active vertex shader.
93 *
94 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
95 * enabled, incoming strips etc are passed to GS threads in individual
96 * line/triangle/point units. The GS thread may perform arbitary
97 * computation and emit whatever primtives with whatever vertices it
98 * chooses. This makes GS an excellent place to implement GL's
99 * unfilled polygon modes, though of course it is capable of much
100 * more. Additionally, GS is used to translate away primitives not
101 * handled by latter units, including Quads and Lineloops.
102 *
103 * CS - Clipper. Mesa's clipping algorithms are imported to run on
104 * this unit. The fixed function part performs cliptesting against
105 * the 6 fixed clipplanes and makes decisions on whether or not the
106 * incoming primitive needs to be passed to a thread for clipping.
107 * User clip planes are handled via cooperation with the VS thread.
108 *
109 * SF - Strips Fans or Setup: Triangles are prepared for
110 * rasterization. Interpolation coefficients are calculated.
111 * Flatshading and two-side lighting usually performed here.
112 *
113 * WM - Windower. Interpolation of vertex attributes performed here.
114 * Fragment shader implemented here. SIMD aspects of EU taken full
115 * advantage of, as pixels are processed in blocks of 16.
116 *
117 * CC - Color Calculator. No EU threads associated with this unit.
118 * Handles blending and (presumably) depth and stencil testing.
119 */
120
121 #define BRW_MAX_CURBE (32*16)
122
123 struct brw_context;
124
125 struct brw_depth_stencil_state {
126 /* Precalculated hardware state:
127 */
128 struct brw_cc0 cc0;
129 struct brw_cc1 cc1;
130 struct brw_cc2 cc2;
131 struct brw_cc3 cc3;
132 struct brw_cc7 cc7;
133
134 unsigned iz_lookup;
135 };
136
137
138 struct brw_blend_state {
139 /* Precalculated hardware state:
140 */
141 struct brw_cc2 cc2;
142 struct brw_cc3 cc3;
143 struct brw_cc5 cc5;
144 struct brw_cc6 cc6;
145
146 struct brw_surf_ss0 ss0;
147 };
148
149
150 struct brw_rasterizer_state;
151
152
153 struct brw_vertex_shader {
154 const struct tgsi_token *tokens;
155 struct tgsi_shader_info info;
156
157 unsigned id;
158 struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */
159 GLboolean use_const_buffer;
160 };
161
162
163 struct brw_fragment_shader {
164 const struct tgsi_token *tokens;
165 struct tgsi_shader_info info;
166
167 unsigned iz_lookup;
168 //unsigned wm_lookup;
169
170 boolean uses_depth:1;
171 boolean has_flow_control:1;
172
173 unsigned id;
174 struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */
175 GLboolean use_const_buffer;
176 };
177
178
179 struct brw_sampler {
180 float border_color[4];
181 struct brw_ss0 ss0;
182 struct brw_ss1 ss1;
183 struct brw_ss3 ss3;
184 };
185
186
187
188 #define PIPE_NEW_DEPTH_STENCIL_ALPHA 0x1
189 #define PIPE_NEW_RAST 0x2
190 #define PIPE_NEW_BLEND 0x4
191 #define PIPE_NEW_VIEWPORT 0x8
192 #define PIPE_NEW_SAMPLERS 0x10
193 #define PIPE_NEW_VERTEX_BUFFER 0x20
194 #define PIPE_NEW_VERTEX_ELEMENT 0x40
195 #define PIPE_NEW_FRAGMENT_SHADER 0x80
196 #define PIPE_NEW_VERTEX_SHADER 0x100
197 #define PIPE_NEW_FRAGMENT_CONSTANTS 0x200
198 #define PIPE_NEW_VERTEX_CONSTANTS 0x400
199 #define PIPE_NEW_CLIP 0x800
200 #define PIPE_NEW_INDEX_BUFFER 0x1000
201 #define PIPE_NEW_INDEX_RANGE 0x2000
202 #define PIPE_NEW_BLEND_COLOR 0x4000
203 #define PIPE_NEW_POLYGON_STIPPLE 0x8000
204 #define PIPE_NEW_FRAMEBUFFER_DIMENSIONS 0x10000
205 #define PIPE_NEW_DEPTH_BUFFER 0x20000
206 #define PIPE_NEW_COLOR_BUFFERS 0x40000
207 #define PIPE_NEW_QUERY 0x80000
208 #define PIPE_NEW_SCISSOR 0x100000
209 #define PIPE_NEW_BOUND_TEXTURES 0x200000
210
211
212
213 #define BRW_NEW_URB_FENCE 0x1
214 #define BRW_NEW_FRAGMENT_PROGRAM 0x2
215 #define BRW_NEW_VERTEX_PROGRAM 0x4
216 #define BRW_NEW_INPUT_DIMENSIONS 0x8
217 #define BRW_NEW_CURBE_OFFSETS 0x10
218 #define BRW_NEW_REDUCED_PRIMITIVE 0x20
219 #define BRW_NEW_PRIMITIVE 0x40
220 #define BRW_NEW_CONTEXT 0x80
221 #define BRW_NEW_WM_INPUT_DIMENSIONS 0x100
222 #define BRW_NEW_PSP 0x800
223 #define BRW_NEW_WM_SURFACES 0x1000
224 #define BRW_NEW_xxx 0x2000 /* was FENCE */
225 #define BRW_NEW_INDICES 0x4000
226 #define BRW_NEW_VERTICES 0x8000
227 /**
228 * Used for any batch entry with a relocated pointer that will be used
229 * by any 3D rendering. Need to re-emit these fresh in each
230 * batchbuffer as the referenced buffers may be relocated in the
231 * meantime.
232 */
233 #define BRW_NEW_BATCH 0x10000
234 #define BRW_NEW_NR_WM_SURFACES 0x40000
235 #define BRW_NEW_NR_VS_SURFACES 0x80000
236 #define BRW_NEW_INDEX_BUFFER 0x100000
237
238 struct brw_state_flags {
239 /** State update flags signalled by mesa internals */
240 GLuint mesa;
241 /**
242 * State update flags signalled as the result of brw_tracked_state updates
243 */
244 GLuint brw;
245 /** State update flags signalled by brw_state_cache.c searches */
246 GLuint cache;
247 };
248
249
250
251 /* Data about a particular attempt to compile a program. Note that
252 * there can be many of these, each in a different GL state
253 * corresponding to a different brw_wm_prog_key struct, with different
254 * compiled programs:
255 */
256 struct brw_wm_prog_data {
257 GLuint curb_read_length;
258 GLuint urb_read_length;
259
260 GLuint first_curbe_grf;
261 GLuint total_grf;
262 GLuint total_scratch;
263
264 GLuint nr_params; /**< number of float params/constants */
265 GLboolean error;
266
267 /* Pointer to tracked values (only valid once
268 * _mesa_load_state_parameters has been called at runtime).
269 */
270 const GLfloat *param[BRW_MAX_CURBE];
271 };
272
273 struct brw_sf_prog_data {
274 GLuint urb_read_length;
275 GLuint total_grf;
276
277 /* Each vertex may have upto 12 attributes, 4 components each,
278 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
279 * rows.
280 *
281 * Actually we use 4 for each, so call it 12 rows.
282 */
283 GLuint urb_entry_size;
284 };
285
286
287 struct brw_clip_prog_data;
288
289 struct brw_gs_prog_data {
290 GLuint urb_read_length;
291 GLuint total_grf;
292 };
293
294 struct brw_vs_prog_data {
295 GLuint curb_read_length;
296 GLuint urb_read_length;
297 GLuint total_grf;
298
299 GLuint nr_outputs;
300 GLuint nr_inputs;
301
302 GLuint nr_params; /**< number of TGSI_FILE_CONSTANT's */
303
304 GLboolean copy_edgeflag;
305 GLboolean writes_psiz;
306
307 /* Used for calculating urb partitions:
308 */
309 GLuint urb_entry_size;
310 };
311
312
313 /* Size == 0 if output either not written, or always [0,0,0,1]
314 */
315 struct brw_vs_ouput_sizes {
316 GLubyte output_size[PIPE_MAX_SHADER_OUTPUTS];
317 };
318
319
320 /** Number of texture sampler units */
321 #define BRW_MAX_TEX_UNIT 16
322
323 /**
324 * Size of our surface binding table for the WM.
325 * This contains pointers to the drawing surfaces and current texture
326 * objects and shader constant buffers (+2).
327 */
328 #define BRW_WM_MAX_SURF (PIPE_MAX_COLOR_BUFS + BRW_MAX_TEX_UNIT + 1)
329
330 /**
331 * Helpers to convert drawing buffers, textures and constant buffers
332 * to surface binding table indexes, for WM.
333 */
334 #define SURF_INDEX_DRAW(d) (d)
335 #define SURF_INDEX_FRAG_CONST_BUFFER (PIPE_MAX_COLOR_BUFS)
336 #define SURF_INDEX_TEXTURE(t) (PIPE_MAX_COLOR_BUFS + 1 + (t))
337
338 /**
339 * Size of surface binding table for the VS.
340 * Only one constant buffer for now.
341 */
342 #define BRW_VS_MAX_SURF 1
343
344 /**
345 * Only a VS constant buffer
346 */
347 #define SURF_INDEX_VERT_CONST_BUFFER 0
348
349
350 enum brw_cache_id {
351 BRW_CC_VP,
352 BRW_CC_UNIT,
353 BRW_WM_PROG,
354 BRW_SAMPLER_DEFAULT_COLOR,
355 BRW_SAMPLER,
356 BRW_WM_UNIT,
357 BRW_SF_PROG,
358 BRW_SF_VP,
359 BRW_SF_UNIT,
360 BRW_VS_UNIT,
361 BRW_VS_PROG,
362 BRW_GS_UNIT,
363 BRW_GS_PROG,
364 BRW_CLIP_VP,
365 BRW_CLIP_UNIT,
366 BRW_CLIP_PROG,
367 BRW_SS_SURFACE,
368 BRW_SS_SURF_BIND,
369
370 BRW_MAX_CACHE
371 };
372
373 struct brw_cache_item {
374 /**
375 * Effectively part of the key, cache_id identifies what kind of state
376 * buffer is involved, and also which brw->state.dirty.cache flag should
377 * be set when this cache item is chosen.
378 */
379 enum brw_cache_id cache_id;
380 /** 32-bit hash of the key data */
381 GLuint hash;
382 GLuint key_size; /* for variable-sized keys */
383 const void *key;
384 struct brw_winsys_buffer **reloc_bufs;
385 GLuint nr_reloc_bufs;
386
387 struct brw_winsys_buffer *bo;
388 GLuint data_size;
389
390 struct brw_cache_item *next;
391 };
392
393
394
395 struct brw_cache {
396 struct brw_context *brw;
397 struct brw_winsys_screen *sws;
398
399 struct brw_cache_item **items;
400 GLuint size, n_items;
401
402 GLuint key_size[BRW_MAX_CACHE]; /* for fixed-size keys */
403 GLuint aux_size[BRW_MAX_CACHE];
404 char *name[BRW_MAX_CACHE];
405
406
407 /* Record of the last BOs chosen for each cache_id. Used to set
408 * brw->state.dirty.cache when a new cache item is chosen.
409 */
410 struct brw_winsys_buffer *last_bo[BRW_MAX_CACHE];
411 };
412
413
414 struct brw_tracked_state {
415 struct brw_state_flags dirty;
416 int (*prepare)( struct brw_context *brw );
417 int (*emit)( struct brw_context *brw );
418 };
419
420 /* Flags for brw->state.cache.
421 */
422 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
423 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
424 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
425 #define CACHE_NEW_SAMPLER_DEFAULT_COLOR (1<<BRW_SAMPLER_DEFAULT_COLOR)
426 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
427 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
428 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
429 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
430 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
431 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
432 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
433 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
434 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
435 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
436 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
437 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
438 #define CACHE_NEW_SURFACE (1<<BRW_SS_SURFACE)
439 #define CACHE_NEW_SURF_BIND (1<<BRW_SS_SURF_BIND)
440
441 struct brw_cached_batch_item {
442 struct header *header;
443 GLuint sz;
444 struct brw_cached_batch_item *next;
445 };
446
447
448
449 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
450 * be easier if C allowed arrays of packed elements?
451 */
452 #define VS_INPUT_BITMASK_DWORDS ((PIPE_MAX_SHADER_INPUTS+31)/32)
453
454
455
456
457 struct brw_vertex_info {
458 GLuint sizes[VS_INPUT_BITMASK_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */
459 };
460
461
462 struct brw_query_object {
463 /** Doubly linked list of active query objects in the context. */
464 struct brw_query_object *prev, *next;
465
466 /** Last query BO associated with this query. */
467 struct brw_winsys_buffer *bo;
468 /** First index in bo with query data for this object. */
469 int first_index;
470 /** Last index in bo with query data for this object. */
471 int last_index;
472
473 /* Total count of pixels from previous BOs */
474 uint64_t result;
475 };
476
477
478 /**
479 * brw_context is derived from pipe_context
480 */
481 struct brw_context
482 {
483 struct pipe_context base;
484 struct brw_chipset chipset;
485
486 struct brw_screen *brw_screen;
487 struct brw_winsys_screen *sws;
488
489 struct brw_batchbuffer *batch;
490
491 GLuint primitive;
492 GLuint reduced_primitive;
493
494 /* Active state from the state tracker:
495 */
496 struct {
497 struct brw_vertex_shader *vertex_shader;
498 struct brw_fragment_shader *fragment_shader;
499 const struct brw_blend_state *blend;
500 const struct brw_rasterizer_state *rast;
501 const struct brw_depth_stencil_state *zstencil;
502
503 const struct brw_sampler *sampler[PIPE_MAX_SAMPLERS];
504 const struct pipe_vertex_element vertex_element[PIPE_MAX_ATTRIBS];
505 unsigned num_vertex_elements;
506 unsigned num_samplers;
507
508 struct brw_texture *texture[PIPE_MAX_SAMPLERS];
509 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
510 unsigned num_textures;
511 unsigned num_vertex_buffers;
512
513 struct pipe_scissor_state scissor;
514 struct pipe_framebuffer_state fb;
515 struct pipe_viewport_state vp;
516 struct pipe_clip_state ucp;
517 struct pipe_buffer *vertex_constants;
518 struct pipe_buffer *fragment_constants;
519
520 struct pipe_viewport_state viewport;
521 struct brw_blend_constant_color bcc;
522 struct brw_polygon_stipple bps;
523
524
525
526 /**
527 * Index buffer for this draw_prims call.
528 *
529 * Updates are signaled by PIPE_NEW_INDEX_BUFFER.
530 */
531 struct pipe_buffer *index_buffer;
532 unsigned index_size;
533
534 /* Updates are signalled by PIPE_NEW_INDEX_RANGE:
535 */
536 unsigned min_index;
537 unsigned max_index;
538
539 } curr;
540
541 struct {
542 struct brw_state_flags dirty;
543
544 /**
545 * List of buffers accumulated in brw_validate_state to receive
546 * dri_bo_check_aperture treatment before exec, so we can know if we
547 * should flush the batch and try again before emitting primitives.
548 *
549 * This can be a fixed number as we only have a limited number of
550 * objects referenced from the batchbuffer in a primitive emit,
551 * consisting of the vertex buffers, pipelined state pointers,
552 * the CURBE, the depth buffer, and a query BO.
553 */
554 struct brw_winsys_buffer *validated_bos[PIPE_MAX_SHADER_INPUTS + 16];
555 int validated_bo_count;
556 } state;
557
558 struct brw_cache cache; /** non-surface items */
559 struct brw_cache surface_cache; /* surface items */
560 struct brw_cached_batch_item *cached_batch_items;
561
562 struct {
563 struct u_upload_mgr *upload_vertex;
564 struct u_upload_mgr *upload_index;
565
566 /* Information on uploaded vertex buffers:
567 */
568 struct {
569 unsigned stride; /* in bytes between successive vertices */
570 unsigned offset; /* in bytes, of first vertex in bo */
571 unsigned vertex_count; /* count of valid vertices which may be accessed */
572 struct brw_winsys_buffer *bo;
573 } vb[PIPE_MAX_ATTRIBS];
574
575 struct {
576 } ve[PIPE_MAX_ATTRIBS];
577
578 unsigned nr_vb; /* currently the same as curr.num_vertex_buffers */
579 unsigned nr_ve; /* currently the same as curr.num_vertex_elements */
580 } vb;
581
582 struct {
583 /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */
584 struct brw_winsys_buffer *bo;
585 unsigned int offset;
586 unsigned int size;
587 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
588 * avoid re-uploading the IB packet over and over if we're actually
589 * referencing the same index buffer.
590 */
591 unsigned int start_vertex_offset;
592 } ib;
593
594
595 /* BRW_NEW_URB_ALLOCATIONS:
596 */
597 struct {
598 GLuint vsize; /* vertex size plus header in urb registers */
599 GLuint csize; /* constant buffer size in urb registers */
600 GLuint sfsize; /* setup data size in urb registers */
601
602 GLboolean constrained;
603
604 GLuint nr_vs_entries;
605 GLuint nr_gs_entries;
606 GLuint nr_clip_entries;
607 GLuint nr_sf_entries;
608 GLuint nr_cs_entries;
609
610 GLuint vs_start;
611 GLuint gs_start;
612 GLuint clip_start;
613 GLuint sf_start;
614 GLuint cs_start;
615 } urb;
616
617
618 /* BRW_NEW_CURBE_OFFSETS:
619 */
620 struct {
621 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
622 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
623 GLuint clip_start;
624 GLuint clip_size;
625 GLuint vs_start;
626 GLuint vs_size;
627 GLuint total_size;
628
629 struct brw_winsys_buffer *curbe_bo;
630 /** Offset within curbe_bo of space for current curbe entry */
631 GLuint curbe_offset;
632 /** Offset within curbe_bo of space for next curbe entry */
633 GLuint curbe_next_offset;
634
635 GLfloat *last_buf;
636 GLuint last_bufsz;
637 /**
638 * Whether we should create a new bo instead of reusing the old one
639 * (if we just dispatch the batch pointing at the old one.
640 */
641 GLboolean need_new_bo;
642 } curbe;
643
644 struct {
645 struct brw_vs_prog_data *prog_data;
646
647 struct brw_winsys_buffer *prog_bo;
648 struct brw_winsys_buffer *state_bo;
649
650 /** Binding table of pointers to surf_bo entries */
651 struct brw_winsys_buffer *bind_bo;
652 struct brw_winsys_buffer *surf_bo[BRW_VS_MAX_SURF];
653 GLuint nr_surfaces;
654 } vs;
655
656 struct {
657 struct brw_gs_prog_data *prog_data;
658
659 GLboolean prog_active;
660 struct brw_winsys_buffer *prog_bo;
661 struct brw_winsys_buffer *state_bo;
662 } gs;
663
664 struct {
665 struct brw_clip_prog_data *prog_data;
666
667 struct brw_winsys_buffer *prog_bo;
668 struct brw_winsys_buffer *state_bo;
669 struct brw_winsys_buffer *vp_bo;
670 } clip;
671
672
673 struct {
674 struct brw_sf_prog_data *prog_data;
675
676 struct brw_winsys_buffer *prog_bo;
677 struct brw_winsys_buffer *state_bo;
678 struct brw_winsys_buffer *vp_bo;
679 } sf;
680
681 struct {
682 struct brw_wm_prog_data *prog_data;
683 struct brw_wm_compile *compile_data;
684
685 /** Input sizes, calculated from active vertex program.
686 * One bit per fragment program input attribute.
687 */
688 //GLbitfield input_size_masks[4];
689
690 /** Array of surface default colors (texture border color) */
691 struct brw_winsys_buffer *sdc_bo[BRW_MAX_TEX_UNIT];
692
693 GLuint render_surf;
694 GLuint nr_surfaces;
695
696 GLuint max_threads;
697 struct brw_winsys_buffer *scratch_bo;
698
699 GLuint sampler_count;
700 struct brw_winsys_buffer *sampler_bo;
701
702 /** Binding table of pointers to surf_bo entries */
703 struct brw_winsys_buffer *bind_bo;
704 struct brw_winsys_buffer *surf_bo[PIPE_MAX_COLOR_BUFS];
705
706 struct brw_winsys_buffer *prog_bo;
707 struct brw_winsys_buffer *state_bo;
708 } wm;
709
710
711 struct {
712 struct brw_winsys_buffer *prog_bo;
713 struct brw_winsys_buffer *state_bo;
714 struct brw_winsys_buffer *vp_bo;
715 } cc;
716
717 struct {
718 struct brw_query_object active_head;
719 struct brw_winsys_buffer *bo;
720 int index;
721 GLboolean active;
722 int stats_wm;
723 } query;
724
725 struct {
726 unsigned always_emit_state:1;
727 unsigned always_flush_batch:1;
728 unsigned force_swtnl:1;
729 unsigned no_swtnl:1;
730 } flags;
731
732 /* Used to give every program string a unique id
733 */
734 GLuint program_id;
735 };
736
737
738
739 /*======================================================================
740 * brw_queryobj.c
741 */
742 void brw_init_query(struct brw_context *brw);
743 void brw_prepare_query_begin(struct brw_context *brw);
744 void brw_emit_query_begin(struct brw_context *brw);
745 void brw_emit_query_end(struct brw_context *brw);
746
747 /*======================================================================
748 * brw_state_dump.c
749 */
750 void brw_debug_batch(struct brw_context *intel);
751
752
753 /*======================================================================
754 * brw_pipe_*.c
755 */
756 void brw_pipe_blend_init( struct brw_context *brw );
757 void brw_pipe_depth_stencil_init( struct brw_context *brw );
758 void brw_pipe_framebuffer_init( struct brw_context *brw );
759 void brw_pipe_flush_init( struct brw_context *brw );
760 void brw_pipe_misc_init( struct brw_context *brw );
761 void brw_pipe_query_init( struct brw_context *brw );
762 void brw_pipe_rast_init( struct brw_context *brw );
763 void brw_pipe_sampler_init( struct brw_context *brw );
764 void brw_pipe_shader_init( struct brw_context *brw );
765 void brw_pipe_vertex_init( struct brw_context *brw );
766
767 void brw_pipe_blend_cleanup( struct brw_context *brw );
768 void brw_pipe_depth_stencil_cleanup( struct brw_context *brw );
769 void brw_pipe_framebuffer_cleanup( struct brw_context *brw );
770 void brw_pipe_flush_cleanup( struct brw_context *brw );
771 void brw_pipe_misc_cleanup( struct brw_context *brw );
772 void brw_pipe_query_cleanup( struct brw_context *brw );
773 void brw_pipe_rast_cleanup( struct brw_context *brw );
774 void brw_pipe_sampler_cleanup( struct brw_context *brw );
775 void brw_pipe_shader_cleanup( struct brw_context *brw );
776 void brw_pipe_vertex_cleanup( struct brw_context *brw );
777
778
779 /* brw_urb.c
780 */
781 int brw_upload_urb_fence(struct brw_context *brw);
782
783 /* brw_curbe.c
784 */
785 int brw_upload_cs_urb_state(struct brw_context *brw);
786
787 /* brw_disasm.c */
788 int brw_disasm (FILE *file, struct brw_instruction *inst);
789
790 /*======================================================================
791 * Inline conversion functions. These are better-typed than the
792 * macros used previously:
793 */
794 static INLINE struct brw_context *
795 brw_context( struct pipe_context *ctx )
796 {
797 return (struct brw_context *)ctx;
798 }
799
800
801 #define BRW_IS_965(brw) ((brw)->chipset.is_965)
802 #define BRW_IS_IGDNG(brw) ((brw)->chipset.is_igdng)
803 #define BRW_IS_G4X(brw) ((brw)->chipset.is_g4x)
804
805
806 #endif
807