i965g: add lots of error checks and early returns
[mesa.git] / src / gallium / drivers / i965 / brw_draw.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "util/u_prim.h"
30 #include "util/u_upload_mgr.h"
31
32 #include "brw_draw.h"
33 #include "brw_defines.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_debug.h"
37 #include "brw_screen.h"
38
39 #include "brw_batchbuffer.h"
40
41
42 static uint32_t prim_to_hw_prim[PIPE_PRIM_POLYGON+1] = {
43 _3DPRIM_POINTLIST,
44 _3DPRIM_LINELIST,
45 _3DPRIM_LINELOOP,
46 _3DPRIM_LINESTRIP,
47 _3DPRIM_TRILIST,
48 _3DPRIM_TRISTRIP,
49 _3DPRIM_TRIFAN,
50 _3DPRIM_QUADLIST,
51 _3DPRIM_QUADSTRIP,
52 _3DPRIM_POLYGON
53 };
54
55
56
57 /* When the primitive changes, set a state bit and re-validate. Not
58 * the nicest and would rather deal with this by having all the
59 * programs be immune to the active primitive (ie. cope with all
60 * possibilities). That may not be realistic however.
61 */
62 static int brw_set_prim(struct brw_context *brw, unsigned prim )
63 {
64
65 if (BRW_DEBUG & DEBUG_PRIMS)
66 debug_printf("PRIM: %s\n", u_prim_name(prim));
67
68 if (prim != brw->primitive) {
69 unsigned reduced_prim;
70
71 brw->primitive = prim;
72 brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;
73
74 reduced_prim = u_reduced_prim(prim);
75 if (reduced_prim != brw->reduced_primitive) {
76 brw->reduced_primitive = reduced_prim;
77 brw->state.dirty.brw |= BRW_NEW_REDUCED_PRIMITIVE;
78 }
79 }
80
81 return prim_to_hw_prim[prim];
82 }
83
84
85
86 static int brw_emit_prim(struct brw_context *brw,
87 unsigned start,
88 unsigned count,
89 boolean indexed,
90 uint32_t hw_prim)
91 {
92 struct brw_3d_primitive prim_packet;
93 int ret;
94
95 prim_packet.header.opcode = CMD_3D_PRIM;
96 prim_packet.header.length = sizeof(prim_packet)/4 - 2;
97 prim_packet.header.pad = 0;
98 prim_packet.header.topology = hw_prim;
99 prim_packet.header.indexed = indexed;
100
101 prim_packet.verts_per_instance = count;
102 prim_packet.start_vert_location = start;
103 if (indexed)
104 prim_packet.start_vert_location += brw->ib.start_vertex_offset;
105 prim_packet.instance_count = 1;
106 prim_packet.start_instance_location = 0;
107 prim_packet.base_vert_location = 0; // prim->basevertex; XXX: add this to gallium
108
109
110 /* If we're set to always flush, do it before and after the primitive emit.
111 * We want to catch both missed flushes that hurt instruction/state cache
112 * and missed flushes of the render cache as it heads to other parts of
113 * the besides the draw code.
114 */
115 if (0) {
116 BEGIN_BATCH(1, IGNORE_CLIPRECTS);
117 OUT_BATCH((CMD_MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE);
118 ADVANCE_BATCH();
119 }
120 if (prim_packet.verts_per_instance) {
121 ret = brw_batchbuffer_data( brw->batch, &prim_packet,
122 sizeof(prim_packet), LOOP_CLIPRECTS);
123 if (ret)
124 return ret;
125 }
126 if (0) {
127 BEGIN_BATCH(1, IGNORE_CLIPRECTS);
128 OUT_BATCH((CMD_MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE);
129 ADVANCE_BATCH();
130 }
131
132 return 0;
133 }
134
135
136 /* May fail if out of video memory for texture or vbo upload, or on
137 * fallback conditions.
138 */
139 static int
140 try_draw_range_elements(struct brw_context *brw,
141 struct pipe_buffer *index_buffer,
142 unsigned hw_prim,
143 unsigned start, unsigned count)
144 {
145 int ret;
146
147 ret = brw_validate_state(brw);
148 if (ret)
149 return ret;
150
151 /* Check that we can fit our state in with our existing batchbuffer, or
152 * flush otherwise.
153 */
154 ret = brw->sws->check_aperture_space(brw->sws,
155 brw->state.validated_bos,
156 brw->state.validated_bo_count);
157 if (ret)
158 return ret;
159
160 ret = brw_upload_state(brw);
161 if (ret)
162 return ret;
163
164 ret = brw_emit_prim(brw, start, count, index_buffer != NULL, hw_prim);
165 if (ret)
166 return ret;
167
168 if (brw->flags.always_flush_batch)
169 brw_context_flush( brw );
170
171 return 0;
172 }
173
174
175 static boolean
176 brw_draw_range_elements(struct pipe_context *pipe,
177 struct pipe_buffer *index_buffer,
178 unsigned index_size,
179 unsigned min_index,
180 unsigned max_index,
181 unsigned mode, unsigned start, unsigned count)
182 {
183 struct brw_context *brw = brw_context(pipe);
184 int ret;
185 uint32_t hw_prim;
186
187 hw_prim = brw_set_prim(brw, mode);
188
189 if (BRW_DEBUG & DEBUG_PRIMS)
190 debug_printf("PRIM: %s %d %d\n", u_prim_name(mode), start, count);
191
192 /* Potentially trigger upload of new index buffer.
193 *
194 * XXX: do we need to go through state validation to achieve this?
195 * Could just call upload code directly.
196 */
197 if (brw->curr.index_buffer != index_buffer) {
198 pipe_buffer_reference( &brw->curr.index_buffer, index_buffer );
199 brw->state.dirty.mesa |= PIPE_NEW_INDEX_BUFFER;
200 }
201
202 /* XXX: do we really care?
203 */
204 if (brw->curr.min_index != min_index ||
205 brw->curr.max_index != max_index)
206 {
207 brw->curr.min_index = min_index;
208 brw->curr.max_index = max_index;
209 brw->state.dirty.mesa |= PIPE_NEW_INDEX_RANGE;
210 }
211
212
213 /* Make a first attempt at drawing:
214 */
215 ret = try_draw_range_elements(brw, index_buffer, hw_prim, start, count );
216
217 /* Otherwise, flush and retry:
218 */
219 if (ret != 0) {
220 brw_context_flush( brw );
221 ret = try_draw_range_elements(brw, index_buffer, hw_prim, start, count );
222 assert(ret == 0);
223 }
224
225 return TRUE;
226 }
227
228 static boolean
229 brw_draw_elements(struct pipe_context *pipe,
230 struct pipe_buffer *index_buffer,
231 unsigned index_size,
232 unsigned mode,
233 unsigned start, unsigned count)
234 {
235 return brw_draw_range_elements( pipe, index_buffer,
236 index_size,
237 0, 0xffffffff,
238 mode,
239 start, count );
240 }
241
242 static boolean
243 brw_draw_arrays(struct pipe_context *pipe, unsigned mode,
244 unsigned start, unsigned count)
245 {
246 return brw_draw_elements(pipe, NULL, 0, mode, start, count);
247 }
248
249
250
251 boolean brw_draw_init( struct brw_context *brw )
252 {
253 /* Register our drawing function:
254 */
255 brw->base.draw_arrays = brw_draw_arrays;
256 brw->base.draw_elements = brw_draw_elements;
257 brw->base.draw_range_elements = brw_draw_range_elements;
258
259 /* Create helpers for uploading data in user buffers:
260 */
261 brw->vb.upload_vertex = u_upload_create( brw->base.screen,
262 128 * 1024,
263 64,
264 PIPE_BUFFER_USAGE_VERTEX );
265 if (brw->vb.upload_vertex == NULL)
266 return FALSE;
267
268 brw->vb.upload_index = u_upload_create( brw->base.screen,
269 128 * 1024,
270 64,
271 PIPE_BUFFER_USAGE_INDEX );
272 if (brw->vb.upload_index == NULL)
273 return FALSE;
274
275 return TRUE;
276 }
277
278 void brw_draw_cleanup( struct brw_context *brw )
279 {
280 u_upload_destroy( brw->vb.upload_vertex );
281 u_upload_destroy( brw->vb.upload_index );
282
283 bo_reference(&brw->ib.bo, NULL);
284 }