1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "pipe/p_context.h"
29 #include "util/u_inlines.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/u_math.h"
35 #include "brw_defines.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38 #include "brw_screen.h"
39 #include "brw_batchbuffer.h"
40 #include "brw_debug.h"
45 static unsigned brw_translate_surface_format( unsigned id
)
48 case PIPE_FORMAT_R64_FLOAT
:
49 return BRW_SURFACEFORMAT_R64_FLOAT
;
50 case PIPE_FORMAT_R64G64_FLOAT
:
51 return BRW_SURFACEFORMAT_R64G64_FLOAT
;
52 case PIPE_FORMAT_R64G64B64_FLOAT
:
53 return BRW_SURFACEFORMAT_R64G64B64_FLOAT
;
54 case PIPE_FORMAT_R64G64B64A64_FLOAT
:
55 return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
;
57 case PIPE_FORMAT_R32_FLOAT
:
58 return BRW_SURFACEFORMAT_R32_FLOAT
;
59 case PIPE_FORMAT_R32G32_FLOAT
:
60 return BRW_SURFACEFORMAT_R32G32_FLOAT
;
61 case PIPE_FORMAT_R32G32B32_FLOAT
:
62 return BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
63 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
64 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
66 case PIPE_FORMAT_R32_UNORM
:
67 return BRW_SURFACEFORMAT_R32_UNORM
;
68 case PIPE_FORMAT_R32G32_UNORM
:
69 return BRW_SURFACEFORMAT_R32G32_UNORM
;
70 case PIPE_FORMAT_R32G32B32_UNORM
:
71 return BRW_SURFACEFORMAT_R32G32B32_UNORM
;
72 case PIPE_FORMAT_R32G32B32A32_UNORM
:
73 return BRW_SURFACEFORMAT_R32G32B32A32_UNORM
;
75 case PIPE_FORMAT_R32_USCALED
:
76 return BRW_SURFACEFORMAT_R32_USCALED
;
77 case PIPE_FORMAT_R32G32_USCALED
:
78 return BRW_SURFACEFORMAT_R32G32_USCALED
;
79 case PIPE_FORMAT_R32G32B32_USCALED
:
80 return BRW_SURFACEFORMAT_R32G32B32_USCALED
;
81 case PIPE_FORMAT_R32G32B32A32_USCALED
:
82 return BRW_SURFACEFORMAT_R32G32B32A32_USCALED
;
84 case PIPE_FORMAT_R32_SNORM
:
85 return BRW_SURFACEFORMAT_R32_SNORM
;
86 case PIPE_FORMAT_R32G32_SNORM
:
87 return BRW_SURFACEFORMAT_R32G32_SNORM
;
88 case PIPE_FORMAT_R32G32B32_SNORM
:
89 return BRW_SURFACEFORMAT_R32G32B32_SNORM
;
90 case PIPE_FORMAT_R32G32B32A32_SNORM
:
91 return BRW_SURFACEFORMAT_R32G32B32A32_SNORM
;
93 case PIPE_FORMAT_R32_SSCALED
:
94 return BRW_SURFACEFORMAT_R32_SSCALED
;
95 case PIPE_FORMAT_R32G32_SSCALED
:
96 return BRW_SURFACEFORMAT_R32G32_SSCALED
;
97 case PIPE_FORMAT_R32G32B32_SSCALED
:
98 return BRW_SURFACEFORMAT_R32G32B32_SSCALED
;
99 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
100 return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
;
102 case PIPE_FORMAT_R16_UNORM
:
103 return BRW_SURFACEFORMAT_R16_UNORM
;
104 case PIPE_FORMAT_R16G16_UNORM
:
105 return BRW_SURFACEFORMAT_R16G16_UNORM
;
106 case PIPE_FORMAT_R16G16B16_UNORM
:
107 return BRW_SURFACEFORMAT_R16G16B16_UNORM
;
108 case PIPE_FORMAT_R16G16B16A16_UNORM
:
109 return BRW_SURFACEFORMAT_R16G16B16A16_UNORM
;
111 case PIPE_FORMAT_R16_USCALED
:
112 return BRW_SURFACEFORMAT_R16_USCALED
;
113 case PIPE_FORMAT_R16G16_USCALED
:
114 return BRW_SURFACEFORMAT_R16G16_USCALED
;
115 case PIPE_FORMAT_R16G16B16_USCALED
:
116 return BRW_SURFACEFORMAT_R16G16B16_USCALED
;
117 case PIPE_FORMAT_R16G16B16A16_USCALED
:
118 return BRW_SURFACEFORMAT_R16G16B16A16_USCALED
;
120 case PIPE_FORMAT_R16_SNORM
:
121 return BRW_SURFACEFORMAT_R16_SNORM
;
122 case PIPE_FORMAT_R16G16_SNORM
:
123 return BRW_SURFACEFORMAT_R16G16_SNORM
;
124 case PIPE_FORMAT_R16G16B16_SNORM
:
125 return BRW_SURFACEFORMAT_R16G16B16_SNORM
;
126 case PIPE_FORMAT_R16G16B16A16_SNORM
:
127 return BRW_SURFACEFORMAT_R16G16B16A16_SNORM
;
129 case PIPE_FORMAT_R16_SSCALED
:
130 return BRW_SURFACEFORMAT_R16_SSCALED
;
131 case PIPE_FORMAT_R16G16_SSCALED
:
132 return BRW_SURFACEFORMAT_R16G16_SSCALED
;
133 case PIPE_FORMAT_R16G16B16_SSCALED
:
134 return BRW_SURFACEFORMAT_R16G16B16_SSCALED
;
135 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
136 return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
;
138 case PIPE_FORMAT_R8_UNORM
:
139 return BRW_SURFACEFORMAT_R8_UNORM
;
140 case PIPE_FORMAT_R8G8_UNORM
:
141 return BRW_SURFACEFORMAT_R8G8_UNORM
;
142 case PIPE_FORMAT_R8G8B8_UNORM
:
143 return BRW_SURFACEFORMAT_R8G8B8_UNORM
;
144 case PIPE_FORMAT_R8G8B8A8_UNORM
:
145 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM
;
147 case PIPE_FORMAT_R8_USCALED
:
148 return BRW_SURFACEFORMAT_R8_USCALED
;
149 case PIPE_FORMAT_R8G8_USCALED
:
150 return BRW_SURFACEFORMAT_R8G8_USCALED
;
151 case PIPE_FORMAT_R8G8B8_USCALED
:
152 return BRW_SURFACEFORMAT_R8G8B8_USCALED
;
153 case PIPE_FORMAT_R8G8B8A8_USCALED
:
154 return BRW_SURFACEFORMAT_R8G8B8A8_USCALED
;
156 case PIPE_FORMAT_R8_SNORM
:
157 return BRW_SURFACEFORMAT_R8_SNORM
;
158 case PIPE_FORMAT_R8G8_SNORM
:
159 return BRW_SURFACEFORMAT_R8G8_SNORM
;
160 case PIPE_FORMAT_R8G8B8_SNORM
:
161 return BRW_SURFACEFORMAT_R8G8B8_SNORM
;
162 case PIPE_FORMAT_R8G8B8A8_SNORM
:
163 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM
;
165 case PIPE_FORMAT_R8_SSCALED
:
166 return BRW_SURFACEFORMAT_R8_SSCALED
;
167 case PIPE_FORMAT_R8G8_SSCALED
:
168 return BRW_SURFACEFORMAT_R8G8_SSCALED
;
169 case PIPE_FORMAT_R8G8B8_SSCALED
:
170 return BRW_SURFACEFORMAT_R8G8B8_SSCALED
;
171 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
172 return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
;
180 static unsigned get_index_type(int type
)
183 case 1: return BRW_INDEX_BYTE
;
184 case 2: return BRW_INDEX_WORD
;
185 case 4: return BRW_INDEX_DWORD
;
186 default: assert(0); return 0;
191 static int brw_prepare_vertices(struct brw_context
*brw
)
193 unsigned int min_index
= brw
->curr
.min_index
;
194 unsigned int max_index
= brw
->curr
.max_index
;
198 if (BRW_DEBUG
& DEBUG_VERTS
)
199 debug_printf("%s %d..%d\n", __FUNCTION__
, min_index
, max_index
);
202 for (i
= 0; i
< brw
->curr
.num_vertex_buffers
; i
++) {
203 struct pipe_vertex_buffer
*vb
= &brw
->curr
.vertex_buffer
[i
];
204 struct brw_winsys_buffer
*bo
;
205 struct pipe_buffer
*upload_buf
= NULL
;
208 if (BRW_DEBUG
& DEBUG_VERTS
)
209 debug_printf("%s vb[%d] user:%d offset:0x%x sz:0x%x stride:0x%x\n",
211 brw_buffer_is_user_buffer(vb
->buffer
),
216 if (brw_buffer_is_user_buffer(vb
->buffer
)) {
218 /* XXX: simplify this. Stop the state trackers from generating
219 * zero-stride buffers & have them use additional constants (or
220 * add support for >1 constant buffer) instead.
222 unsigned size
= (vb
->stride
== 0 ?
223 vb
->buffer
->size
- vb
->buffer_offset
:
224 MAX2(vb
->buffer
->size
- vb
->buffer_offset
,
225 vb
->stride
* (max_index
+ 1 - min_index
)));
227 ret
= u_upload_buffer( brw
->vb
.upload_vertex
,
228 vb
->buffer_offset
+ min_index
* vb
->stride
,
236 bo
= brw_buffer(upload_buf
)->bo
;
238 assert(offset
+ size
<= bo
->size
);
242 offset
= vb
->buffer_offset
;
243 bo
= brw_buffer(vb
->buffer
)->bo
;
246 assert(offset
< bo
->size
);
248 /* Set up post-upload info about this vertex buffer:
250 brw
->vb
.vb
[i
].offset
= offset
;
251 brw
->vb
.vb
[i
].stride
= vb
->stride
;
252 brw
->vb
.vb
[i
].vertex_count
= (vb
->stride
== 0 ?
254 (bo
->size
- offset
) / vb
->stride
);
256 bo_reference( &brw
->vb
.vb
[i
].bo
, bo
);
258 /* Don't need to retain this reference. We have a reference on
259 * the underlying winsys buffer:
261 pipe_buffer_reference( &upload_buf
, NULL
);
265 brw_prepare_query_begin(brw
);
267 for (i
= 0; i
< brw
->vb
.nr_vb
; i
++) {
268 brw_add_validated_bo(brw
, brw
->vb
.vb
[i
].bo
);
274 static int brw_emit_vertex_buffers( struct brw_context
*brw
)
278 /* If the VS doesn't read any inputs (calculating vertex position from
279 * a state variable for some reason, for example), just bail.
281 * The stale VB state stays in place, but they don't do anything unless
282 * a VE loads from them.
284 if (brw
->vb
.nr_vb
== 0) {
285 if (BRW_DEBUG
& DEBUG_VERTS
)
286 debug_printf("%s: no active vertex buffers\n", __FUNCTION__
);
291 /* Emit VB state packets.
293 BEGIN_BATCH(1 + brw
->vb
.nr_vb
* 4, IGNORE_CLIPRECTS
);
294 OUT_BATCH((CMD_VERTEX_BUFFER
<< 16) |
295 ((1 + brw
->vb
.nr_vb
* 4) - 2));
297 for (i
= 0; i
< brw
->vb
.nr_vb
; i
++) {
298 OUT_BATCH((i
<< BRW_VB0_INDEX_SHIFT
) |
299 BRW_VB0_ACCESS_VERTEXDATA
|
300 (brw
->vb
.vb
[i
].stride
<< BRW_VB0_PITCH_SHIFT
));
301 OUT_RELOC(brw
->vb
.vb
[i
].bo
,
303 brw
->vb
.vb
[i
].offset
);
304 if (BRW_IS_IGDNG(brw
)) {
305 OUT_RELOC(brw
->vb
.vb
[i
].bo
,
307 brw
->vb
.vb
[i
].bo
->size
- 1);
309 OUT_BATCH(brw
->vb
.vb
[i
].stride
? brw
->vb
.vb
[i
].vertex_count
: 0);
310 OUT_BATCH(0); /* Instance data step rate */
319 static int brw_emit_vertex_elements(struct brw_context
*brw
)
321 GLuint nr
= brw
->curr
.num_vertex_elements
;
324 brw_emit_query_begin(brw
);
326 /* If the VS doesn't read any inputs (calculating vertex position from
327 * a state variable for some reason, for example), emit a single pad
328 * VERTEX_ELEMENT struct and bail.
330 * The stale VB state stays in place, but they don't do anything unless
331 * a VE loads from them.
334 BEGIN_BATCH(3, IGNORE_CLIPRECTS
);
335 OUT_BATCH((CMD_VERTEX_ELEMENT
<< 16) | 1);
336 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT
) |
338 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
339 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
340 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
341 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
342 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
343 (BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
));
348 /* Now emit vertex element (VEP) state packets.
351 BEGIN_BATCH(1 + nr
* 2, IGNORE_CLIPRECTS
);
352 OUT_BATCH((CMD_VERTEX_ELEMENT
<< 16) | ((1 + nr
* 2) - 2));
353 for (i
= 0; i
< nr
; i
++) {
354 const struct pipe_vertex_element
*input
= &brw
->curr
.vertex_element
[i
];
355 uint32_t format
= brw_translate_surface_format( input
->src_format
);
356 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
357 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
358 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_SRC
;
359 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_SRC
;
361 switch (input
->nr_components
) {
362 case 0: comp0
= BRW_VE1_COMPONENT_STORE_0
; /* fallthrough */
363 case 1: comp1
= BRW_VE1_COMPONENT_STORE_0
; /* fallthrough */
364 case 2: comp2
= BRW_VE1_COMPONENT_STORE_0
; /* fallthrough */
365 case 3: comp3
= BRW_VE1_COMPONENT_STORE_1_FLT
;
369 OUT_BATCH((input
->vertex_buffer_index
<< BRW_VE0_INDEX_SHIFT
) |
371 (format
<< BRW_VE0_FORMAT_SHIFT
) |
372 (input
->src_offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
374 if (BRW_IS_IGDNG(brw
))
375 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
376 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
377 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
378 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
));
380 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
381 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
382 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
383 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
) |
384 ((i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
));
391 static int brw_emit_vertices( struct brw_context
*brw
)
395 ret
= brw_emit_vertex_buffers( brw
);
399 ret
= brw_emit_vertex_elements( brw
);
407 const struct brw_tracked_state brw_vertices
= {
409 .mesa
= (PIPE_NEW_INDEX_RANGE
|
410 PIPE_NEW_VERTEX_BUFFER
),
411 .brw
= BRW_NEW_BATCH
,
414 .prepare
= brw_prepare_vertices
,
415 .emit
= brw_emit_vertices
,
419 static int brw_prepare_indices(struct brw_context
*brw
)
421 struct pipe_buffer
*index_buffer
= brw
->curr
.index_buffer
;
422 struct pipe_buffer
*upload_buf
= NULL
;
423 struct brw_winsys_buffer
*bo
= NULL
;
429 if (index_buffer
== NULL
)
432 if (BRW_DEBUG
& DEBUG_VERTS
)
433 debug_printf("%s: index_size:%d index_buffer->size:%d\n",
435 brw
->curr
.index_size
,
436 brw
->curr
.index_buffer
->size
);
438 ib_size
= index_buffer
->size
;
439 index_size
= brw
->curr
.index_size
;
441 /* Turn userbuffer into a proper hardware buffer?
443 if (brw_buffer_is_user_buffer(index_buffer
)) {
445 ret
= u_upload_buffer( brw
->vb
.upload_index
,
454 bo
= brw_buffer(upload_buf
)->bo
;
456 /* XXX: annotate the userbuffer with the upload information so
457 * that successive calls don't get re-uploaded.
461 bo
= brw_buffer(index_buffer
)->bo
;
466 /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading the
467 * index buffer state when we're just moving the start index of our
470 * In gallium this will happen in the case where successive draw
471 * calls are made with (distinct?) userbuffers, but the upload_mgr
472 * places the data into a single winsys buffer.
474 * This statechange doesn't raise any state flags and is always
475 * just merged into the final draw packet:
478 assert((offset
& (index_size
- 1)) == 0);
479 brw
->ib
.start_vertex_offset
= offset
/ index_size
;
482 /* These statechanges trigger a new CMD_INDEX_BUFFER packet:
484 if (brw
->ib
.bo
!= bo
||
485 brw
->ib
.size
!= ib_size
)
487 bo_reference(&brw
->ib
.bo
, bo
);
488 brw
->ib
.size
= ib_size
;
489 brw
->state
.dirty
.brw
|= BRW_NEW_INDEX_BUFFER
;
492 pipe_buffer_reference( &upload_buf
, NULL
);
493 brw_add_validated_bo(brw
, brw
->ib
.bo
);
497 const struct brw_tracked_state brw_indices
= {
499 .mesa
= PIPE_NEW_INDEX_BUFFER
,
503 .prepare
= brw_prepare_indices
,
506 static int brw_emit_index_buffer(struct brw_context
*brw
)
508 /* Emit the indexbuffer packet:
512 struct brw_indexbuffer ib
;
514 memset(&ib
, 0, sizeof(ib
));
516 ib
.header
.bits
.opcode
= CMD_INDEX_BUFFER
;
517 ib
.header
.bits
.length
= sizeof(ib
)/4 - 2;
518 ib
.header
.bits
.index_format
= get_index_type(brw
->ib
.size
);
519 ib
.header
.bits
.cut_index_enable
= 0;
521 BEGIN_BATCH(4, IGNORE_CLIPRECTS
);
522 OUT_BATCH( ib
.header
.dword
);
523 OUT_RELOC(brw
->ib
.bo
,
526 OUT_RELOC(brw
->ib
.bo
,
528 brw
->ib
.offset
+ brw
->ib
.size
- 1);
536 const struct brw_tracked_state brw_index_buffer
= {
539 .brw
= BRW_NEW_BATCH
| BRW_NEW_INDEX_BUFFER
,
542 .emit
= brw_emit_index_buffer
,