src/gallium/drivers/i965/brw_draw_upload.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "pipe/p_context.h"
  29
  30 #include "util/u_upload_mgr.h"
  31
  32 #include "brw_draw.h"
  33 #include "brw_defines.h"
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_fallback.h"
  37
  38 #include "intel_batchbuffer.h"
  39 #include "intel_buffer_objects.h"
  40 #include "intel_tex.h"
  41
  42
  43
  44
  45 unsigned brw_translate_surface_format( unsigned id )
  46 {
  47    switch (id) {
  48    case PIPE_FORMAT_R64_FLOAT:
  49       return BRW_SURFACEFORMAT_R64_FLOAT;
  50    case PIPE_FORMAT_R64G64_FLOAT:
  51       return BRW_SURFACEFORMAT_R64G64_FLOAT;
  52    case PIPE_FORMAT_R64G64B64_FLOAT:
  53       return BRW_SURFACEFORMAT_R64G64B64_FLOAT;
  54    case PIPE_FORMAT_R64G64B64A64_FLOAT:
  55       return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT;
  56
  57    case PIPE_FORMAT_R32_FLOAT:
  58       return BRW_SURFACEFORMAT_R32_FLOAT;
  59    case PIPE_FORMAT_R32G32_FLOAT:
  60       return BRW_SURFACEFORMAT_R32G32_FLOAT;
  61    case PIPE_FORMAT_R32G32B32_FLOAT:
  62       return BRW_SURFACEFORMAT_R32G32B32_FLOAT;
  63    case PIPE_FORMAT_R32G32B32A32_FLOAT:
  64       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
  65
  66    case PIPE_FORMAT_R32_UNORM:
  67       return BRW_SURFACEFORMAT_R32_UNORM;
  68    case PIPE_FORMAT_R32G32_UNORM:
  69       return BRW_SURFACEFORMAT_R32G32_UNORM;
  70    case PIPE_FORMAT_R32G32B32_UNORM:
  71       return BRW_SURFACEFORMAT_R32G32B32_UNORM;
  72    case PIPE_FORMAT_R32G32B32A32_UNORM:
  73       return BRW_SURFACEFORMAT_R32G32B32A32_UNORM;
  74
  75    case PIPE_FORMAT_R32_USCALED:
  76       return BRW_SURFACEFORMAT_R32_USCALED;
  77    case PIPE_FORMAT_R32G32_USCALED:
  78       return BRW_SURFACEFORMAT_R32G32_USCALED;
  79    case PIPE_FORMAT_R32G32B32_USCALED:
  80       return BRW_SURFACEFORMAT_R32G32B32_USCALED;
  81    case PIPE_FORMAT_R32G32B32A32_USCALED:
  82       return BRW_SURFACEFORMAT_R32G32B32A32_USCALED;
  83
  84    case PIPE_FORMAT_R32_SNORM:
  85       return BRW_SURFACEFORMAT_R32_SNORM;
  86    case PIPE_FORMAT_R32G32_SNORM:
  87       return BRW_SURFACEFORMAT_R32G32_SNORM;
  88    case PIPE_FORMAT_R32G32B32_SNORM:
  89       return BRW_SURFACEFORMAT_R32G32B32_SNORM;
  90    case PIPE_FORMAT_R32G32B32A32_SNORM:
  91       return BRW_SURFACEFORMAT_R32G32B32A32_SNORM;
  92
  93    case PIPE_FORMAT_R32_SSCALED:
  94       return BRW_SURFACEFORMAT_R32_SSCALED;
  95    case PIPE_FORMAT_R32G32_SSCALED:
  96       return BRW_SURFACEFORMAT_R32G32_SSCALED;
  97    case PIPE_FORMAT_R32G32B32_SSCALED:
  98       return BRW_SURFACEFORMAT_R32G32B32_SSCALED;
  99    case PIPE_FORMAT_R32G32B32A32_SSCALED:
 100       return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED;
 101
 102    case PIPE_FORMAT_R16_UNORM:
 103       return BRW_SURFACEFORMAT_R16_UNORM;
 104    case PIPE_FORMAT_R16G16_UNORM:
 105       return BRW_SURFACEFORMAT_R16G16_UNORM;
 106    case PIPE_FORMAT_R16G16B16_UNORM:
 107       return BRW_SURFACEFORMAT_R16G16B16_UNORM;
 108    case PIPE_FORMAT_R16G16B16A16_UNORM:
 109       return BRW_SURFACEFORMAT_R16G16B16A16_UNORM;
 110
 111    case PIPE_FORMAT_R16_USCALED:
 112       return BRW_SURFACEFORMAT_R16_USCALED;
 113    case PIPE_FORMAT_R16G16_USCALED:
 114       return BRW_SURFACEFORMAT_R16G16_USCALED;
 115    case PIPE_FORMAT_R16G16B16_USCALED:
 116       return BRW_SURFACEFORMAT_R16G16B16_USCALED;
 117    case PIPE_FORMAT_R16G16B16A16_USCALED:
 118       return BRW_SURFACEFORMAT_R16G16B16A16_USCALED;
 119
 120    case PIPE_FORMAT_R16_SNORM:
 121       return BRW_SURFACEFORMAT_R16_SNORM;
 122    case PIPE_FORMAT_R16G16_SNORM:
 123       return BRW_SURFACEFORMAT_R16G16_SNORM;
 124    case PIPE_FORMAT_R16G16B16_SNORM:
 125       return BRW_SURFACEFORMAT_R16G16B16_SNORM;
 126    case PIPE_FORMAT_R16G16B16A16_SNORM:
 127       return BRW_SURFACEFORMAT_R16G16B16A16_SNORM;
 128
 129    case PIPE_FORMAT_R16_SSCALED:
 130       return BRW_SURFACEFORMAT_R16_SSCALED;
 131    case PIPE_FORMAT_R16G16_SSCALED:
 132       return BRW_SURFACEFORMAT_R16G16_SSCALED;
 133    case PIPE_FORMAT_R16G16B16_SSCALED:
 134       return BRW_SURFACEFORMAT_R16G16B16_SSCALED;
 135    case PIPE_FORMAT_R16G16B16A16_SSCALED:
 136       return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED;
 137
 138    case PIPE_FORMAT_R8_UNORM:
 139       return BRW_SURFACEFORMAT_R8_UNORM;
 140    case PIPE_FORMAT_R8G8_UNORM:
 141       return BRW_SURFACEFORMAT_R8G8_UNORM;
 142    case PIPE_FORMAT_R8G8B8_UNORM:
 143       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
 144    case PIPE_FORMAT_R8G8B8A8_UNORM:
 145       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 146
 147    case PIPE_FORMAT_R8_USCALED:
 148       return BRW_SURFACEFORMAT_R8_USCALED;
 149    case PIPE_FORMAT_R8G8_USCALED:
 150       return BRW_SURFACEFORMAT_R8G8_USCALED;
 151    case PIPE_FORMAT_R8G8B8_USCALED:
 152       return BRW_SURFACEFORMAT_R8G8B8_USCALED;
 153    case PIPE_FORMAT_R8G8B8A8_USCALED:
 154       return BRW_SURFACEFORMAT_R8G8B8A8_USCALED;
 155
 156    case PIPE_FORMAT_R8_SNORM:
 157       return BRW_SURFACEFORMAT_R8_SNORM;
 158    case PIPE_FORMAT_R8G8_SNORM:
 159       return BRW_SURFACEFORMAT_R8G8_SNORM;
 160    case PIPE_FORMAT_R8G8B8_SNORM:
 161       return BRW_SURFACEFORMAT_R8G8B8_SNORM;
 162    case PIPE_FORMAT_R8G8B8A8_SNORM:
 163       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 164
 165    case PIPE_FORMAT_R8_SSCALED:
 166       return BRW_SURFACEFORMAT_R8_SSCALED;
 167    case PIPE_FORMAT_R8G8_SSCALED:
 168       return BRW_SURFACEFORMAT_R8G8_SSCALED;
 169    case PIPE_FORMAT_R8G8B8_SSCALED:
 170       return BRW_SURFACEFORMAT_R8G8B8_SSCALED;
 171    case PIPE_FORMAT_R8G8B8A8_SSCALED:
 172       return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED;
 173
 174    default:
 175       assert(0);
 176       return 0;
 177    }
 178 }
 179
 180 static unsigned get_index_type(int type)
 181 {
 182    switch (type) {
 183    case 1: return BRW_INDEX_BYTE;
 184    case 2: return BRW_INDEX_WORD;
 185    case 4: return BRW_INDEX_DWORD;
 186    default: assert(0); return 0;
 187    }
 188 }
 189
 190
 191
 192 static boolean brw_prepare_vertices(struct brw_context *brw)
 193 {
 194    GLcontext *ctx = &brw->intel.ctx;
 195    struct intel_context *intel = intel_context(ctx);
 196    GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
 197    GLuint i;
 198    const unsigned char *ptr = NULL;
 199    GLuint interleave = 0;
 200    unsigned int min_index = brw->vb.min_index;
 201    unsigned int max_index = brw->vb.max_index;
 202
 203    struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
 204    GLuint nr_uploads = 0;
 205
 206    /* First build an array of pointers to ve's in vb.inputs_read
 207     */
 208    if (0)
 209       _mesa_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
 210
 211
 212
 213    for (i = 0; i < brw->vb.nr_enabled; i++) {
 214       struct brw_vertex_element *input = brw->vb.enabled[i];
 215
 216       input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
 217
 218       if (brw_is_user_buffer(vb)) {
 219          u_upload_buffer( brw->upload,
 220                           min_index * vb->stride,
 221                           (max_index + 1 - min_index) * vb->stride,
 222                           &offset,
 223                           &buffer );
 224       }
 225       else
 226       {
 227          offset = 0;
 228          buffer = vb->buffer;
 229          count = stride == 0 ? 1 : max_index + 1 - min_index;
 230       }
 231
 232       /* Named buffer object: Just reference its contents directly. */
 233       dri_bo_unreference(input->bo);
 234       input->bo = intel_bufferobj_buffer(intel, intel_buffer,
 235                                          INTEL_READ);
 236       dri_bo_reference(input->bo);
 237
 238       input->offset = (unsigned long)offset;
 239       input->stride = vb->stride;
 240       input->count = count;
 241
 242       assert(input->offset < input->bo->size);
 243    }
 244
 245    brw_prepare_query_begin(brw);
 246
 247    for (i = 0; i < brw->vb.nr_enabled; i++) {
 248       struct brw_vertex_element *input = brw->vb.enabled[i];
 249
 250       brw_add_validated_bo(brw, input->bo);
 251    }
 252 }
 253
 254 static void brw_emit_vertices(struct brw_context *brw)
 255 {
 256    GLcontext *ctx = &brw->intel.ctx;
 257    struct intel_context *intel = intel_context(ctx);
 258    GLuint i;
 259
 260    brw_emit_query_begin(brw);
 261
 262    /* If the VS doesn't read any inputs (calculating vertex position from
 263     * a state variable for some reason, for example), emit a single pad
 264     * VERTEX_ELEMENT struct and bail.
 265     *
 266     * The stale VB state stays in place, but they don't do anything unless
 267     * a VE loads from them.
 268     */
 269    if (brw->vb.nr_enabled == 0) {
 270       BEGIN_BATCH(3, IGNORE_CLIPRECTS);
 271       OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
 272       OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
 273                 BRW_VE0_VALID |
 274                 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 275                 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 276       OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 277                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 278                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 279                 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
 280       ADVANCE_BATCH();
 281       return;
 282    }
 283
 284    /* Now emit VB and VEP state packets.
 285     *
 286     * This still defines a hardware VB for each input, even if they
 287     * are interleaved or from the same VBO.  TBD if this makes a
 288     * performance difference.
 289     */
 290    BEGIN_BATCH(1 + brw->vb.nr_enabled * 4, IGNORE_CLIPRECTS);
 291    OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
 292              ((1 + brw->vb.nr_enabled * 4) - 2));
 293
 294    for (i = 0; i < brw->vb.nr_enabled; i++) {
 295       struct brw_vertex_element *input = brw->vb.enabled[i];
 296
 297       OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
 298                 BRW_VB0_ACCESS_VERTEXDATA |
 299                 (input->stride << BRW_VB0_PITCH_SHIFT));
 300       OUT_RELOC(input->bo,
 301                 I915_GEM_DOMAIN_VERTEX, 0,
 302                 input->offset);
 303       if (BRW_IS_IGDNG(brw)) {
 304           if (input->stride) {
 305               OUT_RELOC(input->bo,
 306                         I915_GEM_DOMAIN_VERTEX, 0,
 307                         input->offset + input->stride * input->count - 1);
 308           } else {
 309               assert(input->count == 1);
 310               OUT_RELOC(input->bo,
 311                         I915_GEM_DOMAIN_VERTEX, 0,
 312                         input->offset + input->element_size - 1);
 313           }
 314       } else
 315           OUT_BATCH(input->stride ? input->count : 0);
 316       OUT_BATCH(0); /* Instance data step rate */
 317    }
 318    ADVANCE_BATCH();
 319
 320    BEGIN_BATCH(1 + brw->vb.nr_enabled * 2, IGNORE_CLIPRECTS);
 321    OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2));
 322    for (i = 0; i < brw->vb.nr_enabled; i++) {
 323       struct brw_vertex_element *input = brw->vb.enabled[i];
 324       uint32_t format = get_surface_type(input->glarray->Type,
 325                                          input->glarray->Size,
 326                                          input->glarray->Format,
 327                                          input->glarray->Normalized);
 328       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
 329       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
 330       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
 331       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
 332
 333       switch (input->glarray->Size) {
 334       case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
 335       case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
 336       case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
 337       case 3: comp3 = BRW_VE1_COMPONENT_STORE_1_FLT;
 338          break;
 339       }
 340
 341       OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
 342                 BRW_VE0_VALID |
 343                 (format << BRW_VE0_FORMAT_SHIFT) |
 344                 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 345
 346       if (BRW_IS_IGDNG(brw))
 347           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 348                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 349                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 350                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
 351       else
 352           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 353                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 354                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 355                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
 356                     ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
 357    }
 358    ADVANCE_BATCH();
 359 }
 360
 361 const struct brw_tracked_state brw_vertices = {
 362    .dirty = {
 363       .mesa = 0,
 364       .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
 365       .cache = 0,
 366    },
 367    .prepare = brw_prepare_vertices,
 368    .emit = brw_emit_vertices,
 369 };
 370
 371 static void brw_prepare_indices(struct brw_context *brw)
 372 {
 373    GLcontext *ctx = &brw->intel.ctx;
 374    struct intel_context *intel = &brw->intel;
 375    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 376    GLuint ib_size;
 377    dri_bo *bo = NULL;
 378    struct gl_buffer_object *bufferobj;
 379    GLuint offset;
 380    GLuint ib_type_size;
 381
 382    if (index_buffer == NULL)
 383       return;
 384
 385    ib_type_size = get_size(index_buffer->type);
 386    ib_size = ib_type_size * index_buffer->count;
 387    bufferobj = index_buffer->obj;;
 388
 389    /* Turn into a proper VBO:
 390     */
 391    if (!_mesa_is_bufferobj(bufferobj)) {
 392       brw->ib.start_vertex_offset = 0;
 393
 394       /* Get new bufferobj, offset:
 395        */
 396       get_space(brw, ib_size, &bo, &offset);
 397
 398       /* Straight upload
 399        */
 400       brw_bo_subdata(bo, offset, ib_size, index_buffer->ptr);
 401
 402    } else {
 403       offset = (GLuint) (unsigned long) index_buffer->ptr;
 404       brw->ib.start_vertex_offset = 0;
 405
 406       /* If the index buffer isn't aligned to its element size, we have to
 407        * rebase it into a temporary.
 408        */
 409        if ((get_size(index_buffer->type) - 1) & offset) {
 410            GLubyte *map = ctx->Driver.MapBuffer(ctx,
 411                                                 GL_ELEMENT_ARRAY_BUFFER_ARB,
 412                                                 GL_DYNAMIC_DRAW_ARB,
 413                                                 bufferobj);
 414            map += offset;
 415
 416            get_space(brw, ib_size, &bo, &offset);
 417
 418            dri_bo_subdata(bo, offset, ib_size, map);
 419
 420            ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
 421        } else {
 422           bo = intel_bufferobj_buffer(intel, intel_buffer_object(bufferobj),
 423                                       INTEL_READ);
 424           dri_bo_reference(bo);
 425
 426           /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading
 427            * the index buffer state when we're just moving the start index
 428            * of our drawing.
 429            */
 430           brw->ib.start_vertex_offset = offset / ib_type_size;
 431           offset = 0;
 432           ib_size = bo->size;
 433        }
 434    }
 435
 436    if (brw->ib.bo != bo ||
 437        brw->ib.offset != offset ||
 438        brw->ib.size != ib_size)
 439    {
 440       drm_intel_bo_unreference(brw->ib.bo);
 441       brw->ib.bo = bo;
 442       brw->ib.offset = offset;
 443       brw->ib.size = ib_size;
 444
 445       brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
 446    } else {
 447       drm_intel_bo_unreference(bo);
 448    }
 449
 450    brw_add_validated_bo(brw, brw->ib.bo);
 451 }
 452
 453 const struct brw_tracked_state brw_indices = {
 454    .dirty = {
 455       .mesa = 0,
 456       .brw = BRW_NEW_INDICES,
 457       .cache = 0,
 458    },
 459    .prepare = brw_prepare_indices,
 460 };
 461
 462 static void brw_emit_index_buffer(struct brw_context *brw)
 463 {
 464    struct intel_context *intel = &brw->intel;
 465    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 466
 467    if (index_buffer == NULL)
 468       return;
 469
 470    /* Emit the indexbuffer packet:
 471     */
 472    {
 473       struct brw_indexbuffer ib;
 474
 475       memset(&ib, 0, sizeof(ib));
 476
 477       ib.header.bits.opcode = CMD_INDEX_BUFFER;
 478       ib.header.bits.length = sizeof(ib)/4 - 2;
 479       ib.header.bits.index_format = get_index_type(index_buffer->type);
 480       ib.header.bits.cut_index_enable = 0;
 481
 482       BEGIN_BATCH(4, IGNORE_CLIPRECTS);
 483       OUT_BATCH( ib.header.dword );
 484       OUT_RELOC(brw->ib.bo,
 485                 I915_GEM_DOMAIN_VERTEX, 0,
 486                 brw->ib.offset);
 487       OUT_RELOC(brw->ib.bo,
 488                 I915_GEM_DOMAIN_VERTEX, 0,
 489                 brw->ib.offset + brw->ib.size - 1);
 490       OUT_BATCH( 0 );
 491       ADVANCE_BATCH();
 492    }
 493 }
 494
 495 const struct brw_tracked_state brw_index_buffer = {
 496    .dirty = {
 497       .mesa = 0,
 498       .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
 499       .cache = 0,
 500    },
 501    .emit = brw_emit_index_buffer,
 502 };