src/gallium/drivers/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_debug.h"
  35 #include "brw_batchbuffer.h"
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_screen.h"
  40 #include "brw_pipe_rast.h"
  41
  42
  43
  44
  45
  46 /***********************************************************************
  47  * Blend color
  48  */
  49
  50 static int upload_blend_constant_color(struct brw_context *brw)
  51 {
  52    BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bcc);
  53    return 0;
  54 }
  55
  56
  57 const struct brw_tracked_state brw_blend_constant_color = {
  58    .dirty = {
  59       .mesa = PIPE_NEW_BLEND_COLOR,
  60       .brw = 0,
  61       .cache = 0
  62    },
  63    .emit = upload_blend_constant_color
  64 };
  65
  66 /***********************************************************************
  67  * Drawing rectangle - framebuffer dimensions
  68  */
  69 static int upload_drawing_rect(struct brw_context *brw)
  70 {
  71    BEGIN_BATCH(4, NO_LOOP_CLIPRECTS);
  72    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  73    OUT_BATCH(0);
  74    OUT_BATCH(((brw->curr.fb.width - 1) & 0xffff) |
  75             ((brw->curr.fb.height - 1) << 16));
  76    OUT_BATCH(0);
  77    ADVANCE_BATCH();
  78    return 0;
  79 }
  80
  81 const struct brw_tracked_state brw_drawing_rect = {
  82    .dirty = {
  83       .mesa = PIPE_NEW_FRAMEBUFFER_DIMENSIONS,
  84       .brw = 0,
  85       .cache = 0
  86    },
  87    .emit = upload_drawing_rect
  88 };
  89
  90
  91 /***********************************************************************
  92  * Binding table pointers
  93  */
  94
  95 static int prepare_binding_table_pointers(struct brw_context *brw)
  96 {
  97    brw_add_validated_bo(brw, brw->vs.bind_bo);
  98    brw_add_validated_bo(brw, brw->wm.bind_bo);
  99    return 0;
 100 }
 101
 102 /**
 103  * Upload the binding table pointers, which point each stage's array of surface
 104  * state pointers.
 105  *
 106  * The binding table pointers are relative to the surface state base address,
 107  * which is 0.
 108  */
 109 static int upload_binding_table_pointers(struct brw_context *brw)
 110 {
 111    BEGIN_BATCH(6, IGNORE_CLIPRECTS);
 112    OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
 113    if (brw->vs.bind_bo != NULL)
 114       OUT_RELOC(brw->vs.bind_bo,
 115                 BRW_USAGE_SAMPLER,
 116                 0); /* vs */
 117    else
 118       OUT_BATCH(0);
 119    OUT_BATCH(0); /* gs */
 120    OUT_BATCH(0); /* clip */
 121    OUT_BATCH(0); /* sf */
 122    OUT_RELOC(brw->wm.bind_bo,
 123              BRW_USAGE_SAMPLER,
 124              0); /* wm/ps */
 125    ADVANCE_BATCH();
 126    return 0;
 127 }
 128
 129 const struct brw_tracked_state brw_binding_table_pointers = {
 130    .dirty = {
 131       .mesa = 0,
 132       .brw = BRW_NEW_BATCH,
 133       .cache = CACHE_NEW_SURF_BIND,
 134    },
 135    .prepare = prepare_binding_table_pointers,
 136    .emit = upload_binding_table_pointers,
 137 };
 138
 139
 140 /**********************************************************************
 141  * Upload pointers to the per-stage state.
 142  *
 143  * The state pointers in this packet are all relative to the general state
 144  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 145  */
 146 static int upload_pipelined_state_pointers(struct brw_context *brw )
 147 {
 148    BEGIN_BATCH(7, IGNORE_CLIPRECTS);
 149    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
 150    OUT_RELOC(brw->vs.state_bo,
 151              BRW_USAGE_STATE,
 152              0);
 153    if (brw->gs.prog_active)
 154       OUT_RELOC(brw->gs.state_bo,
 155                 BRW_USAGE_STATE,
 156                 1);
 157    else
 158       OUT_BATCH(0);
 159    OUT_RELOC(brw->clip.state_bo,
 160              BRW_USAGE_STATE,
 161              1);
 162    OUT_RELOC(brw->sf.state_bo,
 163              BRW_USAGE_STATE,
 164              0);
 165    OUT_RELOC(brw->wm.state_bo,
 166              BRW_USAGE_STATE,
 167              0);
 168    OUT_RELOC(brw->cc.state_bo,
 169              BRW_USAGE_STATE,
 170              0);
 171    ADVANCE_BATCH();
 172
 173    brw->state.dirty.brw |= BRW_NEW_PSP;
 174    return 0;
 175 }
 176
 177
 178 static int prepare_psp_urb_cbs(struct brw_context *brw)
 179 {
 180    brw_add_validated_bo(brw, brw->vs.state_bo);
 181    brw_add_validated_bo(brw, brw->gs.state_bo);
 182    brw_add_validated_bo(brw, brw->clip.state_bo);
 183    brw_add_validated_bo(brw, brw->sf.state_bo);
 184    brw_add_validated_bo(brw, brw->wm.state_bo);
 185    brw_add_validated_bo(brw, brw->cc.state_bo);
 186    return 0;
 187 }
 188
 189 static int upload_psp_urb_cbs(struct brw_context *brw )
 190 {
 191    int ret;
 192
 193    ret = upload_pipelined_state_pointers(brw);
 194    if (ret)
 195       return ret;
 196
 197    ret = brw_upload_urb_fence(brw);
 198    if (ret)
 199       return ret;
 200
 201    ret = brw_upload_cs_urb_state(brw);
 202    if (ret)
 203       return ret;
 204
 205    return 0;
 206 }
 207
 208 const struct brw_tracked_state brw_psp_urb_cbs = {
 209    .dirty = {
 210       .mesa = 0,
 211       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 212       .cache = (CACHE_NEW_VS_UNIT |
 213                 CACHE_NEW_GS_UNIT |
 214                 CACHE_NEW_GS_PROG |
 215                 CACHE_NEW_CLIP_UNIT |
 216                 CACHE_NEW_SF_UNIT |
 217                 CACHE_NEW_WM_UNIT |
 218                 CACHE_NEW_CC_UNIT)
 219    },
 220    .prepare = prepare_psp_urb_cbs,
 221    .emit = upload_psp_urb_cbs,
 222 };
 223
 224
 225 /***********************************************************************
 226  * Depth buffer
 227  */
 228
 229 static int prepare_depthbuffer(struct brw_context *brw)
 230 {
 231    struct pipe_surface *zsbuf = brw->curr.fb.zsbuf;
 232
 233    if (zsbuf)
 234       brw_add_validated_bo(brw, brw_surface_bo(zsbuf));
 235
 236    return 0;
 237 }
 238
 239 static int emit_depthbuffer(struct brw_context *brw)
 240 {
 241    struct pipe_surface *surface = brw->curr.fb.zsbuf;
 242    unsigned int len = (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? 6 : 5;
 243
 244    if (surface == NULL) {
 245       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
 246       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 247       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 248                 (BRW_SURFACE_NULL << 29));
 249       OUT_BATCH(0);
 250       OUT_BATCH(0);
 251       OUT_BATCH(0);
 252
 253       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 254          OUT_BATCH(0);
 255
 256       ADVANCE_BATCH();
 257    } else {
 258       struct brw_winsys_buffer *bo;
 259       unsigned int format;
 260       unsigned int pitch;
 261       unsigned int cpp;
 262
 263       switch (surface->format) {
 264       case PIPE_FORMAT_Z16_UNORM:
 265          format = BRW_DEPTHFORMAT_D16_UNORM;
 266          cpp = 2;
 267          break;
 268       case PIPE_FORMAT_Z24S8_UNORM:
 269          format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 270          cpp = 4;
 271          break;
 272       case PIPE_FORMAT_Z32_FLOAT:
 273          format = BRW_DEPTHFORMAT_D32_FLOAT;
 274          cpp = 4;
 275          break;
 276       default:
 277          assert(0);
 278          return PIPE_ERROR_BAD_INPUT;
 279       }
 280
 281       bo = brw_surface_bo(surface);
 282       pitch = brw_surface_pitch(surface);
 283
 284       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
 285       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 286       OUT_BATCH(((pitch * cpp) - 1) |
 287                 (format << 18) |
 288                 (BRW_TILEWALK_YMAJOR << 26) |
 289                 ((surface->layout != PIPE_SURFACE_LAYOUT_LINEAR) << 27) |
 290                 (BRW_SURFACE_2D << 29));
 291       OUT_RELOC(bo,
 292                 BRW_USAGE_DEPTH_BUFFER,
 293                 surface->offset);
 294       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 295                 ((pitch - 1) << 6) |
 296                 ((surface->height - 1) << 19));
 297       OUT_BATCH(0);
 298
 299       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 300          OUT_BATCH(0);
 301
 302       ADVANCE_BATCH();
 303    }
 304
 305    return 0;
 306 }
 307
 308 const struct brw_tracked_state brw_depthbuffer = {
 309    .dirty = {
 310       .mesa = PIPE_NEW_DEPTH_BUFFER,
 311       .brw = BRW_NEW_BATCH,
 312       .cache = 0,
 313    },
 314    .prepare = prepare_depthbuffer,
 315    .emit = emit_depthbuffer,
 316 };
 317
 318
 319
 320 /***********************************************************************
 321  * Polygon stipple packet
 322  */
 323
 324 static int upload_polygon_stipple(struct brw_context *brw)
 325 {
 326    BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bps);
 327    return 0;
 328 }
 329
 330 const struct brw_tracked_state brw_polygon_stipple = {
 331    .dirty = {
 332       .mesa = PIPE_NEW_POLYGON_STIPPLE,
 333       .brw = 0,
 334       .cache = 0
 335    },
 336    .emit = upload_polygon_stipple
 337 };
 338
 339
 340 /***********************************************************************
 341  * Line stipple packet
 342  */
 343
 344 static int upload_line_stipple(struct brw_context *brw)
 345 {
 346    const struct brw_line_stipple *bls = &brw->curr.rast->bls;
 347    BRW_CACHED_BATCH_STRUCT(brw, bls);
 348    return 0;
 349 }
 350
 351 const struct brw_tracked_state brw_line_stipple = {
 352    .dirty = {
 353       .mesa = PIPE_NEW_RAST,
 354       .brw = 0,
 355       .cache = 0
 356    },
 357    .emit = upload_line_stipple
 358 };
 359
 360
 361 /***********************************************************************
 362  * Misc invarient state packets
 363  */
 364
 365 static int upload_invarient_state( struct brw_context *brw )
 366 {
 367    {
 368       /* 0x61040000  Pipeline Select */
 369       /*     PipelineSelect            : 0 */
 370       struct brw_pipeline_select ps;
 371
 372       memset(&ps, 0, sizeof(ps));
 373       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 374          ps.header.opcode = CMD_PIPELINE_SELECT_GM45;
 375       else
 376          ps.header.opcode = CMD_PIPELINE_SELECT_965;
 377       ps.header.pipeline_select = 0;
 378       BRW_BATCH_STRUCT(brw, &ps);
 379    }
 380
 381    {
 382       struct brw_global_depth_offset_clamp gdo;
 383       memset(&gdo, 0, sizeof(gdo));
 384
 385       /* Disable depth offset clamping.
 386        */
 387       gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP;
 388       gdo.header.length = sizeof(gdo)/4 - 2;
 389       gdo.depth_offset_clamp = 0.0;
 390
 391       BRW_BATCH_STRUCT(brw, &gdo);
 392    }
 393
 394
 395    /* 0x61020000  State Instruction Pointer */
 396    {
 397       struct brw_system_instruction_pointer sip;
 398       memset(&sip, 0, sizeof(sip));
 399
 400       sip.header.opcode = CMD_STATE_INSN_POINTER;
 401       sip.header.length = 0;
 402       sip.bits0.pad = 0;
 403       sip.bits0.system_instruction_pointer = 0;
 404       BRW_BATCH_STRUCT(brw, &sip);
 405    }
 406
 407
 408    {
 409       struct brw_vf_statistics vfs;
 410       memset(&vfs, 0, sizeof(vfs));
 411
 412       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 413          vfs.opcode = CMD_VF_STATISTICS_GM45;
 414       else
 415          vfs.opcode = CMD_VF_STATISTICS_965;
 416
 417       if (BRW_DEBUG & DEBUG_STATS)
 418          vfs.statistics_enable = 1;
 419
 420       BRW_BATCH_STRUCT(brw, &vfs);
 421    }
 422
 423    if (!BRW_IS_965(brw))
 424    {
 425       struct brw_aa_line_parameters balp;
 426
 427       /* use legacy aa line coverage computation */
 428       memset(&balp, 0, sizeof(balp));
 429       balp.header.opcode = CMD_AA_LINE_PARAMETERS;
 430       balp.header.length = sizeof(balp) / 4 - 2;
 431
 432       BRW_BATCH_STRUCT(brw, &balp);
 433    }
 434
 435    {
 436       struct brw_polygon_stipple_offset bpso;
 437
 438       /* This is invarient state in gallium:
 439        */
 440       memset(&bpso, 0, sizeof(bpso));
 441       bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
 442       bpso.header.length = sizeof(bpso)/4-2;
 443       bpso.bits0.y_offset = 0;
 444       bpso.bits0.x_offset = 0;
 445
 446       BRW_BATCH_STRUCT(brw, &bpso);
 447    }
 448
 449    return 0;
 450 }
 451
 452 const struct brw_tracked_state brw_invarient_state = {
 453    .dirty = {
 454       .mesa = 0,
 455       .brw = BRW_NEW_CONTEXT,
 456       .cache = 0
 457    },
 458    .emit = upload_invarient_state
 459 };
 460
 461
 462 /***********************************************************************
 463  * State base address
 464  */
 465
 466 /**
 467  * Define the base addresses which some state is referenced from.
 468  *
 469  * This allows us to avoid having to emit relocations in many places for
 470  * cached state, and instead emit pointers inside of large, mostly-static
 471  * state pools.  This comes at the expense of memory, and more expensive cache
 472  * misses.
 473  */
 474 static int upload_state_base_address( struct brw_context *brw )
 475 {
 476    /* Output the structure (brw_state_base_address) directly to the
 477     * batchbuffer, so we can emit relocations inline.
 478     */
 479    if (BRW_IS_IGDNG(brw)) {
 480        BEGIN_BATCH(8, IGNORE_CLIPRECTS);
 481        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 482        OUT_BATCH(1); /* General state base address */
 483        OUT_BATCH(1); /* Surface state base address */
 484        OUT_BATCH(1); /* Indirect object base address */
 485        OUT_BATCH(1); /* Instruction base address */
 486        OUT_BATCH(1); /* General state upper bound */
 487        OUT_BATCH(1); /* Indirect object upper bound */
 488        OUT_BATCH(1); /* Instruction access upper bound */
 489        ADVANCE_BATCH();
 490    } else {
 491        BEGIN_BATCH(6, IGNORE_CLIPRECTS);
 492        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 493        OUT_BATCH(1); /* General state base address */
 494        OUT_BATCH(1); /* Surface state base address */
 495        OUT_BATCH(1); /* Indirect object base address */
 496        OUT_BATCH(1); /* General state upper bound */
 497        OUT_BATCH(1); /* Indirect object upper bound */
 498        ADVANCE_BATCH();
 499    }
 500    return 0;
 501 }
 502
 503 const struct brw_tracked_state brw_state_base_address = {
 504    .dirty = {
 505       .mesa = 0,
 506       .brw = BRW_NEW_CONTEXT,
 507       .cache = 0,
 508    },
 509    .emit = upload_state_base_address
 510 };