src/gallium/drivers/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_debug.h"
  35 #include "brw_batchbuffer.h"
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_screen.h"
  40
  41
  42
  43
  44
  45 /***********************************************************************
  46  * Blend color
  47  */
  48
  49 static int upload_blend_constant_color(struct brw_context *brw)
  50 {
  51    BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bcc);
  52    return 0;
  53 }
  54
  55
  56 const struct brw_tracked_state brw_blend_constant_color = {
  57    .dirty = {
  58       .mesa = PIPE_NEW_BLEND_COLOR,
  59       .brw = 0,
  60       .cache = 0
  61    },
  62    .emit = upload_blend_constant_color
  63 };
  64
  65 /***********************************************************************
  66  * Drawing rectangle - framebuffer dimensions
  67  */
  68 static int upload_drawing_rect(struct brw_context *brw)
  69 {
  70    BEGIN_BATCH(4, NO_LOOP_CLIPRECTS);
  71    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  72    OUT_BATCH(0);
  73    OUT_BATCH(((brw->curr.fb.width - 1) & 0xffff) |
  74             ((brw->curr.fb.height - 1) << 16));
  75    OUT_BATCH(0);
  76    ADVANCE_BATCH();
  77    return 0;
  78 }
  79
  80 const struct brw_tracked_state brw_drawing_rect = {
  81    .dirty = {
  82       .mesa = PIPE_NEW_FRAMEBUFFER_DIMENSIONS,
  83       .brw = 0,
  84       .cache = 0
  85    },
  86    .emit = upload_drawing_rect
  87 };
  88
  89
  90 /***********************************************************************
  91  * Binding table pointers
  92  */
  93
  94 static int prepare_binding_table_pointers(struct brw_context *brw)
  95 {
  96    brw_add_validated_bo(brw, brw->vs.bind_bo);
  97    brw_add_validated_bo(brw, brw->wm.bind_bo);
  98    return 0;
  99 }
 100
 101 /**
 102  * Upload the binding table pointers, which point each stage's array of surface
 103  * state pointers.
 104  *
 105  * The binding table pointers are relative to the surface state base address,
 106  * which is 0.
 107  */
 108 static int upload_binding_table_pointers(struct brw_context *brw)
 109 {
 110    BEGIN_BATCH(6, IGNORE_CLIPRECTS);
 111    OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
 112    if (brw->vs.bind_bo != NULL)
 113       OUT_RELOC(brw->vs.bind_bo,
 114                 BRW_USAGE_SAMPLER,
 115                 0); /* vs */
 116    else
 117       OUT_BATCH(0);
 118    OUT_BATCH(0); /* gs */
 119    OUT_BATCH(0); /* clip */
 120    OUT_BATCH(0); /* sf */
 121    OUT_RELOC(brw->wm.bind_bo,
 122              BRW_USAGE_SAMPLER,
 123              0); /* wm/ps */
 124    ADVANCE_BATCH();
 125    return 0;
 126 }
 127
 128 const struct brw_tracked_state brw_binding_table_pointers = {
 129    .dirty = {
 130       .mesa = 0,
 131       .brw = BRW_NEW_BATCH,
 132       .cache = CACHE_NEW_SURF_BIND,
 133    },
 134    .prepare = prepare_binding_table_pointers,
 135    .emit = upload_binding_table_pointers,
 136 };
 137
 138
 139 /**********************************************************************
 140  * Upload pointers to the per-stage state.
 141  *
 142  * The state pointers in this packet are all relative to the general state
 143  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 144  */
 145 static int upload_pipelined_state_pointers(struct brw_context *brw )
 146 {
 147    BEGIN_BATCH(7, IGNORE_CLIPRECTS);
 148    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
 149    OUT_RELOC(brw->vs.state_bo,
 150              BRW_USAGE_STATE,
 151              0);
 152    if (brw->gs.prog_active)
 153       OUT_RELOC(brw->gs.state_bo,
 154                 BRW_USAGE_STATE,
 155                 1);
 156    else
 157       OUT_BATCH(0);
 158    OUT_RELOC(brw->clip.state_bo,
 159              BRW_USAGE_STATE,
 160              1);
 161    OUT_RELOC(brw->sf.state_bo,
 162              BRW_USAGE_STATE,
 163              0);
 164    OUT_RELOC(brw->wm.state_bo,
 165              BRW_USAGE_STATE,
 166              0);
 167    OUT_RELOC(brw->cc.state_bo,
 168              BRW_USAGE_STATE,
 169              0);
 170    ADVANCE_BATCH();
 171
 172    brw->state.dirty.brw |= BRW_NEW_PSP;
 173    return 0;
 174 }
 175
 176
 177 static int prepare_psp_urb_cbs(struct brw_context *brw)
 178 {
 179    brw_add_validated_bo(brw, brw->vs.state_bo);
 180    brw_add_validated_bo(brw, brw->gs.state_bo);
 181    brw_add_validated_bo(brw, brw->clip.state_bo);
 182    brw_add_validated_bo(brw, brw->sf.state_bo);
 183    brw_add_validated_bo(brw, brw->wm.state_bo);
 184    brw_add_validated_bo(brw, brw->cc.state_bo);
 185    return 0;
 186 }
 187
 188 static int upload_psp_urb_cbs(struct brw_context *brw )
 189 {
 190    int ret;
 191
 192    ret = upload_pipelined_state_pointers(brw);
 193    if (ret)
 194       return ret;
 195
 196    ret = brw_upload_urb_fence(brw);
 197    if (ret)
 198       return ret;
 199
 200    ret = brw_upload_cs_urb_state(brw);
 201    if (ret)
 202       return ret;
 203
 204    return 0;
 205 }
 206
 207 const struct brw_tracked_state brw_psp_urb_cbs = {
 208    .dirty = {
 209       .mesa = 0,
 210       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 211       .cache = (CACHE_NEW_VS_UNIT |
 212                 CACHE_NEW_GS_UNIT |
 213                 CACHE_NEW_GS_PROG |
 214                 CACHE_NEW_CLIP_UNIT |
 215                 CACHE_NEW_SF_UNIT |
 216                 CACHE_NEW_WM_UNIT |
 217                 CACHE_NEW_CC_UNIT)
 218    },
 219    .prepare = prepare_psp_urb_cbs,
 220    .emit = upload_psp_urb_cbs,
 221 };
 222
 223
 224 /***********************************************************************
 225  * Depth buffer
 226  */
 227
 228 static int prepare_depthbuffer(struct brw_context *brw)
 229 {
 230    struct pipe_surface *zsbuf = brw->curr.fb.zsbuf;
 231
 232    if (zsbuf)
 233       brw_add_validated_bo(brw, brw_surface_bo(zsbuf));
 234
 235    return 0;
 236 }
 237
 238 static int emit_depthbuffer(struct brw_context *brw)
 239 {
 240    struct pipe_surface *surface = brw->curr.fb.zsbuf;
 241    unsigned int len = (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? 6 : 5;
 242
 243    if (surface == NULL) {
 244       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
 245       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 246       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 247                 (BRW_SURFACE_NULL << 29));
 248       OUT_BATCH(0);
 249       OUT_BATCH(0);
 250       OUT_BATCH(0);
 251
 252       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 253          OUT_BATCH(0);
 254
 255       ADVANCE_BATCH();
 256    } else {
 257       struct brw_winsys_buffer *bo;
 258       unsigned int format;
 259       unsigned int pitch;
 260       unsigned int cpp;
 261
 262       switch (surface->format) {
 263       case PIPE_FORMAT_Z16_UNORM:
 264          format = BRW_DEPTHFORMAT_D16_UNORM;
 265          cpp = 2;
 266          break;
 267       case PIPE_FORMAT_Z24S8_UNORM:
 268          format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 269          cpp = 4;
 270          break;
 271       case PIPE_FORMAT_Z32_FLOAT:
 272          format = BRW_DEPTHFORMAT_D32_FLOAT;
 273          cpp = 4;
 274          break;
 275       default:
 276          assert(0);
 277          return PIPE_ERROR_BAD_INPUT;
 278       }
 279
 280       bo = brw_surface_bo(surface);
 281       pitch = brw_surface_pitch(surface);
 282
 283       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
 284       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 285       OUT_BATCH(((pitch * cpp) - 1) |
 286                 (format << 18) |
 287                 (BRW_TILEWALK_YMAJOR << 26) |
 288                 ((surface->layout != PIPE_SURFACE_LAYOUT_LINEAR) << 27) |
 289                 (BRW_SURFACE_2D << 29));
 290       OUT_RELOC(bo,
 291                 BRW_USAGE_DEPTH_BUFFER,
 292                 surface->offset);
 293       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 294                 ((pitch - 1) << 6) |
 295                 ((surface->height - 1) << 19));
 296       OUT_BATCH(0);
 297
 298       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 299          OUT_BATCH(0);
 300
 301       ADVANCE_BATCH();
 302    }
 303
 304    return 0;
 305 }
 306
 307 const struct brw_tracked_state brw_depthbuffer = {
 308    .dirty = {
 309       .mesa = PIPE_NEW_DEPTH_BUFFER,
 310       .brw = BRW_NEW_BATCH,
 311       .cache = 0,
 312    },
 313    .prepare = prepare_depthbuffer,
 314    .emit = emit_depthbuffer,
 315 };
 316
 317
 318
 319 /***********************************************************************
 320  * Polygon stipple packet
 321  */
 322
 323 static int upload_polygon_stipple(struct brw_context *brw)
 324 {
 325    BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bps);
 326    return 0;
 327 }
 328
 329 const struct brw_tracked_state brw_polygon_stipple = {
 330    .dirty = {
 331       .mesa = PIPE_NEW_POLYGON_STIPPLE,
 332       .brw = 0,
 333       .cache = 0
 334    },
 335    .emit = upload_polygon_stipple
 336 };
 337
 338
 339 /***********************************************************************
 340  * Line stipple packet
 341  */
 342
 343 static int upload_line_stipple(struct brw_context *brw)
 344 {
 345    struct brw_line_stipple *bls = NULL; //brw->curr.rast->bls;
 346    BRW_CACHED_BATCH_STRUCT(brw, bls);
 347    return 0;
 348 }
 349
 350 const struct brw_tracked_state brw_line_stipple = {
 351    .dirty = {
 352       .mesa = PIPE_NEW_RAST,
 353       .brw = 0,
 354       .cache = 0
 355    },
 356    .emit = upload_line_stipple
 357 };
 358
 359
 360 /***********************************************************************
 361  * Misc invarient state packets
 362  */
 363
 364 static int upload_invarient_state( struct brw_context *brw )
 365 {
 366    {
 367       /* 0x61040000  Pipeline Select */
 368       /*     PipelineSelect            : 0 */
 369       struct brw_pipeline_select ps;
 370
 371       memset(&ps, 0, sizeof(ps));
 372       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 373          ps.header.opcode = CMD_PIPELINE_SELECT_GM45;
 374       else
 375          ps.header.opcode = CMD_PIPELINE_SELECT_965;
 376       ps.header.pipeline_select = 0;
 377       BRW_BATCH_STRUCT(brw, &ps);
 378    }
 379
 380    {
 381       struct brw_global_depth_offset_clamp gdo;
 382       memset(&gdo, 0, sizeof(gdo));
 383
 384       /* Disable depth offset clamping.
 385        */
 386       gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP;
 387       gdo.header.length = sizeof(gdo)/4 - 2;
 388       gdo.depth_offset_clamp = 0.0;
 389
 390       BRW_BATCH_STRUCT(brw, &gdo);
 391    }
 392
 393
 394    /* 0x61020000  State Instruction Pointer */
 395    {
 396       struct brw_system_instruction_pointer sip;
 397       memset(&sip, 0, sizeof(sip));
 398
 399       sip.header.opcode = CMD_STATE_INSN_POINTER;
 400       sip.header.length = 0;
 401       sip.bits0.pad = 0;
 402       sip.bits0.system_instruction_pointer = 0;
 403       BRW_BATCH_STRUCT(brw, &sip);
 404    }
 405
 406
 407    {
 408       struct brw_vf_statistics vfs;
 409       memset(&vfs, 0, sizeof(vfs));
 410
 411       if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
 412          vfs.opcode = CMD_VF_STATISTICS_GM45;
 413       else
 414          vfs.opcode = CMD_VF_STATISTICS_965;
 415
 416       if (BRW_DEBUG & DEBUG_STATS)
 417          vfs.statistics_enable = 1;
 418
 419       BRW_BATCH_STRUCT(brw, &vfs);
 420    }
 421
 422    if (!BRW_IS_965(brw))
 423    {
 424       struct brw_aa_line_parameters balp;
 425
 426       /* use legacy aa line coverage computation */
 427       memset(&balp, 0, sizeof(balp));
 428       balp.header.opcode = CMD_AA_LINE_PARAMETERS;
 429       balp.header.length = sizeof(balp) / 4 - 2;
 430
 431       BRW_BATCH_STRUCT(brw, &balp);
 432    }
 433
 434    {
 435       struct brw_polygon_stipple_offset bpso;
 436
 437       /* This is invarient state in gallium:
 438        */
 439       memset(&bpso, 0, sizeof(bpso));
 440       bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
 441       bpso.header.length = sizeof(bpso)/4-2;
 442       bpso.bits0.y_offset = 0;
 443       bpso.bits0.x_offset = 0;
 444
 445       BRW_BATCH_STRUCT(brw, &bpso);
 446    }
 447
 448    return 0;
 449 }
 450
 451 const struct brw_tracked_state brw_invarient_state = {
 452    .dirty = {
 453       .mesa = 0,
 454       .brw = BRW_NEW_CONTEXT,
 455       .cache = 0
 456    },
 457    .emit = upload_invarient_state
 458 };
 459
 460
 461 /***********************************************************************
 462  * State base address
 463  */
 464
 465 /**
 466  * Define the base addresses which some state is referenced from.
 467  *
 468  * This allows us to avoid having to emit relocations in many places for
 469  * cached state, and instead emit pointers inside of large, mostly-static
 470  * state pools.  This comes at the expense of memory, and more expensive cache
 471  * misses.
 472  */
 473 static int upload_state_base_address( struct brw_context *brw )
 474 {
 475    /* Output the structure (brw_state_base_address) directly to the
 476     * batchbuffer, so we can emit relocations inline.
 477     */
 478    if (BRW_IS_IGDNG(brw)) {
 479        BEGIN_BATCH(8, IGNORE_CLIPRECTS);
 480        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 481        OUT_BATCH(1); /* General state base address */
 482        OUT_BATCH(1); /* Surface state base address */
 483        OUT_BATCH(1); /* Indirect object base address */
 484        OUT_BATCH(1); /* Instruction base address */
 485        OUT_BATCH(1); /* General state upper bound */
 486        OUT_BATCH(1); /* Indirect object upper bound */
 487        OUT_BATCH(1); /* Instruction access upper bound */
 488        ADVANCE_BATCH();
 489    } else {
 490        BEGIN_BATCH(6, IGNORE_CLIPRECTS);
 491        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 492        OUT_BATCH(1); /* General state base address */
 493        OUT_BATCH(1); /* Surface state base address */
 494        OUT_BATCH(1); /* Indirect object base address */
 495        OUT_BATCH(1); /* General state upper bound */
 496        OUT_BATCH(1); /* Indirect object upper bound */
 497        ADVANCE_BATCH();
 498    }
 499    return 0;
 500 }
 501
 502 const struct brw_tracked_state brw_state_base_address = {
 503    .dirty = {
 504       .mesa = 0,
 505       .brw = BRW_NEW_CONTEXT,
 506       .cache = 0,
 507    },
 508    .emit = upload_state_base_address
 509 };