i965g: more files compiling
[mesa.git] / src / gallium / drivers / i965 / brw_pipe_flush.c
1
2 #include "util/u_upload_mgr.h"
3
4 #include "brw_context.h"
5
6
7 /**
8 * called from brw_batchbuffer_flush and children before sending a
9 * batchbuffer off.
10 */
11 static void brw_finish_batch(struct brw_context *brw)
12 {
13 brw_emit_query_end(brw);
14 }
15
16
17 /**
18 * called from intelFlushBatchLocked
19 */
20 static void brw_new_batch( struct brw_context *brw )
21 {
22 brw->curbe.need_new_bo = GL_TRUE;
23
24 /* Mark all context state as needing to be re-emitted.
25 * This is probably not as severe as on 915, since almost all of our state
26 * is just in referenced buffers.
27 */
28 brw->state.dirty.brw |= BRW_NEW_CONTEXT;
29
30 brw->state.dirty.mesa |= ~0;
31 brw->state.dirty.brw |= ~0;
32 brw->state.dirty.cache |= ~0;
33
34 /* Move to the end of the current upload buffer so that we'll force choosing
35 * a new buffer next time.
36 */
37 u_upload_flush( brw->vb.upload_vertex );
38 u_upload_flush( brw->vb.upload_index );
39
40 }
41
42 /* called from intelWaitForIdle() and intelFlush()
43 *
44 * For now, just flush everything. Could be smarter later.
45 */
46 static GLuint brw_flush_cmd( void )
47 {
48 return ((MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE);
49 }
50
51