i965g: wip
[mesa.git] / src / gallium / drivers / i965 / brw_pipe_flush.c
1
2 /**
3 * called from intel_batchbuffer_flush and children before sending a
4 * batchbuffer off.
5 */
6 static void brw_finish_batch(struct intel_context *intel)
7 {
8 struct brw_context *brw = brw_context(&intel->ctx);
9 brw_emit_query_end(brw);
10 }
11
12
13 /**
14 * called from intelFlushBatchLocked
15 */
16 static void brw_new_batch( struct intel_context *intel )
17 {
18 struct brw_context *brw = brw_context(&intel->ctx);
19
20 /* Check that we didn't just wrap our batchbuffer at a bad time. */
21 assert(!brw->no_batch_wrap);
22
23 brw->curbe.need_new_bo = GL_TRUE;
24
25 /* Mark all context state as needing to be re-emitted.
26 * This is probably not as severe as on 915, since almost all of our state
27 * is just in referenced buffers.
28 */
29 brw->state.dirty.brw |= BRW_NEW_CONTEXT;
30
31 brw->state.dirty.mesa |= ~0;
32 brw->state.dirty.brw |= ~0;
33 brw->state.dirty.cache |= ~0;
34
35 /* Move to the end of the current upload buffer so that we'll force choosing
36 * a new buffer next time.
37 */
38 if (brw->vb.upload.bo != NULL) {
39 dri_bo_unreference(brw->vb.upload.bo);
40 brw->vb.upload.bo = NULL;
41 brw->vb.upload.offset = 0;
42 }
43 }
44
45
46 static void brw_note_fence( struct intel_context *intel, GLuint fence )
47 {
48 brw_context(&intel->ctx)->state.dirty.brw |= BRW_NEW_FENCE;
49 }
50
51 /* called from intelWaitForIdle() and intelFlush()
52 *
53 * For now, just flush everything. Could be smarter later.
54 */
55 static GLuint brw_flush_cmd( void )
56 {
57 struct brw_mi_flush flush;
58 flush.opcode = CMD_MI_FLUSH;
59 flush.pad = 0;
60 flush.flags = BRW_FLUSH_STATE_CACHE;
61 return *(GLuint *)&flush;
62 }
63
64