src/gallium/drivers/i965/brw_reg.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef BRW_REG_H
  29 #define BRW_REG_H
  30
  31 #define CMD_MI                          (0x0 << 29)
  32 #define CMD_2D                          (0x2 << 29)
  33 #define CMD_3D                          (0x3 << 29)
  34
  35 #define MI_NOOP                         (CMD_MI | 0)
  36 #define MI_BATCH_BUFFER_END             (CMD_MI | 0xA << 23)
  37 #define MI_FLUSH                        (CMD_MI | (4 << 23))
  38
  39 #define _3DSTATE_DRAWRECT_INFO_I965     (CMD_3D | (3 << 27) | (1 << 24) | 0x2)
  40
  41 /** @{
  42  *
  43  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
  44  * additional flushing control.
  45  */
  46 #define _3DSTATE_PIPE_CONTROL           (CMD_3D | (3 << 27) | (2 << 24) | 2)
  47 #define PIPE_CONTROL_NO_WRITE           (0 << 14)
  48 #define PIPE_CONTROL_WRITE_IMMEDIATE    (1 << 14)
  49 #define PIPE_CONTROL_WRITE_DEPTH_COUNT  (2 << 14)
  50 #define PIPE_CONTROL_WRITE_TIMESTAMP    (3 << 14)
  51 #define PIPE_CONTROL_DEPTH_STALL        (1 << 13)
  52 #define PIPE_CONTROL_WRITE_FLUSH        (1 << 12)
  53 #define PIPE_CONTROL_INSTRUCTION_FLUSH  (1 << 11)
  54 #define PIPE_CONTROL_INTERRUPT_ENABLE   (1 << 8)
  55 #define PIPE_CONTROL_PPGTT_WRITE        (0 << 2)
  56 #define PIPE_CONTROL_GLOBAL_GTT_WRITE   (1 << 2)
  57
  58 /** @} */
  59
  60 #define XY_SETUP_BLT_CMD                (CMD_2D | (0x01 << 22) | 6)
  61 #define XY_COLOR_BLT_CMD                (CMD_2D | (0x50 << 22) | 4)
  62 #define XY_SRC_COPY_BLT_CMD             (CMD_2D | (0x53 << 22) | 6)
  63
  64 /* BR00 */
  65 #define XY_BLT_WRITE_ALPHA      (1 << 21)
  66 #define XY_BLT_WRITE_RGB        (1 << 20)
  67 #define XY_SRC_TILED            (1 << 15)
  68 #define XY_DST_TILED            (1 << 11)
  69
  70 /* BR13 */
  71 #define BR13_565                (0x1 << 24)
  72 #define BR13_8888               (0x3 << 24)
  73
  74 #define FENCE_LINEAR 0
  75 #define FENCE_XMAJOR 1
  76 #define FENCE_YMAJOR 2
  77
  78
  79
  80 /* PCI IDs
  81  */
  82 #define PCI_CHIP_I965_G                 0x29A2
  83 #define PCI_CHIP_I965_Q                 0x2992
  84 #define PCI_CHIP_I965_G_1               0x2982
  85 #define PCI_CHIP_I946_GZ                0x2972
  86 #define PCI_CHIP_I965_GM                0x2A02
  87 #define PCI_CHIP_I965_GME               0x2A12
  88
  89 #define PCI_CHIP_GM45_GM                0x2A42
  90
  91 #define PCI_CHIP_IGD_E_G                0x2E02
  92 #define PCI_CHIP_Q45_G                  0x2E12
  93 #define PCI_CHIP_G45_G                  0x2E22
  94 #define PCI_CHIP_G41_G                  0x2E32
  95 #define PCI_CHIP_B43_G                  0x2E42
  96 #define PCI_CHIP_B43_G1                 0x2E92
  97
  98 #define PCI_CHIP_ILD_G                  0x0042
  99 #define PCI_CHIP_ILM_G                  0x0046
 100
 101 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102  /* Desktop */
 102 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
 103 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
 104 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106  /* Mobile */
 105 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
 106 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
 107 #define PCI_CHIP_SANDYBRIDGE_S          0x010A  /* Server */
 108
 109 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
 110                                  devid == PCI_CHIP_Q45_G || \
 111                                  devid == PCI_CHIP_G45_G || \
 112                                  devid == PCI_CHIP_G41_G || \
 113                                  devid == PCI_CHIP_B43_G || \
 114                                  devid == PCI_CHIP_B43_G1)
 115 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 116 #define IS_G4X(devid)           (IS_G45(devid) || IS_GM45(devid))
 117
 118 #define IS_GEN4(devid)          (devid == PCI_CHIP_I965_G || \
 119                                  devid == PCI_CHIP_I965_Q || \
 120                                  devid == PCI_CHIP_I965_G_1 || \
 121                                  devid == PCI_CHIP_I965_GM || \
 122                                  devid == PCI_CHIP_I965_GME || \
 123                                  devid == PCI_CHIP_I946_GZ || \
 124                                  IS_G4X(devid))
 125
 126 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 127 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
 128 #define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
 129
 130 #define IS_IRONLAKE(devid)      IS_GEN5(devid)
 131
 132 #define IS_GEN6(devid)          (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
 133                                  devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
 134                                  devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 135                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 136                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 137                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
 138                                  devid == PCI_CHIP_SANDYBRIDGE_S)
 139
 140 #define IS_965(devid)           (IS_GEN4(devid) || \
 141                                  IS_G4X(devid) || \
 142                                  IS_GEN5(devid) || \
 143                                  IS_GEN6(devid))
 144
 145 /* XXX: hacks
 146  */
 147 #define VERT_RESULT_HPOS 0      /* not always true */
 148 #define VERT_RESULT_PSIZ 127    /* disabled */
 149
 150
 151 #endif