src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_string.h"
  32
  33 #include "brw_reg.h"
  34 #include "brw_context.h"
  35 #include "brw_screen.h"
  36 #include "brw_winsys.h"
  37 #include "brw_debug.h"
  38 #include "brw_resource.h"
  39
  40 #ifdef DEBUG
  41 static const struct debug_named_value debug_names[] = {
  42    { "tex",   DEBUG_TEXTURE},
  43    { "state", DEBUG_STATE},
  44    { "ioctl", DEBUG_IOCTL},
  45    { "blit",  DEBUG_BLIT},
  46    { "curbe", DEBUG_CURBE},
  47    { "fall",  DEBUG_FALLBACKS},
  48    { "verb",  DEBUG_VERBOSE},
  49    { "bat",   DEBUG_BATCH},
  50    { "pix",   DEBUG_PIXEL},
  51    { "wins",  DEBUG_WINSYS},
  52    { "min",   DEBUG_MIN_URB},
  53    { "dis",   DEBUG_DISASSEM},
  54    { "sync",  DEBUG_SYNC},
  55    { "prim",  DEBUG_PRIMS },
  56    { "vert",  DEBUG_VERTS },
  57    { "dma",   DEBUG_DMA },
  58    { "san",   DEBUG_SANITY },
  59    { "sleep", DEBUG_SLEEP },
  60    { "stats", DEBUG_STATS },
  61    { "sing",  DEBUG_SINGLE_THREAD },
  62    { "thre",  DEBUG_SINGLE_THREAD },
  63    { "wm",    DEBUG_WM },
  64    { "urb",   DEBUG_URB },
  65    { "vs",    DEBUG_VS },
  66    { NULL,    0 }
  67 };
  68
  69 static const struct debug_named_value dump_names[] = {
  70    { "asm",   DUMP_ASM},
  71    { "state", DUMP_STATE},
  72    { "batch", DUMP_BATCH},
  73    { NULL, 0 }
  74 };
  75
  76 int BRW_DEBUG = 0;
  77 int BRW_DUMP = 0;
  78
  79 #endif
  80
  81
  82 /*
  83  * Probe functions
  84  */
  85
  86
  87 static const char *
  88 brw_get_vendor(struct pipe_screen *screen)
  89 {
  90    return "VMware, Inc.";
  91 }
  92
  93 static const char *
  94 brw_get_name(struct pipe_screen *screen)
  95 {
  96    static char buffer[128];
  97    const char *chipset;
  98
  99    switch (brw_screen(screen)->chipset.pci_id) {
 100    case PCI_CHIP_I965_G:
 101       chipset = "I965_G";
 102       break;
 103    case PCI_CHIP_I965_Q:
 104       chipset = "I965_Q";
 105       break;
 106    case PCI_CHIP_I965_G_1:
 107       chipset = "I965_G_1";
 108       break;
 109    case PCI_CHIP_I946_GZ:
 110       chipset = "I946_GZ";
 111       break;
 112    case PCI_CHIP_I965_GM:
 113       chipset = "I965_GM";
 114       break;
 115    case PCI_CHIP_I965_GME:
 116       chipset = "I965_GME";
 117       break;
 118    case PCI_CHIP_GM45_GM:
 119       chipset = "GM45_GM";
 120       break;
 121    case PCI_CHIP_IGD_E_G:
 122       chipset = "IGD_E_G";
 123       break;
 124    case PCI_CHIP_Q45_G:
 125       chipset = "Q45_G";
 126       break;
 127    case PCI_CHIP_G45_G:
 128       chipset = "G45_G";
 129       break;
 130    case PCI_CHIP_G41_G:
 131       chipset = "G41_G";
 132       break;
 133    case PCI_CHIP_B43_G:
 134       chipset = "B43_G";
 135       break;
 136    case PCI_CHIP_ILD_G:
 137       chipset = "ILD_G";
 138       break;
 139    case PCI_CHIP_ILM_G:
 140       chipset = "ILM_G";
 141       break;
 142    default:
 143       chipset = "unknown";
 144       break;
 145    }
 146
 147    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 148    return buffer;
 149 }
 150
 151 static int
 152 brw_get_param(struct pipe_screen *screen, enum pipe_cap param)
 153 {
 154    switch (param) {
 155    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 156       return 8;
 157    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 158       return 8;
 159    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 160       return 16; /* XXX correct? */
 161    case PIPE_CAP_NPOT_TEXTURES:
 162       return 1;
 163    case PIPE_CAP_TWO_SIDED_STENCIL:
 164       return 1;
 165    case PIPE_CAP_GLSL:
 166       return 0;
 167    case PIPE_CAP_ANISOTROPIC_FILTER:
 168       return 0;
 169    case PIPE_CAP_POINT_SPRITE:
 170       return 0;
 171    case PIPE_CAP_MAX_RENDER_TARGETS:
 172       return 1;
 173    case PIPE_CAP_OCCLUSION_QUERY:
 174       return 0;
 175    case PIPE_CAP_TIMER_QUERY:
 176       return 0;
 177    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 178       return 1;
 179    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 180       return BRW_MAX_TEXTURE_2D_LEVELS;
 181    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 182       return BRW_MAX_TEXTURE_3D_LEVELS;
 183    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 184       return BRW_MAX_TEXTURE_2D_LEVELS;
 185    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 186    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 187       return 1;
 188    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 189    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 190       return 0;
 191    default:
 192       return 0;
 193    }
 194 }
 195
 196 static float
 197 brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param)
 198 {
 199    switch (param) {
 200    case PIPE_CAP_MAX_LINE_WIDTH:
 201       /* fall-through */
 202    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 203       return 7.5;
 204
 205    case PIPE_CAP_MAX_POINT_WIDTH:
 206       /* fall-through */
 207    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 208       return 255.0;
 209
 210    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 211       return 4.0;
 212
 213    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 214       return 16.0;
 215
 216    default:
 217       return 0;
 218    }
 219 }
 220
 221 static boolean
 222 brw_is_format_supported(struct pipe_screen *screen,
 223                          enum pipe_format format,
 224                          enum pipe_texture_target target,
 225                          unsigned sample_count,
 226                          unsigned tex_usage,
 227                          unsigned geom_flags)
 228 {
 229    static const enum pipe_format tex_supported[] = {
 230       PIPE_FORMAT_L8_UNORM,
 231       PIPE_FORMAT_I8_UNORM,
 232       PIPE_FORMAT_A8_UNORM,
 233       PIPE_FORMAT_L16_UNORM,
 234       /*PIPE_FORMAT_I16_UNORM,*/
 235       /*PIPE_FORMAT_A16_UNORM,*/
 236       PIPE_FORMAT_L8A8_UNORM,
 237       PIPE_FORMAT_B5G6R5_UNORM,
 238       PIPE_FORMAT_B5G5R5A1_UNORM,
 239       PIPE_FORMAT_B4G4R4A4_UNORM,
 240       PIPE_FORMAT_B8G8R8X8_UNORM,
 241       PIPE_FORMAT_B8G8R8A8_UNORM,
 242       /* video */
 243       PIPE_FORMAT_UYVY,
 244       PIPE_FORMAT_YUYV,
 245       /* compressed */
 246       /*PIPE_FORMAT_FXT1_RGBA,*/
 247       PIPE_FORMAT_DXT1_RGB,
 248       PIPE_FORMAT_DXT1_RGBA,
 249       PIPE_FORMAT_DXT3_RGBA,
 250       PIPE_FORMAT_DXT5_RGBA,
 251       /* sRGB */
 252       PIPE_FORMAT_A8B8G8R8_SRGB,
 253       PIPE_FORMAT_L8A8_SRGB,
 254       PIPE_FORMAT_L8_SRGB,
 255       PIPE_FORMAT_DXT1_SRGB,
 256       /* depth */
 257       PIPE_FORMAT_Z32_FLOAT,
 258       PIPE_FORMAT_Z24X8_UNORM,
 259       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 260       PIPE_FORMAT_Z16_UNORM,
 261       /* signed */
 262       PIPE_FORMAT_R8G8_SNORM,
 263       PIPE_FORMAT_R8G8B8A8_SNORM,
 264       PIPE_FORMAT_NONE  /* list terminator */
 265    };
 266    static const enum pipe_format render_supported[] = {
 267       PIPE_FORMAT_B8G8R8X8_UNORM,
 268       PIPE_FORMAT_B8G8R8A8_UNORM,
 269       PIPE_FORMAT_B5G6R5_UNORM,
 270       PIPE_FORMAT_NONE  /* list terminator */
 271    };
 272    static const enum pipe_format depth_supported[] = {
 273       PIPE_FORMAT_Z32_FLOAT,
 274       PIPE_FORMAT_Z24X8_UNORM,
 275       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 276       PIPE_FORMAT_Z16_UNORM,
 277       PIPE_FORMAT_NONE  /* list terminator */
 278    };
 279    const enum pipe_format *list;
 280    uint i;
 281
 282    if (sample_count > 1)
 283       return FALSE;
 284
 285    if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
 286       list = depth_supported;
 287    else if (tex_usage & PIPE_BIND_RENDER_TARGET)
 288       list = render_supported;
 289    else
 290       list = tex_supported;
 291
 292    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 293       if (list[i] == format)
 294          return TRUE;
 295    }
 296
 297    return FALSE;
 298 }
 299
 300
 301 /*
 302  * Fence functions
 303  */
 304
 305
 306 static void
 307 brw_fence_reference(struct pipe_screen *screen,
 308                      struct pipe_fence_handle **ptr,
 309                      struct pipe_fence_handle *fence)
 310 {
 311 }
 312
 313 static int
 314 brw_fence_signalled(struct pipe_screen *screen,
 315                      struct pipe_fence_handle *fence,
 316                      unsigned flags)
 317 {
 318    return 0;                    /* XXX shouldn't this be a boolean? */
 319 }
 320
 321 static int
 322 brw_fence_finish(struct pipe_screen *screen,
 323                  struct pipe_fence_handle *fence,
 324                  unsigned flags)
 325 {
 326    return 0;
 327 }
 328
 329
 330 /*
 331  * Generic functions
 332  */
 333
 334
 335 static void
 336 brw_destroy_screen(struct pipe_screen *screen)
 337 {
 338    struct brw_screen *bscreen = brw_screen(screen);
 339
 340    if (bscreen->sws)
 341       bscreen->sws->destroy(bscreen->sws);
 342
 343    FREE(bscreen);
 344 }
 345
 346 /**
 347  * Create a new brw_screen object
 348  */
 349 struct pipe_screen *
 350 brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
 351 {
 352    struct brw_screen *bscreen;
 353    struct brw_chipset chipset;
 354
 355 #ifdef DEBUG
 356    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 357    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 358    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 359
 360    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 361 #endif
 362
 363    memset(&chipset, 0, sizeof chipset);
 364
 365    chipset.pci_id = pci_id;
 366
 367    switch (pci_id) {
 368    case PCI_CHIP_I965_G:
 369    case PCI_CHIP_I965_Q:
 370    case PCI_CHIP_I965_G_1:
 371    case PCI_CHIP_I946_GZ:
 372    case PCI_CHIP_I965_GM:
 373    case PCI_CHIP_I965_GME:
 374       chipset.is_965 = TRUE;
 375       break;
 376
 377    case PCI_CHIP_GM45_GM:
 378    case PCI_CHIP_IGD_E_G:
 379    case PCI_CHIP_Q45_G:
 380    case PCI_CHIP_G45_G:
 381    case PCI_CHIP_G41_G:
 382    case PCI_CHIP_B43_G:
 383       chipset.is_g4x = TRUE;
 384       break;
 385
 386    case PCI_CHIP_ILD_G:
 387    case PCI_CHIP_ILM_G:
 388       chipset.is_igdng = TRUE;
 389       break;
 390
 391    default:
 392       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 393                    __FUNCTION__, pci_id);
 394       return NULL;
 395    }
 396
 397
 398    bscreen = CALLOC_STRUCT(brw_screen);
 399    if (!bscreen)
 400       return NULL;
 401
 402    bscreen->chipset = chipset;
 403    bscreen->sws = sws;
 404    bscreen->base.winsys = NULL;
 405    bscreen->base.destroy = brw_destroy_screen;
 406    bscreen->base.get_name = brw_get_name;
 407    bscreen->base.get_vendor = brw_get_vendor;
 408    bscreen->base.get_param = brw_get_param;
 409    bscreen->base.get_paramf = brw_get_paramf;
 410    bscreen->base.is_format_supported = brw_is_format_supported;
 411    bscreen->base.context_create = brw_create_context;
 412    bscreen->base.fence_reference = brw_fence_reference;
 413    bscreen->base.fence_signalled = brw_fence_signalled;
 414    bscreen->base.fence_finish = brw_fence_finish;
 415
 416    brw_init_screen_resource_functions(bscreen);
 417    brw_screen_tex_surface_init(bscreen);
 418
 419    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 420
 421
 422    return &bscreen->base;
 423 }