1 /**************************************************************************
3 * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "util/u_inlines.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
34 #include "brw_context.h"
35 #include "brw_screen.h"
36 #include "brw_winsys.h"
37 #include "brw_debug.h"
38 #include "brw_resource.h"
41 static const struct debug_named_value debug_names
[] = {
42 { "tex", DEBUG_TEXTURE
, NULL
},
43 { "state", DEBUG_STATE
, NULL
},
44 { "ioctl", DEBUG_IOCTL
, NULL
},
45 { "blit", DEBUG_BLIT
, NULL
},
46 { "curbe", DEBUG_CURBE
, NULL
},
47 { "fall", DEBUG_FALLBACKS
, NULL
},
48 { "verb", DEBUG_VERBOSE
, NULL
},
49 { "bat", DEBUG_BATCH
, NULL
},
50 { "pix", DEBUG_PIXEL
, NULL
},
51 { "wins", DEBUG_WINSYS
, NULL
},
52 { "min", DEBUG_MIN_URB
, NULL
},
53 { "dis", DEBUG_DISASSEM
, NULL
},
54 { "sync", DEBUG_SYNC
, NULL
},
55 { "prim", DEBUG_PRIMS
, NULL
},
56 { "vert", DEBUG_VERTS
, NULL
},
57 { "dma", DEBUG_DMA
, NULL
},
58 { "san", DEBUG_SANITY
, NULL
},
59 { "sleep", DEBUG_SLEEP
, NULL
},
60 { "stats", DEBUG_STATS
, NULL
},
61 { "sing", DEBUG_SINGLE_THREAD
, NULL
},
62 { "thre", DEBUG_SINGLE_THREAD
, NULL
},
63 { "wm", DEBUG_WM
, NULL
},
64 { "urb", DEBUG_URB
, NULL
},
65 { "vs", DEBUG_VS
, NULL
},
69 static const struct debug_named_value dump_names
[] = {
70 { "asm", DUMP_ASM
, NULL
},
71 { "state", DUMP_STATE
, NULL
},
72 { "batch", DUMP_BATCH
, NULL
},
88 brw_get_vendor(struct pipe_screen
*screen
)
90 return "VMware, Inc.";
94 brw_get_name(struct pipe_screen
*screen
)
96 static char buffer
[128];
99 switch (brw_screen(screen
)->chipset
.pci_id
) {
100 case PCI_CHIP_I965_G
:
103 case PCI_CHIP_I965_Q
:
106 case PCI_CHIP_I965_G_1
:
107 chipset
= "I965_G_1";
109 case PCI_CHIP_I946_GZ
:
112 case PCI_CHIP_I965_GM
:
115 case PCI_CHIP_I965_GME
:
116 chipset
= "I965_GME";
118 case PCI_CHIP_GM45_GM
:
121 case PCI_CHIP_IGD_E_G
:
147 util_snprintf(buffer
, sizeof(buffer
), "i965 (chipset: %s)", chipset
);
152 brw_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
155 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
157 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
159 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
160 return 16; /* XXX correct? */
161 case PIPE_CAP_NPOT_TEXTURES
:
163 case PIPE_CAP_TWO_SIDED_STENCIL
:
167 case PIPE_CAP_ANISOTROPIC_FILTER
:
169 case PIPE_CAP_POINT_SPRITE
:
171 case PIPE_CAP_MAX_RENDER_TARGETS
:
173 case PIPE_CAP_OCCLUSION_QUERY
:
175 case PIPE_CAP_TIMER_QUERY
:
177 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
179 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
180 return BRW_MAX_TEXTURE_2D_LEVELS
;
181 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
182 return BRW_MAX_TEXTURE_3D_LEVELS
;
183 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
184 return BRW_MAX_TEXTURE_2D_LEVELS
;
185 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
186 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
188 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
189 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
191 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
192 /* disable for now */
200 brw_get_paramf(struct pipe_screen
*screen
, enum pipe_cap param
)
203 case PIPE_CAP_MAX_LINE_WIDTH
:
205 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
208 case PIPE_CAP_MAX_POINT_WIDTH
:
210 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
213 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
216 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
225 brw_is_format_supported(struct pipe_screen
*screen
,
226 enum pipe_format format
,
227 enum pipe_texture_target target
,
228 unsigned sample_count
,
232 static const enum pipe_format tex_supported
[] = {
233 PIPE_FORMAT_L8_UNORM
,
234 PIPE_FORMAT_I8_UNORM
,
235 PIPE_FORMAT_A8_UNORM
,
236 PIPE_FORMAT_L16_UNORM
,
237 /*PIPE_FORMAT_I16_UNORM,*/
238 /*PIPE_FORMAT_A16_UNORM,*/
239 PIPE_FORMAT_L8A8_UNORM
,
240 PIPE_FORMAT_B5G6R5_UNORM
,
241 PIPE_FORMAT_B5G5R5A1_UNORM
,
242 PIPE_FORMAT_B4G4R4A4_UNORM
,
243 PIPE_FORMAT_B8G8R8X8_UNORM
,
244 PIPE_FORMAT_B8G8R8A8_UNORM
,
249 /*PIPE_FORMAT_FXT1_RGBA,*/
250 PIPE_FORMAT_DXT1_RGB
,
251 PIPE_FORMAT_DXT1_RGBA
,
252 PIPE_FORMAT_DXT3_RGBA
,
253 PIPE_FORMAT_DXT5_RGBA
,
255 PIPE_FORMAT_A8B8G8R8_SRGB
,
256 PIPE_FORMAT_L8A8_SRGB
,
258 PIPE_FORMAT_DXT1_SRGB
,
260 PIPE_FORMAT_Z32_FLOAT
,
261 PIPE_FORMAT_Z24X8_UNORM
,
262 PIPE_FORMAT_Z24_UNORM_S8_USCALED
,
263 PIPE_FORMAT_Z16_UNORM
,
265 PIPE_FORMAT_R8G8_SNORM
,
266 PIPE_FORMAT_R8G8B8A8_SNORM
,
267 PIPE_FORMAT_NONE
/* list terminator */
269 static const enum pipe_format render_supported
[] = {
270 PIPE_FORMAT_B8G8R8X8_UNORM
,
271 PIPE_FORMAT_B8G8R8A8_UNORM
,
272 PIPE_FORMAT_B5G6R5_UNORM
,
273 PIPE_FORMAT_NONE
/* list terminator */
275 static const enum pipe_format depth_supported
[] = {
276 PIPE_FORMAT_Z32_FLOAT
,
277 PIPE_FORMAT_Z24X8_UNORM
,
278 PIPE_FORMAT_Z24_UNORM_S8_USCALED
,
279 PIPE_FORMAT_Z16_UNORM
,
280 PIPE_FORMAT_NONE
/* list terminator */
282 const enum pipe_format
*list
;
285 if (sample_count
> 1)
288 if (tex_usage
& PIPE_BIND_DEPTH_STENCIL
)
289 list
= depth_supported
;
290 else if (tex_usage
& PIPE_BIND_RENDER_TARGET
)
291 list
= render_supported
;
293 list
= tex_supported
;
295 for (i
= 0; list
[i
] != PIPE_FORMAT_NONE
; i
++) {
296 if (list
[i
] == format
)
310 brw_fence_reference(struct pipe_screen
*screen
,
311 struct pipe_fence_handle
**ptr
,
312 struct pipe_fence_handle
*fence
)
317 brw_fence_signalled(struct pipe_screen
*screen
,
318 struct pipe_fence_handle
*fence
,
321 return 0; /* XXX shouldn't this be a boolean? */
325 brw_fence_finish(struct pipe_screen
*screen
,
326 struct pipe_fence_handle
*fence
,
339 brw_destroy_screen(struct pipe_screen
*screen
)
341 struct brw_screen
*bscreen
= brw_screen(screen
);
344 bscreen
->sws
->destroy(bscreen
->sws
);
350 * Create a new brw_screen object
353 brw_create_screen(struct brw_winsys_screen
*sws
)
355 struct brw_screen
*bscreen
;
356 struct brw_chipset chipset
;
359 BRW_DEBUG
= debug_get_flags_option("BRW_DEBUG", debug_names
, 0);
360 BRW_DEBUG
|= debug_get_flags_option("INTEL_DEBUG", debug_names
, 0);
361 BRW_DEBUG
|= DEBUG_STATS
| DEBUG_MIN_URB
| DEBUG_WM
;
363 BRW_DUMP
= debug_get_flags_option("BRW_DUMP", dump_names
, 0);
366 memset(&chipset
, 0, sizeof chipset
);
368 chipset
.pci_id
= sws
->pci_id
;
370 switch (chipset
.pci_id
) {
371 case PCI_CHIP_I965_G
:
372 case PCI_CHIP_I965_Q
:
373 case PCI_CHIP_I965_G_1
:
374 case PCI_CHIP_I946_GZ
:
375 case PCI_CHIP_I965_GM
:
376 case PCI_CHIP_I965_GME
:
377 chipset
.is_965
= TRUE
;
380 case PCI_CHIP_GM45_GM
:
381 case PCI_CHIP_IGD_E_G
:
386 chipset
.is_g4x
= TRUE
;
391 chipset
.is_igdng
= TRUE
;
395 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
396 __FUNCTION__
, chipset
.pci_id
);
401 bscreen
= CALLOC_STRUCT(brw_screen
);
405 bscreen
->chipset
= chipset
;
407 bscreen
->base
.winsys
= NULL
;
408 bscreen
->base
.destroy
= brw_destroy_screen
;
409 bscreen
->base
.get_name
= brw_get_name
;
410 bscreen
->base
.get_vendor
= brw_get_vendor
;
411 bscreen
->base
.get_param
= brw_get_param
;
412 bscreen
->base
.get_paramf
= brw_get_paramf
;
413 bscreen
->base
.is_format_supported
= brw_is_format_supported
;
414 bscreen
->base
.context_create
= brw_create_context
;
415 bscreen
->base
.fence_reference
= brw_fence_reference
;
416 bscreen
->base
.fence_signalled
= brw_fence_signalled
;
417 bscreen
->base
.fence_finish
= brw_fence_finish
;
419 brw_init_screen_resource_functions(bscreen
);
420 brw_screen_tex_surface_init(bscreen
);
422 bscreen
->no_tiling
= debug_get_option("BRW_NO_TILING", FALSE
) != NULL
;
425 return &bscreen
->base
;