src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_string.h"
  32
  33 #include "brw_reg.h"
  34 #include "brw_context.h"
  35 #include "brw_screen.h"
  36 #include "brw_winsys.h"
  37 #include "brw_public.h"
  38 #include "brw_debug.h"
  39 #include "brw_resource.h"
  40
  41 #ifdef DEBUG
  42 static const struct debug_named_value debug_names[] = {
  43    { "tex",   DEBUG_TEXTURE, NULL },
  44    { "state", DEBUG_STATE, NULL },
  45    { "ioctl", DEBUG_IOCTL, NULL },
  46    { "blit",  DEBUG_BLIT, NULL },
  47    { "curbe", DEBUG_CURBE, NULL },
  48    { "fall",  DEBUG_FALLBACKS, NULL },
  49    { "verb",  DEBUG_VERBOSE, NULL },
  50    { "bat",   DEBUG_BATCH, NULL },
  51    { "pix",   DEBUG_PIXEL, NULL },
  52    { "wins",  DEBUG_WINSYS, NULL },
  53    { "min",   DEBUG_MIN_URB, NULL },
  54    { "dis",   DEBUG_DISASSEM, NULL },
  55    { "sync",  DEBUG_SYNC, NULL },
  56    { "prim",  DEBUG_PRIMS, NULL },
  57    { "vert",  DEBUG_VERTS, NULL },
  58    { "dma",   DEBUG_DMA, NULL },
  59    { "san",   DEBUG_SANITY, NULL },
  60    { "sleep", DEBUG_SLEEP, NULL },
  61    { "stats", DEBUG_STATS, NULL },
  62    { "sing",  DEBUG_SINGLE_THREAD, NULL },
  63    { "thre",  DEBUG_SINGLE_THREAD, NULL },
  64    { "wm",    DEBUG_WM, NULL },
  65    { "urb",   DEBUG_URB, NULL },
  66    { "vs",    DEBUG_VS, NULL },
  67    DEBUG_NAMED_VALUE_END
  68 };
  69
  70 static const struct debug_named_value dump_names[] = {
  71    { "asm",   DUMP_ASM, NULL },
  72    { "state", DUMP_STATE, NULL },
  73    { "batch", DUMP_BATCH, NULL },
  74    DEBUG_NAMED_VALUE_END
  75 };
  76
  77 int BRW_DEBUG = 0;
  78 int BRW_DUMP = 0;
  79
  80 #endif
  81
  82
  83 /*
  84  * Probe functions
  85  */
  86
  87
  88 static const char *
  89 brw_get_vendor(struct pipe_screen *screen)
  90 {
  91    return "VMware, Inc.";
  92 }
  93
  94 static const char *
  95 brw_get_name(struct pipe_screen *screen)
  96 {
  97    static char buffer[128];
  98    const char *chipset;
  99
 100    switch (brw_screen(screen)->chipset.pci_id) {
 101    case PCI_CHIP_I965_G:
 102       chipset = "I965_G";
 103       break;
 104    case PCI_CHIP_I965_Q:
 105       chipset = "I965_Q";
 106       break;
 107    case PCI_CHIP_I965_G_1:
 108       chipset = "I965_G_1";
 109       break;
 110    case PCI_CHIP_I946_GZ:
 111       chipset = "I946_GZ";
 112       break;
 113    case PCI_CHIP_I965_GM:
 114       chipset = "I965_GM";
 115       break;
 116    case PCI_CHIP_I965_GME:
 117       chipset = "I965_GME";
 118       break;
 119    case PCI_CHIP_GM45_GM:
 120       chipset = "GM45_GM";
 121       break;
 122    case PCI_CHIP_IGD_E_G:
 123       chipset = "IGD_E_G";
 124       break;
 125    case PCI_CHIP_Q45_G:
 126       chipset = "Q45_G";
 127       break;
 128    case PCI_CHIP_G45_G:
 129       chipset = "G45_G";
 130       break;
 131    case PCI_CHIP_G41_G:
 132       chipset = "G41_G";
 133       break;
 134    case PCI_CHIP_B43_G:
 135       chipset = "B43_G";
 136       break;
 137    case PCI_CHIP_ILD_G:
 138       chipset = "ILD_G";
 139       break;
 140    case PCI_CHIP_ILM_G:
 141       chipset = "ILM_G";
 142       break;
 143    default:
 144       chipset = "unknown";
 145       break;
 146    }
 147
 148    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 149    return buffer;
 150 }
 151
 152 static int
 153 brw_get_param(struct pipe_screen *screen, enum pipe_cap param)
 154 {
 155    switch (param) {
 156    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 157       return 8;
 158    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 159       return 8;
 160    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 161       return 16; /* XXX correct? */
 162    case PIPE_CAP_NPOT_TEXTURES:
 163       return 1;
 164    case PIPE_CAP_TWO_SIDED_STENCIL:
 165       return 1;
 166    case PIPE_CAP_GLSL:
 167       return 0;
 168    case PIPE_CAP_ANISOTROPIC_FILTER:
 169       return 0;
 170    case PIPE_CAP_POINT_SPRITE:
 171       return 0;
 172    case PIPE_CAP_MAX_RENDER_TARGETS:
 173       return 1;
 174    case PIPE_CAP_OCCLUSION_QUERY:
 175       return 0;
 176    case PIPE_CAP_TIMER_QUERY:
 177       return 0;
 178    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 179       return 1;
 180    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 181       return BRW_MAX_TEXTURE_2D_LEVELS;
 182    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 183       return BRW_MAX_TEXTURE_3D_LEVELS;
 184    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 185       return BRW_MAX_TEXTURE_2D_LEVELS;
 186    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 187    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 188       return 1;
 189    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 190    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 191       return 0;
 192    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 193       /* disable for now */
 194       return 0;
 195    default:
 196       return 0;
 197    }
 198 }
 199
 200 static int
 201 brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param)
 202 {
 203    switch(shader) {
 204    case PIPE_SHADER_VERTEX:
 205    case PIPE_SHADER_FRAGMENT:
 206    case PIPE_SHADER_GEOMETRY:
 207       break;
 208    default:
 209       return 0;
 210    }
 211
 212    /* XXX: these are just shader model 4.0 values, fix this! */
 213    switch(param) {
 214       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 215          return 65536;
 216       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 217          return 65536;
 218       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 219          return 65536;
 220       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 221          return 65536;
 222       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 223          return 65536;
 224       case PIPE_SHADER_CAP_MAX_INPUTS:
 225          return 32;
 226       case PIPE_SHADER_CAP_MAX_CONSTS:
 227          return 4096;
 228       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 229          return PIPE_MAX_CONSTANT_BUFFERS;
 230       case PIPE_SHADER_CAP_MAX_TEMPS:
 231          return 4096;
 232       case PIPE_SHADER_CAP_MAX_ADDRS:
 233          return 0;
 234       case PIPE_SHADER_CAP_MAX_PREDS:
 235          return 0;
 236       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 237          return 1;
 238       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 239       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 240       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 241       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 242           return 1;
 243       default:
 244          assert(0);
 245          return 0;
 246       }
 247 }
 248
 249 static float
 250 brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param)
 251 {
 252    switch (param) {
 253    case PIPE_CAP_MAX_LINE_WIDTH:
 254       /* fall-through */
 255    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 256       return 7.5;
 257
 258    case PIPE_CAP_MAX_POINT_WIDTH:
 259       /* fall-through */
 260    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 261       return 255.0;
 262
 263    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 264       return 4.0;
 265
 266    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 267       return 16.0;
 268
 269    default:
 270       return 0;
 271    }
 272 }
 273
 274 static boolean
 275 brw_is_format_supported(struct pipe_screen *screen,
 276                          enum pipe_format format,
 277                          enum pipe_texture_target target,
 278                          unsigned sample_count,
 279                          unsigned tex_usage,
 280                          unsigned geom_flags)
 281 {
 282    static const enum pipe_format tex_supported[] = {
 283       PIPE_FORMAT_L8_UNORM,
 284       PIPE_FORMAT_I8_UNORM,
 285       PIPE_FORMAT_A8_UNORM,
 286       PIPE_FORMAT_L16_UNORM,
 287       /*PIPE_FORMAT_I16_UNORM,*/
 288       /*PIPE_FORMAT_A16_UNORM,*/
 289       PIPE_FORMAT_L8A8_UNORM,
 290       PIPE_FORMAT_B5G6R5_UNORM,
 291       PIPE_FORMAT_B5G5R5A1_UNORM,
 292       PIPE_FORMAT_B4G4R4A4_UNORM,
 293       PIPE_FORMAT_B8G8R8X8_UNORM,
 294       PIPE_FORMAT_B8G8R8A8_UNORM,
 295       /* video */
 296       PIPE_FORMAT_UYVY,
 297       PIPE_FORMAT_YUYV,
 298       /* compressed */
 299       /*PIPE_FORMAT_FXT1_RGBA,*/
 300       PIPE_FORMAT_DXT1_RGB,
 301       PIPE_FORMAT_DXT1_RGBA,
 302       PIPE_FORMAT_DXT3_RGBA,
 303       PIPE_FORMAT_DXT5_RGBA,
 304       /* sRGB */
 305       PIPE_FORMAT_A8B8G8R8_SRGB,
 306       PIPE_FORMAT_L8A8_SRGB,
 307       PIPE_FORMAT_L8_SRGB,
 308       PIPE_FORMAT_DXT1_SRGB,
 309       /* depth */
 310       PIPE_FORMAT_Z32_FLOAT,
 311       PIPE_FORMAT_Z24X8_UNORM,
 312       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 313       PIPE_FORMAT_Z16_UNORM,
 314       /* signed */
 315       PIPE_FORMAT_R8G8_SNORM,
 316       PIPE_FORMAT_R8G8B8A8_SNORM,
 317       PIPE_FORMAT_NONE  /* list terminator */
 318    };
 319    static const enum pipe_format render_supported[] = {
 320       PIPE_FORMAT_B8G8R8X8_UNORM,
 321       PIPE_FORMAT_B8G8R8A8_UNORM,
 322       PIPE_FORMAT_B5G6R5_UNORM,
 323       PIPE_FORMAT_NONE  /* list terminator */
 324    };
 325    static const enum pipe_format depth_supported[] = {
 326       PIPE_FORMAT_Z32_FLOAT,
 327       PIPE_FORMAT_Z24X8_UNORM,
 328       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 329       PIPE_FORMAT_Z16_UNORM,
 330       PIPE_FORMAT_NONE  /* list terminator */
 331    };
 332    const enum pipe_format *list;
 333    uint i;
 334
 335    if (sample_count > 1)
 336       return FALSE;
 337
 338    if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
 339       list = depth_supported;
 340    else if (tex_usage & PIPE_BIND_RENDER_TARGET)
 341       list = render_supported;
 342    else
 343       list = tex_supported;
 344
 345    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 346       if (list[i] == format)
 347          return TRUE;
 348    }
 349
 350    return FALSE;
 351 }
 352
 353
 354 /*
 355  * Fence functions
 356  */
 357
 358
 359 static void
 360 brw_fence_reference(struct pipe_screen *screen,
 361                      struct pipe_fence_handle **ptr,
 362                      struct pipe_fence_handle *fence)
 363 {
 364 }
 365
 366 static int
 367 brw_fence_signalled(struct pipe_screen *screen,
 368                      struct pipe_fence_handle *fence,
 369                      unsigned flags)
 370 {
 371    return 0;                    /* XXX shouldn't this be a boolean? */
 372 }
 373
 374 static int
 375 brw_fence_finish(struct pipe_screen *screen,
 376                  struct pipe_fence_handle *fence,
 377                  unsigned flags)
 378 {
 379    return 0;
 380 }
 381
 382
 383 /*
 384  * Generic functions
 385  */
 386
 387
 388 static void
 389 brw_destroy_screen(struct pipe_screen *screen)
 390 {
 391    struct brw_screen *bscreen = brw_screen(screen);
 392
 393    if (bscreen->sws)
 394       bscreen->sws->destroy(bscreen->sws);
 395
 396    FREE(bscreen);
 397 }
 398
 399 /**
 400  * Create a new brw_screen object
 401  */
 402 struct pipe_screen *
 403 brw_screen_create(struct brw_winsys_screen *sws)
 404 {
 405    struct brw_screen *bscreen;
 406    struct brw_chipset chipset;
 407
 408 #ifdef DEBUG
 409    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 410    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 411    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 412
 413    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 414 #endif
 415
 416    memset(&chipset, 0, sizeof chipset);
 417
 418    chipset.pci_id = sws->pci_id;
 419
 420    switch (chipset.pci_id) {
 421    case PCI_CHIP_I965_G:
 422    case PCI_CHIP_I965_Q:
 423    case PCI_CHIP_I965_G_1:
 424    case PCI_CHIP_I946_GZ:
 425    case PCI_CHIP_I965_GM:
 426    case PCI_CHIP_I965_GME:
 427       chipset.is_965 = TRUE;
 428       break;
 429
 430    case PCI_CHIP_GM45_GM:
 431    case PCI_CHIP_IGD_E_G:
 432    case PCI_CHIP_Q45_G:
 433    case PCI_CHIP_G45_G:
 434    case PCI_CHIP_G41_G:
 435    case PCI_CHIP_B43_G:
 436       chipset.is_g4x = TRUE;
 437       break;
 438
 439    case PCI_CHIP_ILD_G:
 440    case PCI_CHIP_ILM_G:
 441       chipset.is_igdng = TRUE;
 442       break;
 443
 444    default:
 445       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 446                    __FUNCTION__, chipset.pci_id);
 447       return NULL;
 448    }
 449
 450
 451    bscreen = CALLOC_STRUCT(brw_screen);
 452    if (!bscreen)
 453       return NULL;
 454
 455    bscreen->chipset = chipset;
 456    bscreen->sws = sws;
 457    bscreen->base.winsys = NULL;
 458    bscreen->base.destroy = brw_destroy_screen;
 459    bscreen->base.get_name = brw_get_name;
 460    bscreen->base.get_vendor = brw_get_vendor;
 461    bscreen->base.get_param = brw_get_param;
 462    bscreen->base.get_shader_param = brw_get_shader_param;
 463    bscreen->base.get_paramf = brw_get_paramf;
 464    bscreen->base.is_format_supported = brw_is_format_supported;
 465    bscreen->base.context_create = brw_create_context;
 466    bscreen->base.fence_reference = brw_fence_reference;
 467    bscreen->base.fence_signalled = brw_fence_signalled;
 468    bscreen->base.fence_finish = brw_fence_finish;
 469
 470    brw_init_screen_resource_functions(bscreen);
 471    brw_screen_tex_surface_init(bscreen);
 472
 473    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 474
 475
 476    return &bscreen->base;
 477 }