1 /**************************************************************************
3 * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "util/u_inlines.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
34 #include "brw_context.h"
35 #include "brw_screen.h"
36 #include "brw_winsys.h"
37 #include "brw_public.h"
38 #include "brw_debug.h"
39 #include "brw_resource.h"
42 static const struct debug_named_value debug_names
[] = {
43 { "tex", DEBUG_TEXTURE
, NULL
},
44 { "state", DEBUG_STATE
, NULL
},
45 { "ioctl", DEBUG_IOCTL
, NULL
},
46 { "blit", DEBUG_BLIT
, NULL
},
47 { "curbe", DEBUG_CURBE
, NULL
},
48 { "fall", DEBUG_FALLBACKS
, NULL
},
49 { "verb", DEBUG_VERBOSE
, NULL
},
50 { "bat", DEBUG_BATCH
, NULL
},
51 { "pix", DEBUG_PIXEL
, NULL
},
52 { "wins", DEBUG_WINSYS
, NULL
},
53 { "min", DEBUG_MIN_URB
, NULL
},
54 { "dis", DEBUG_DISASSEM
, NULL
},
55 { "sync", DEBUG_SYNC
, NULL
},
56 { "prim", DEBUG_PRIMS
, NULL
},
57 { "vert", DEBUG_VERTS
, NULL
},
58 { "dma", DEBUG_DMA
, NULL
},
59 { "san", DEBUG_SANITY
, NULL
},
60 { "sleep", DEBUG_SLEEP
, NULL
},
61 { "stats", DEBUG_STATS
, NULL
},
62 { "sing", DEBUG_SINGLE_THREAD
, NULL
},
63 { "thre", DEBUG_SINGLE_THREAD
, NULL
},
64 { "wm", DEBUG_WM
, NULL
},
65 { "urb", DEBUG_URB
, NULL
},
66 { "vs", DEBUG_VS
, NULL
},
70 static const struct debug_named_value dump_names
[] = {
71 { "asm", DUMP_ASM
, NULL
},
72 { "state", DUMP_STATE
, NULL
},
73 { "batch", DUMP_BATCH
, NULL
},
89 brw_get_vendor(struct pipe_screen
*screen
)
91 return "VMware, Inc.";
95 brw_get_name(struct pipe_screen
*screen
)
97 static char buffer
[128];
100 switch (brw_screen(screen
)->chipset
.pci_id
) {
101 case PCI_CHIP_I965_G
:
104 case PCI_CHIP_I965_Q
:
107 case PCI_CHIP_I965_G_1
:
108 chipset
= "I965_G_1";
110 case PCI_CHIP_I946_GZ
:
113 case PCI_CHIP_I965_GM
:
116 case PCI_CHIP_I965_GME
:
117 chipset
= "I965_GME";
119 case PCI_CHIP_GM45_GM
:
122 case PCI_CHIP_IGD_E_G
:
148 util_snprintf(buffer
, sizeof(buffer
), "i965 (chipset: %s)", chipset
);
153 brw_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
156 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
158 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
160 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
161 return 16; /* XXX correct? */
162 case PIPE_CAP_NPOT_TEXTURES
:
164 case PIPE_CAP_TWO_SIDED_STENCIL
:
168 case PIPE_CAP_ANISOTROPIC_FILTER
:
170 case PIPE_CAP_POINT_SPRITE
:
172 case PIPE_CAP_MAX_RENDER_TARGETS
:
174 case PIPE_CAP_OCCLUSION_QUERY
:
176 case PIPE_CAP_TIMER_QUERY
:
178 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
180 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
181 return BRW_MAX_TEXTURE_2D_LEVELS
;
182 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
183 return BRW_MAX_TEXTURE_3D_LEVELS
;
184 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
185 return BRW_MAX_TEXTURE_2D_LEVELS
;
186 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
187 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
189 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
190 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
192 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
193 /* disable for now */
201 brw_get_shader_param(struct pipe_screen
*screen
, unsigned shader
, enum pipe_shader_cap param
)
204 case PIPE_SHADER_VERTEX
:
205 case PIPE_SHADER_FRAGMENT
:
206 case PIPE_SHADER_GEOMETRY
:
212 /* XXX: these are just shader model 4.0 values, fix this! */
214 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
216 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
218 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
220 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
222 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
224 case PIPE_SHADER_CAP_MAX_INPUTS
:
226 case PIPE_SHADER_CAP_MAX_CONSTS
:
228 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
229 return PIPE_MAX_CONSTANT_BUFFERS
;
230 case PIPE_SHADER_CAP_MAX_TEMPS
:
232 case PIPE_SHADER_CAP_MAX_ADDRS
:
234 case PIPE_SHADER_CAP_MAX_PREDS
:
236 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
245 brw_get_paramf(struct pipe_screen
*screen
, enum pipe_cap param
)
248 case PIPE_CAP_MAX_LINE_WIDTH
:
250 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
253 case PIPE_CAP_MAX_POINT_WIDTH
:
255 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
258 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
261 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
270 brw_is_format_supported(struct pipe_screen
*screen
,
271 enum pipe_format format
,
272 enum pipe_texture_target target
,
273 unsigned sample_count
,
277 static const enum pipe_format tex_supported
[] = {
278 PIPE_FORMAT_L8_UNORM
,
279 PIPE_FORMAT_I8_UNORM
,
280 PIPE_FORMAT_A8_UNORM
,
281 PIPE_FORMAT_L16_UNORM
,
282 /*PIPE_FORMAT_I16_UNORM,*/
283 /*PIPE_FORMAT_A16_UNORM,*/
284 PIPE_FORMAT_L8A8_UNORM
,
285 PIPE_FORMAT_B5G6R5_UNORM
,
286 PIPE_FORMAT_B5G5R5A1_UNORM
,
287 PIPE_FORMAT_B4G4R4A4_UNORM
,
288 PIPE_FORMAT_B8G8R8X8_UNORM
,
289 PIPE_FORMAT_B8G8R8A8_UNORM
,
294 /*PIPE_FORMAT_FXT1_RGBA,*/
295 PIPE_FORMAT_DXT1_RGB
,
296 PIPE_FORMAT_DXT1_RGBA
,
297 PIPE_FORMAT_DXT3_RGBA
,
298 PIPE_FORMAT_DXT5_RGBA
,
300 PIPE_FORMAT_A8B8G8R8_SRGB
,
301 PIPE_FORMAT_L8A8_SRGB
,
303 PIPE_FORMAT_DXT1_SRGB
,
305 PIPE_FORMAT_Z32_FLOAT
,
306 PIPE_FORMAT_Z24X8_UNORM
,
307 PIPE_FORMAT_Z24_UNORM_S8_USCALED
,
308 PIPE_FORMAT_Z16_UNORM
,
310 PIPE_FORMAT_R8G8_SNORM
,
311 PIPE_FORMAT_R8G8B8A8_SNORM
,
312 PIPE_FORMAT_NONE
/* list terminator */
314 static const enum pipe_format render_supported
[] = {
315 PIPE_FORMAT_B8G8R8X8_UNORM
,
316 PIPE_FORMAT_B8G8R8A8_UNORM
,
317 PIPE_FORMAT_B5G6R5_UNORM
,
318 PIPE_FORMAT_NONE
/* list terminator */
320 static const enum pipe_format depth_supported
[] = {
321 PIPE_FORMAT_Z32_FLOAT
,
322 PIPE_FORMAT_Z24X8_UNORM
,
323 PIPE_FORMAT_Z24_UNORM_S8_USCALED
,
324 PIPE_FORMAT_Z16_UNORM
,
325 PIPE_FORMAT_NONE
/* list terminator */
327 const enum pipe_format
*list
;
330 if (sample_count
> 1)
333 if (tex_usage
& PIPE_BIND_DEPTH_STENCIL
)
334 list
= depth_supported
;
335 else if (tex_usage
& PIPE_BIND_RENDER_TARGET
)
336 list
= render_supported
;
338 list
= tex_supported
;
340 for (i
= 0; list
[i
] != PIPE_FORMAT_NONE
; i
++) {
341 if (list
[i
] == format
)
355 brw_fence_reference(struct pipe_screen
*screen
,
356 struct pipe_fence_handle
**ptr
,
357 struct pipe_fence_handle
*fence
)
362 brw_fence_signalled(struct pipe_screen
*screen
,
363 struct pipe_fence_handle
*fence
,
366 return 0; /* XXX shouldn't this be a boolean? */
370 brw_fence_finish(struct pipe_screen
*screen
,
371 struct pipe_fence_handle
*fence
,
384 brw_destroy_screen(struct pipe_screen
*screen
)
386 struct brw_screen
*bscreen
= brw_screen(screen
);
389 bscreen
->sws
->destroy(bscreen
->sws
);
395 * Create a new brw_screen object
398 brw_screen_create(struct brw_winsys_screen
*sws
)
400 struct brw_screen
*bscreen
;
401 struct brw_chipset chipset
;
404 BRW_DEBUG
= debug_get_flags_option("BRW_DEBUG", debug_names
, 0);
405 BRW_DEBUG
|= debug_get_flags_option("INTEL_DEBUG", debug_names
, 0);
406 BRW_DEBUG
|= DEBUG_STATS
| DEBUG_MIN_URB
| DEBUG_WM
;
408 BRW_DUMP
= debug_get_flags_option("BRW_DUMP", dump_names
, 0);
411 memset(&chipset
, 0, sizeof chipset
);
413 chipset
.pci_id
= sws
->pci_id
;
415 switch (chipset
.pci_id
) {
416 case PCI_CHIP_I965_G
:
417 case PCI_CHIP_I965_Q
:
418 case PCI_CHIP_I965_G_1
:
419 case PCI_CHIP_I946_GZ
:
420 case PCI_CHIP_I965_GM
:
421 case PCI_CHIP_I965_GME
:
422 chipset
.is_965
= TRUE
;
425 case PCI_CHIP_GM45_GM
:
426 case PCI_CHIP_IGD_E_G
:
431 chipset
.is_g4x
= TRUE
;
436 chipset
.is_igdng
= TRUE
;
440 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
441 __FUNCTION__
, chipset
.pci_id
);
446 bscreen
= CALLOC_STRUCT(brw_screen
);
450 bscreen
->chipset
= chipset
;
452 bscreen
->base
.winsys
= NULL
;
453 bscreen
->base
.destroy
= brw_destroy_screen
;
454 bscreen
->base
.get_name
= brw_get_name
;
455 bscreen
->base
.get_vendor
= brw_get_vendor
;
456 bscreen
->base
.get_param
= brw_get_param
;
457 bscreen
->base
.get_shader_param
= brw_get_shader_param
;
458 bscreen
->base
.get_paramf
= brw_get_paramf
;
459 bscreen
->base
.is_format_supported
= brw_is_format_supported
;
460 bscreen
->base
.context_create
= brw_create_context
;
461 bscreen
->base
.fence_reference
= brw_fence_reference
;
462 bscreen
->base
.fence_signalled
= brw_fence_signalled
;
463 bscreen
->base
.fence_finish
= brw_fence_finish
;
465 brw_init_screen_resource_functions(bscreen
);
466 brw_screen_tex_surface_init(bscreen
);
468 bscreen
->no_tiling
= debug_get_option("BRW_NO_TILING", FALSE
) != NULL
;
471 return &bscreen
->base
;