src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_string.h"
  32
  33 #include "brw_reg.h"
  34 #include "brw_context.h"
  35 #include "brw_screen.h"
  36 #include "brw_winsys.h"
  37 #include "brw_public.h"
  38 #include "brw_debug.h"
  39 #include "brw_resource.h"
  40
  41 #ifdef DEBUG
  42 static const struct debug_named_value debug_names[] = {
  43    { "tex",   DEBUG_TEXTURE, NULL },
  44    { "state", DEBUG_STATE, NULL },
  45    { "ioctl", DEBUG_IOCTL, NULL },
  46    { "blit",  DEBUG_BLIT, NULL },
  47    { "curbe", DEBUG_CURBE, NULL },
  48    { "fall",  DEBUG_FALLBACKS, NULL },
  49    { "verb",  DEBUG_VERBOSE, NULL },
  50    { "bat",   DEBUG_BATCH, NULL },
  51    { "pix",   DEBUG_PIXEL, NULL },
  52    { "wins",  DEBUG_WINSYS, NULL },
  53    { "min",   DEBUG_MIN_URB, NULL },
  54    { "dis",   DEBUG_DISASSEM, NULL },
  55    { "sync",  DEBUG_SYNC, NULL },
  56    { "prim",  DEBUG_PRIMS, NULL },
  57    { "vert",  DEBUG_VERTS, NULL },
  58    { "dma",   DEBUG_DMA, NULL },
  59    { "san",   DEBUG_SANITY, NULL },
  60    { "sleep", DEBUG_SLEEP, NULL },
  61    { "stats", DEBUG_STATS, NULL },
  62    { "sing",  DEBUG_SINGLE_THREAD, NULL },
  63    { "thre",  DEBUG_SINGLE_THREAD, NULL },
  64    { "wm",    DEBUG_WM, NULL },
  65    { "urb",   DEBUG_URB, NULL },
  66    { "vs",    DEBUG_VS, NULL },
  67    DEBUG_NAMED_VALUE_END
  68 };
  69
  70 static const struct debug_named_value dump_names[] = {
  71    { "asm",   DUMP_ASM, NULL },
  72    { "state", DUMP_STATE, NULL },
  73    { "batch", DUMP_BATCH, NULL },
  74    DEBUG_NAMED_VALUE_END
  75 };
  76
  77 int BRW_DEBUG = 0;
  78 int BRW_DUMP = 0;
  79
  80 #endif
  81
  82
  83 /*
  84  * Probe functions
  85  */
  86
  87
  88 static const char *
  89 brw_get_vendor(struct pipe_screen *screen)
  90 {
  91    return "VMware, Inc.";
  92 }
  93
  94 static const char *
  95 brw_get_name(struct pipe_screen *screen)
  96 {
  97    static char buffer[128];
  98    const char *chipset;
  99
 100    switch (brw_screen(screen)->chipset.pci_id) {
 101    case PCI_CHIP_I965_G:
 102       chipset = "I965_G";
 103       break;
 104    case PCI_CHIP_I965_Q:
 105       chipset = "I965_Q";
 106       break;
 107    case PCI_CHIP_I965_G_1:
 108       chipset = "I965_G_1";
 109       break;
 110    case PCI_CHIP_I946_GZ:
 111       chipset = "I946_GZ";
 112       break;
 113    case PCI_CHIP_I965_GM:
 114       chipset = "I965_GM";
 115       break;
 116    case PCI_CHIP_I965_GME:
 117       chipset = "I965_GME";
 118       break;
 119    case PCI_CHIP_GM45_GM:
 120       chipset = "GM45_GM";
 121       break;
 122    case PCI_CHIP_IGD_E_G:
 123       chipset = "IGD_E_G";
 124       break;
 125    case PCI_CHIP_Q45_G:
 126       chipset = "Q45_G";
 127       break;
 128    case PCI_CHIP_G45_G:
 129       chipset = "G45_G";
 130       break;
 131    case PCI_CHIP_G41_G:
 132       chipset = "G41_G";
 133       break;
 134    case PCI_CHIP_B43_G:
 135       chipset = "B43_G";
 136       break;
 137    case PCI_CHIP_ILD_G:
 138       chipset = "ILD_G";
 139       break;
 140    case PCI_CHIP_ILM_G:
 141       chipset = "ILM_G";
 142       break;
 143    default:
 144       chipset = "unknown";
 145       break;
 146    }
 147
 148    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 149    return buffer;
 150 }
 151
 152 static int
 153 brw_get_param(struct pipe_screen *screen, enum pipe_cap param)
 154 {
 155    switch (param) {
 156    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 157       return 8;
 158    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 159       return 8;
 160    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 161       return 16; /* XXX correct? */
 162    case PIPE_CAP_NPOT_TEXTURES:
 163       return 1;
 164    case PIPE_CAP_TWO_SIDED_STENCIL:
 165       return 1;
 166    case PIPE_CAP_GLSL:
 167       return 0;
 168    case PIPE_CAP_ANISOTROPIC_FILTER:
 169       return 0;
 170    case PIPE_CAP_POINT_SPRITE:
 171       return 0;
 172    case PIPE_CAP_MAX_RENDER_TARGETS:
 173       return 1;
 174    case PIPE_CAP_OCCLUSION_QUERY:
 175       return 0;
 176    case PIPE_CAP_TIMER_QUERY:
 177       return 0;
 178    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 179       return 1;
 180    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 181       return BRW_MAX_TEXTURE_2D_LEVELS;
 182    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 183       return BRW_MAX_TEXTURE_3D_LEVELS;
 184    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 185       return BRW_MAX_TEXTURE_2D_LEVELS;
 186    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 187    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 188       return 1;
 189    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 190    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 191       return 0;
 192    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 193       /* disable for now */
 194       return 0;
 195    default:
 196       return 0;
 197    }
 198 }
 199
 200 static float
 201 brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param)
 202 {
 203    switch (param) {
 204    case PIPE_CAP_MAX_LINE_WIDTH:
 205       /* fall-through */
 206    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 207       return 7.5;
 208
 209    case PIPE_CAP_MAX_POINT_WIDTH:
 210       /* fall-through */
 211    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 212       return 255.0;
 213
 214    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 215       return 4.0;
 216
 217    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 218       return 16.0;
 219
 220    default:
 221       return 0;
 222    }
 223 }
 224
 225 static boolean
 226 brw_is_format_supported(struct pipe_screen *screen,
 227                          enum pipe_format format,
 228                          enum pipe_texture_target target,
 229                          unsigned sample_count,
 230                          unsigned tex_usage,
 231                          unsigned geom_flags)
 232 {
 233    static const enum pipe_format tex_supported[] = {
 234       PIPE_FORMAT_L8_UNORM,
 235       PIPE_FORMAT_I8_UNORM,
 236       PIPE_FORMAT_A8_UNORM,
 237       PIPE_FORMAT_L16_UNORM,
 238       /*PIPE_FORMAT_I16_UNORM,*/
 239       /*PIPE_FORMAT_A16_UNORM,*/
 240       PIPE_FORMAT_L8A8_UNORM,
 241       PIPE_FORMAT_B5G6R5_UNORM,
 242       PIPE_FORMAT_B5G5R5A1_UNORM,
 243       PIPE_FORMAT_B4G4R4A4_UNORM,
 244       PIPE_FORMAT_B8G8R8X8_UNORM,
 245       PIPE_FORMAT_B8G8R8A8_UNORM,
 246       /* video */
 247       PIPE_FORMAT_UYVY,
 248       PIPE_FORMAT_YUYV,
 249       /* compressed */
 250       /*PIPE_FORMAT_FXT1_RGBA,*/
 251       PIPE_FORMAT_DXT1_RGB,
 252       PIPE_FORMAT_DXT1_RGBA,
 253       PIPE_FORMAT_DXT3_RGBA,
 254       PIPE_FORMAT_DXT5_RGBA,
 255       /* sRGB */
 256       PIPE_FORMAT_A8B8G8R8_SRGB,
 257       PIPE_FORMAT_L8A8_SRGB,
 258       PIPE_FORMAT_L8_SRGB,
 259       PIPE_FORMAT_DXT1_SRGB,
 260       /* depth */
 261       PIPE_FORMAT_Z32_FLOAT,
 262       PIPE_FORMAT_Z24X8_UNORM,
 263       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 264       PIPE_FORMAT_Z16_UNORM,
 265       /* signed */
 266       PIPE_FORMAT_R8G8_SNORM,
 267       PIPE_FORMAT_R8G8B8A8_SNORM,
 268       PIPE_FORMAT_NONE  /* list terminator */
 269    };
 270    static const enum pipe_format render_supported[] = {
 271       PIPE_FORMAT_B8G8R8X8_UNORM,
 272       PIPE_FORMAT_B8G8R8A8_UNORM,
 273       PIPE_FORMAT_B5G6R5_UNORM,
 274       PIPE_FORMAT_NONE  /* list terminator */
 275    };
 276    static const enum pipe_format depth_supported[] = {
 277       PIPE_FORMAT_Z32_FLOAT,
 278       PIPE_FORMAT_Z24X8_UNORM,
 279       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 280       PIPE_FORMAT_Z16_UNORM,
 281       PIPE_FORMAT_NONE  /* list terminator */
 282    };
 283    const enum pipe_format *list;
 284    uint i;
 285
 286    if (sample_count > 1)
 287       return FALSE;
 288
 289    if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
 290       list = depth_supported;
 291    else if (tex_usage & PIPE_BIND_RENDER_TARGET)
 292       list = render_supported;
 293    else
 294       list = tex_supported;
 295
 296    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 297       if (list[i] == format)
 298          return TRUE;
 299    }
 300
 301    return FALSE;
 302 }
 303
 304
 305 /*
 306  * Fence functions
 307  */
 308
 309
 310 static void
 311 brw_fence_reference(struct pipe_screen *screen,
 312                      struct pipe_fence_handle **ptr,
 313                      struct pipe_fence_handle *fence)
 314 {
 315 }
 316
 317 static int
 318 brw_fence_signalled(struct pipe_screen *screen,
 319                      struct pipe_fence_handle *fence,
 320                      unsigned flags)
 321 {
 322    return 0;                    /* XXX shouldn't this be a boolean? */
 323 }
 324
 325 static int
 326 brw_fence_finish(struct pipe_screen *screen,
 327                  struct pipe_fence_handle *fence,
 328                  unsigned flags)
 329 {
 330    return 0;
 331 }
 332
 333
 334 /*
 335  * Generic functions
 336  */
 337
 338
 339 static void
 340 brw_destroy_screen(struct pipe_screen *screen)
 341 {
 342    struct brw_screen *bscreen = brw_screen(screen);
 343
 344    if (bscreen->sws)
 345       bscreen->sws->destroy(bscreen->sws);
 346
 347    FREE(bscreen);
 348 }
 349
 350 /**
 351  * Create a new brw_screen object
 352  */
 353 struct pipe_screen *
 354 brw_screen_create(struct brw_winsys_screen *sws)
 355 {
 356    struct brw_screen *bscreen;
 357    struct brw_chipset chipset;
 358
 359 #ifdef DEBUG
 360    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 361    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 362    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 363
 364    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 365 #endif
 366
 367    memset(&chipset, 0, sizeof chipset);
 368
 369    chipset.pci_id = sws->pci_id;
 370
 371    switch (chipset.pci_id) {
 372    case PCI_CHIP_I965_G:
 373    case PCI_CHIP_I965_Q:
 374    case PCI_CHIP_I965_G_1:
 375    case PCI_CHIP_I946_GZ:
 376    case PCI_CHIP_I965_GM:
 377    case PCI_CHIP_I965_GME:
 378       chipset.is_965 = TRUE;
 379       break;
 380
 381    case PCI_CHIP_GM45_GM:
 382    case PCI_CHIP_IGD_E_G:
 383    case PCI_CHIP_Q45_G:
 384    case PCI_CHIP_G45_G:
 385    case PCI_CHIP_G41_G:
 386    case PCI_CHIP_B43_G:
 387       chipset.is_g4x = TRUE;
 388       break;
 389
 390    case PCI_CHIP_ILD_G:
 391    case PCI_CHIP_ILM_G:
 392       chipset.is_igdng = TRUE;
 393       break;
 394
 395    default:
 396       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 397                    __FUNCTION__, chipset.pci_id);
 398       return NULL;
 399    }
 400
 401
 402    bscreen = CALLOC_STRUCT(brw_screen);
 403    if (!bscreen)
 404       return NULL;
 405
 406    bscreen->chipset = chipset;
 407    bscreen->sws = sws;
 408    bscreen->base.winsys = NULL;
 409    bscreen->base.destroy = brw_destroy_screen;
 410    bscreen->base.get_name = brw_get_name;
 411    bscreen->base.get_vendor = brw_get_vendor;
 412    bscreen->base.get_param = brw_get_param;
 413    bscreen->base.get_paramf = brw_get_paramf;
 414    bscreen->base.is_format_supported = brw_is_format_supported;
 415    bscreen->base.context_create = brw_create_context;
 416    bscreen->base.fence_reference = brw_fence_reference;
 417    bscreen->base.fence_signalled = brw_fence_signalled;
 418    bscreen->base.fence_finish = brw_fence_finish;
 419
 420    brw_init_screen_resource_functions(bscreen);
 421    brw_screen_tex_surface_init(bscreen);
 422
 423    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 424
 425
 426    return &bscreen->base;
 427 }