e0df6cc629b74426f0d0c0e551b8c79dd491cdac
[mesa.git] / src / gallium / drivers / i965 / brw_screen_surface.c
1
2 #include "pipe/p_screen.h"
3 #include "brw_screen.h"
4
5 struct brw_surface_id {
6 unsigned face:3;
7 unsigned zslice:13;
8 unsigned level:16;
9 };
10
11 static boolean need_linear_view( struct brw_screen *brw_screen,
12 struct brw_texture *brw_texture,
13 unsigned face,
14 unsigned level,
15 unsigned zslice )
16 {
17 #if 0
18 /* XXX: what about IDGNG?
19 */
20 if (!BRW_IS_G4X(brw->brw_screen->pci_id))
21 {
22 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
23 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
24
25 /* The original gen4 hardware couldn't set up WM surfaces pointing
26 * at an offset within a tile, which can happen when rendering to
27 * anything but the base level of a texture or the +X face/0 depth.
28 * This was fixed with the 4 Series hardware.
29 *
30 * For these original chips, you would have to make the depth and
31 * color destination surfaces include information on the texture
32 * type, LOD, face, and various limits to use them as a destination.
33 *
34 * This is easy in Gallium as surfaces are all backed by
35 * textures, but there's also a nasty requirement that the depth
36 * and the color surfaces all be of the same LOD, which is
37 * harder to get around as we can't look at a surface in
38 * isolation and decide if it's legal.
39 *
40 * Instead, end up being pessimistic and say that for i965,
41 * ... ??
42 */
43 if (brw_tex->tiling != I915_TILING_NONE &&
44 (brw_tex_image_offset(brw_tex, face, level, zslize) & 4095)) {
45 if (BRW_DEBUG & DEBUG_VIEW)
46 debug_printf("%s: need surface view for non-aligned tex image\n",
47 __FUNCTION__);
48 return GL_TRUE;
49 }
50 }
51 #endif
52
53 /* Tiled 3d textures don't have subsets that look like 2d surfaces:
54 */
55
56 /* Everything else should be fine to render to in-place:
57 */
58 return GL_FALSE;
59 }
60
61 /* Look at all texture views and figure out if any of them need to be
62 * back-copied into the texture for sampling
63 */
64 void brw_update_texture( struct pipe_screen *screen,
65 struct pipe_texture *texture )
66 {
67 /* currently nothing to do */
68 }
69
70
71 static struct pipe_surface *create_linear_view( struct brw_screen *brw_screen,
72 struct brw_texture *brw_tex,
73 struct brw_surface_id id )
74 {
75
76 }
77
78 static struct pipe_surface *create_in_place_view( struct brw_screen *brw_screen,
79 struct brw_texture *brw_tex,
80 struct brw_surface_id id )
81 {
82 struct brw_surface *surface = CALLOC_STRUCT(brw_surface);
83 surface->id = id;
84
85 }
86
87 /* Get a surface which is view into a texture
88 */
89 struct pipe_surface *brw_get_tex_surface(struct pipe_screen *screen,
90 struct pipe_texture *texture,
91 unsigned face, unsigned level,
92 unsigned zslice,
93 unsigned usage )
94 {
95 struct brw_screen *bscreen = brw_screen(screen);
96 struct brw_surface_id id;
97
98 id.face = face;
99 id.level = level;
100 id.zslice = zslice;
101
102 if (need_linear_view(brw_screen, brw_tex, id))
103 type = BRW_VIEW_LINEAR;
104 else
105 type = BRW_VIEW_IN_PLACE;
106
107
108 foreach (surface, texture->views[type]) {
109 if (id.value == surface->id.value)
110 return surface;
111 }
112
113 switch (type) {
114 case BRW_VIEW_LINEAR:
115 surface = create_linear_view( texture, id, type );
116 break;
117 case BRW_VIEW_IN_PLACE:
118 surface = create_in_place_view( texture, id, type );
119 break;
120 default:
121 return NULL;
122 }
123
124 insert_at_head( texture->views[type], surface );
125 return surface;
126 }
127
128
129 void brw_tex_surface_destroy( struct pipe_surface *surface )
130 {
131 }