i965g: more work on compiling
[mesa.git] / src / gallium / drivers / i965 / brw_sf_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37
38 static void upload_sf_vp(struct brw_context *brw)
39 {
40 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
41 struct brw_sf_viewport sfv;
42 GLfloat y_scale, y_bias;
43 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
44 const GLfloat *v = ctx->Viewport._WindowMap.m;
45
46 memset(&sfv, 0, sizeof(sfv));
47
48 if (render_to_fbo) {
49 y_scale = 1.0;
50 y_bias = 0;
51 }
52 else {
53 y_scale = -1.0;
54 y_bias = ctx->DrawBuffer->Height;
55 }
56
57 /* _NEW_VIEWPORT */
58
59 sfv.viewport.m00 = v[MAT_SX];
60 sfv.viewport.m11 = v[MAT_SY] * y_scale;
61 sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
62 sfv.viewport.m30 = v[MAT_TX];
63 sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
64 sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
65
66 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
67 * for DrawBuffer->_[XY]{min,max}
68 */
69
70 /* The scissor only needs to handle the intersection of drawable and
71 * scissor rect.
72 *
73 * Note that the hardware's coordinates are inclusive, while Mesa's min is
74 * inclusive but max is exclusive.
75 */
76 if (render_to_fbo) {
77 /* texmemory: Y=0=bottom */
78 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
79 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
80 sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
81 sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
82 }
83 else {
84 /* memory: Y=0=top */
85 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
86 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
87 sfv.scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
88 sfv.scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
89 }
90
91 brw->sws->bo_unreference(brw->sf.vp_bo);
92 brw->sf.vp_bo = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0 );
93 }
94
95 const struct brw_tracked_state brw_sf_vp = {
96 .dirty = {
97 .mesa = (_NEW_VIEWPORT |
98 _NEW_SCISSOR |
99 _NEW_BUFFERS),
100 .brw = 0,
101 .cache = 0
102 },
103 .prepare = upload_sf_vp
104 };
105
106 struct brw_sf_unit_key {
107 unsigned int total_grf;
108 unsigned int urb_entry_read_length;
109
110 unsigned int nr_urb_entries, urb_size, sfsize;
111
112 GLenum front_face, cull_face, provoking_vertex;
113 unsigned scissor:1;
114 unsigned line_smooth:1;
115 unsigned point_sprite:1;
116 unsigned point_attenuated:1;
117 unsigned render_to_fbo:1;
118 float line_width;
119 float point_size;
120 };
121
122 static void
123 sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
124 {
125 memset(key, 0, sizeof(*key));
126
127 /* CACHE_NEW_SF_PROG */
128 key->total_grf = brw->sf.prog_data->total_grf;
129 key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
130
131 /* BRW_NEW_URB_FENCE */
132 key->nr_urb_entries = brw->urb.nr_sf_entries;
133 key->urb_size = brw->urb.vsize;
134 key->sfsize = brw->urb.sfsize;
135
136 key->scissor = ctx->Scissor.Enabled;
137 key->front_face = ctx->Polygon.FrontFace;
138
139 if (ctx->Polygon.CullFlag)
140 key->cull_face = ctx->Polygon.CullFaceMode;
141 else
142 key->cull_face = GL_NONE;
143
144 key->line_width = ctx->Line.Width;
145 key->line_smooth = ctx->Line.SmoothFlag;
146
147 key->point_sprite = ctx->Point.PointSprite;
148 key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
149 key->point_attenuated = ctx->Point._Attenuated;
150
151 /* _NEW_LIGHT */
152 key->provoking_vertex = ctx->Light.ProvokingVertex;
153
154 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
155 }
156
157 static struct brw_winsys_buffer *
158 sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
159 struct brw_winsys_buffer **reloc_bufs)
160 {
161 struct brw_sf_unit_state sf;
162 struct brw_winsys_buffer *bo;
163 int chipset_max_threads;
164 memset(&sf, 0, sizeof(sf));
165
166 sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
167 sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
168
169 sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
170
171 sf.thread3.dispatch_grf_start_reg = 3;
172
173 if (BRW_IS_IGDNG(brw))
174 sf.thread3.urb_entry_read_offset = 3;
175 else
176 sf.thread3.urb_entry_read_offset = 1;
177
178 sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
179
180 sf.thread4.nr_urb_entries = key->nr_urb_entries;
181 sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
182
183 /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
184 * 48(IGDNG) threads
185 */
186 if (BRW_IS_IGDNG(brw))
187 chipset_max_threads = 48;
188 else
189 chipset_max_threads = 24;
190
191 sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
192
193 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
194 sf.thread4.max_threads = 0;
195
196 if (INTEL_DEBUG & DEBUG_STATS)
197 sf.thread4.stats_enable = 1;
198
199 /* CACHE_NEW_SF_VP */
200 sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
201
202 sf.sf5.viewport_transform = 1;
203
204 /* _NEW_SCISSOR */
205 if (key->scissor)
206 sf.sf6.scissor = 1;
207
208 /* _NEW_POLYGON */
209 if (key->front_face == GL_CCW)
210 sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
211 else
212 sf.sf5.front_winding = BRW_FRONTWINDING_CW;
213
214 /* The viewport is inverted for rendering to a FBO, and that inverts
215 * polygon front/back orientation.
216 */
217 sf.sf5.front_winding ^= key->render_to_fbo;
218
219 switch (key->cull_face) {
220 case GL_FRONT:
221 sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
222 break;
223 case GL_BACK:
224 sf.sf6.cull_mode = BRW_CULLMODE_BACK;
225 break;
226 case GL_FRONT_AND_BACK:
227 sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
228 break;
229 case GL_NONE:
230 sf.sf6.cull_mode = BRW_CULLMODE_NONE;
231 break;
232 default:
233 assert(0);
234 break;
235 }
236
237 /* _NEW_LINE */
238 /* XXX use ctx->Const.Min/MaxLineWidth here */
239 sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
240
241 sf.sf6.line_endcap_aa_region_width = 1;
242 if (key->line_smooth)
243 sf.sf6.aa_enable = 1;
244 else if (sf.sf6.line_width <= 0x2)
245 sf.sf6.line_width = 0;
246
247 /* _NEW_BUFFERS */
248 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
249 if (!key->render_to_fbo) {
250 /* Rendering to an OpenGL window */
251 sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
252 }
253 else {
254 /* If rendering to an FBO, the pixel coordinate system is
255 * inverted with respect to the normal OpenGL coordinate
256 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
257 * But this value is listed as "Reserved, but not seen as useful"
258 * in Intel documentation (page 212, "Point Rasterization Rule",
259 * section 7.4 "SF Pipeline State Summary", of document
260 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
261 * Chipset Graphics Controller Programmer's Reference Manual,
262 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
263 * available at
264 * http://intellinuxgraphics.org/documentation.html
265 * at the time of this writing).
266 *
267 * It does work on at least some devices, if not all;
268 * if devices that don't support it can be identified,
269 * the likely failure case is that points are rasterized
270 * incorrectly, which is no worse than occurs without
271 * the value, so we're using it here.
272 */
273 sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
274 }
275 /* XXX clamp max depends on AA vs. non-AA */
276
277 /* _NEW_POINT */
278 sf.sf7.sprite_point = key->point_sprite;
279 sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
280 sf.sf7.use_point_size_state = !key->point_attenuated;
281 sf.sf7.aa_line_distance_mode = 0;
282
283 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
284 */
285 if (key->provoking_vertex == GL_LAST_VERTEX_CONVENTION) {
286 sf.sf7.trifan_pv = 2;
287 sf.sf7.linestrip_pv = 1;
288 sf.sf7.tristrip_pv = 2;
289 } else {
290 sf.sf7.trifan_pv = 1;
291 sf.sf7.linestrip_pv = 0;
292 sf.sf7.tristrip_pv = 0;
293 }
294 sf.sf7.line_last_pixel_enable = 0;
295
296 /* Set bias for OpenGL rasterization rules:
297 */
298 sf.sf6.dest_org_vbias = 0x8;
299 sf.sf6.dest_org_hbias = 0x8;
300
301 bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
302 key, sizeof(*key),
303 reloc_bufs, 2,
304 &sf, sizeof(sf),
305 NULL, NULL);
306
307 /* STATE_PREFETCH command description describes this state as being
308 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
309 */
310 /* Emit SF program relocation */
311 dri_bo_emit_reloc(bo,
312 I915_GEM_DOMAIN_INSTRUCTION, 0,
313 sf.thread0.grf_reg_count << 1,
314 offsetof(struct brw_sf_unit_state, thread0),
315 brw->sf.prog_bo);
316
317 /* Emit SF viewport relocation */
318 dri_bo_emit_reloc(bo,
319 I915_GEM_DOMAIN_INSTRUCTION, 0,
320 sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
321 offsetof(struct brw_sf_unit_state, sf5),
322 brw->sf.vp_bo);
323
324 return bo;
325 }
326
327 static void upload_sf_unit( struct brw_context *brw )
328 {
329 struct brw_sf_unit_key key;
330 struct brw_winsys_buffer *reloc_bufs[2];
331
332 sf_unit_populate_key(brw, &key);
333
334 reloc_bufs[0] = brw->sf.prog_bo;
335 reloc_bufs[1] = brw->sf.vp_bo;
336
337 brw->sws->bo_unreference(brw->sf.state_bo);
338 brw->sf.state_bo = brw_search_cache(&brw->cache, BRW_SF_UNIT,
339 &key, sizeof(key),
340 reloc_bufs, 2,
341 NULL);
342 if (brw->sf.state_bo == NULL) {
343 brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
344 }
345 }
346
347 const struct brw_tracked_state brw_sf_unit = {
348 .dirty = {
349 .mesa = (_NEW_POLYGON |
350 _NEW_LIGHT |
351 _NEW_LINE |
352 _NEW_POINT |
353 _NEW_SCISSOR |
354 _NEW_BUFFERS),
355 .brw = BRW_NEW_URB_FENCE,
356 .cache = (CACHE_NEW_SF_VP |
357 CACHE_NEW_SF_PROG)
358 },
359 .prepare = upload_sf_unit,
360 };