src/gallium/drivers/i965/brw_sf_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "util/u_math.h"
  33
  34 #include "pipe/p_state.h"
  35
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_debug.h"
  40 #include "brw_pipe_rast.h"
  41
  42 static enum pipe_error upload_sf_vp(struct brw_context *brw)
  43 {
  44    const struct pipe_viewport_state *vp = &brw->curr.vp;
  45    const struct pipe_scissor_state *scissor = &brw->curr.scissor;
  46    struct brw_sf_viewport sfv;
  47    enum pipe_error ret;
  48
  49    memset(&sfv, 0, sizeof(sfv));
  50
  51    /* PIPE_NEW_VIEWPORT, PIPE_NEW_SCISSOR */
  52
  53    sfv.viewport.m00 = vp->scale[0];
  54    sfv.viewport.m11 = vp->scale[1];
  55    sfv.viewport.m22 = vp->scale[2];
  56    sfv.viewport.m30 = vp->translate[0];
  57    sfv.viewport.m31 = vp->translate[1];
  58    sfv.viewport.m32 = vp->translate[2];
  59
  60    sfv.scissor.xmin = scissor->minx;
  61    sfv.scissor.xmax = scissor->maxx; /* -1 ?? */
  62    sfv.scissor.ymin = scissor->miny;
  63    sfv.scissor.ymax = scissor->maxy; /* -1 ?? */
  64
  65    ret = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0,
  66                          &brw->sf.vp_bo );
  67    if (ret)
  68       return ret;
  69
  70    return PIPE_OK;
  71 }
  72
  73 const struct brw_tracked_state brw_sf_vp = {
  74    .dirty = {
  75       .mesa  = (PIPE_NEW_VIEWPORT |
  76                 PIPE_NEW_SCISSOR),
  77       .brw   = 0,
  78       .cache = 0
  79    },
  80    .prepare = upload_sf_vp
  81 };
  82
  83 struct brw_sf_unit_key {
  84    unsigned int total_grf;
  85    unsigned int urb_entry_read_length;
  86    unsigned int nr_urb_entries, urb_size, sfsize;
  87
  88    unsigned scissor:1;
  89    unsigned line_smooth:1;
  90    unsigned point_sprite:1;
  91    unsigned point_attenuated:1;
  92    unsigned front_face:2;
  93    unsigned cull_mode:2;
  94    unsigned flatshade_first:1;
  95    unsigned gl_rasterization_rules:1;
  96    unsigned line_last_pixel_enable:1;
  97    float line_width;
  98    float point_size;
  99 };
 100
 101 static void
 102 sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
 103 {
 104    const struct pipe_rasterizer_state *rast = &brw->curr.rast->templ;
 105    memset(key, 0, sizeof(*key));
 106
 107    /* CACHE_NEW_SF_PROG */
 108    key->total_grf = brw->sf.prog_data->total_grf;
 109    key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 110
 111    /* BRW_NEW_URB_FENCE */
 112    key->nr_urb_entries = brw->urb.nr_sf_entries;
 113    key->urb_size = brw->urb.vsize;
 114    key->sfsize = brw->urb.sfsize;
 115
 116    /* PIPE_NEW_RAST */
 117    key->scissor = rast->scissor;
 118    key->front_face = rast->front_winding;
 119    key->cull_mode = rast->cull_mode;
 120    key->line_smooth = rast->line_smooth;
 121    key->line_width = rast->line_width;
 122    key->flatshade_first = rast->flatshade_first;
 123    key->line_last_pixel_enable = rast->line_last_pixel;
 124    key->gl_rasterization_rules = rast->gl_rasterization_rules;
 125
 126    key->point_sprite = rast->point_sprite;
 127    key->point_attenuated = rast->point_size_per_vertex;
 128
 129    key->point_size = CLAMP(rast->point_size,
 130                            rast->point_size_min,
 131                            rast->point_size_max);
 132 }
 133
 134 static enum pipe_error
 135 sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
 136                         struct brw_winsys_buffer **reloc_bufs,
 137                         struct brw_winsys_buffer **bo_out)
 138 {
 139    struct brw_sf_unit_state sf;
 140    enum pipe_error ret;
 141    int chipset_max_threads;
 142    memset(&sf, 0, sizeof(sf));
 143
 144    sf.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
 145    sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset[0] >> 6; /* reloc */
 146
 147    sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 148
 149    sf.thread3.dispatch_grf_start_reg = 3;
 150
 151    if (BRW_IS_IGDNG(brw))
 152        sf.thread3.urb_entry_read_offset = 3;
 153    else
 154        sf.thread3.urb_entry_read_offset = 1;
 155
 156    sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
 157
 158    sf.thread4.nr_urb_entries = key->nr_urb_entries;
 159    sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
 160
 161    /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
 162     * 48(IGDNG) threads
 163     */
 164    if (BRW_IS_IGDNG(brw))
 165       chipset_max_threads = 48;
 166    else
 167       chipset_max_threads = 24;
 168
 169    sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
 170
 171    if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
 172       sf.thread4.max_threads = 0;
 173
 174    if (BRW_DEBUG & DEBUG_STATS)
 175       sf.thread4.stats_enable = 1;
 176
 177    /* CACHE_NEW_SF_VP */
 178    sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset[0] >> 5; /* reloc */
 179
 180    sf.sf5.viewport_transform = 1;
 181
 182    if (key->scissor)
 183       sf.sf6.scissor = 1;
 184
 185    if (key->front_face == PIPE_WINDING_CCW)
 186       sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
 187    else
 188       sf.sf5.front_winding = BRW_FRONTWINDING_CW;
 189
 190    switch (key->cull_mode) {
 191    case PIPE_WINDING_CCW:
 192    case PIPE_WINDING_CW:
 193       sf.sf6.cull_mode = (key->front_face == key->cull_mode ?
 194                           BRW_CULLMODE_FRONT :
 195                           BRW_CULLMODE_BACK);
 196       break;
 197    case PIPE_WINDING_BOTH:
 198       sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
 199       break;
 200    case PIPE_WINDING_NONE:
 201       sf.sf6.cull_mode = BRW_CULLMODE_NONE;
 202       break;
 203    default:
 204       assert(0);
 205       sf.sf6.cull_mode = BRW_CULLMODE_NONE;
 206       break;
 207    }
 208
 209    /* _NEW_LINE */
 210    /* XXX use ctx->Const.Min/MaxLineWidth here */
 211    sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
 212
 213    sf.sf6.line_endcap_aa_region_width = 1;
 214    if (key->line_smooth)
 215       sf.sf6.aa_enable = 1;
 216    else if (sf.sf6.line_width <= 0x2)
 217        sf.sf6.line_width = 0;
 218
 219    /* XXX: gl_rasterization_rules?  something else?
 220     */
 221    if (0) {
 222       /* Rendering to an OpenGL window */
 223       sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
 224    }
 225    else {
 226       /* If rendering to an FBO, the pixel coordinate system is
 227        * inverted with respect to the normal OpenGL coordinate
 228        * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
 229        * But this value is listed as "Reserved, but not seen as useful"
 230        * in Intel documentation (page 212, "Point Rasterization Rule",
 231        * section 7.4 "SF Pipeline State Summary", of document
 232        * "Intel® 965 Express Chipset Family and Intel® G35 Express
 233        * Chipset Graphics Controller Programmer's Reference Manual,
 234        * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
 235        * available at
 236        *     http://intellinuxgraphics.org/documentation.html
 237        * at the time of this writing).
 238        *
 239        * It does work on at least some devices, if not all;
 240        * if devices that don't support it can be identified,
 241        * the likely failure case is that points are rasterized
 242        * incorrectly, which is no worse than occurs without
 243        * the value, so we're using it here.
 244        */
 245       sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
 246    }
 247    /* XXX clamp max depends on AA vs. non-AA */
 248
 249    /* _NEW_POINT */
 250    sf.sf7.sprite_point = key->point_sprite;
 251    sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
 252    sf.sf7.use_point_size_state = !key->point_attenuated;
 253    sf.sf7.aa_line_distance_mode = 0;
 254
 255    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
 256     */
 257    if (!key->flatshade_first) {
 258       sf.sf7.trifan_pv = 2;
 259       sf.sf7.linestrip_pv = 1;
 260       sf.sf7.tristrip_pv = 2;
 261    } else {
 262       sf.sf7.trifan_pv = 1;
 263       sf.sf7.linestrip_pv = 0;
 264       sf.sf7.tristrip_pv = 0;
 265    }
 266
 267    sf.sf7.line_last_pixel_enable = key->line_last_pixel_enable;
 268
 269    /* Set bias for OpenGL rasterization rules:
 270     */
 271    if (key->gl_rasterization_rules) {
 272       sf.sf6.dest_org_vbias = 0x8;
 273       sf.sf6.dest_org_hbias = 0x8;
 274    }
 275    else {
 276       sf.sf6.dest_org_vbias = 0x0;
 277       sf.sf6.dest_org_hbias = 0x0;
 278    }
 279
 280    ret = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
 281                           key, sizeof(*key),
 282                           reloc_bufs, 2,
 283                           &sf, sizeof(sf),
 284                           NULL, NULL,
 285                           bo_out);
 286    if (ret)
 287       return ret;
 288
 289    /* STATE_PREFETCH command description describes this state as being
 290     * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
 291     */
 292    /* Emit SF program relocation */
 293    ret = brw->sws->bo_emit_reloc(*bo_out,
 294                                  BRW_USAGE_STATE,
 295                                  sf.thread0.grf_reg_count << 1,
 296                                  offsetof(struct brw_sf_unit_state, thread0),
 297                                  brw->sf.prog_bo);
 298    if (ret)
 299       return ret;
 300
 301
 302    /* Emit SF viewport relocation */
 303    ret = brw->sws->bo_emit_reloc(*bo_out,
 304                                  BRW_USAGE_STATE,
 305                                  sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
 306                                  offsetof(struct brw_sf_unit_state, sf5),
 307                                  brw->sf.vp_bo);
 308    if (ret)
 309       return ret;
 310
 311    return PIPE_OK;
 312 }
 313
 314 static enum pipe_error upload_sf_unit( struct brw_context *brw )
 315 {
 316    struct brw_sf_unit_key key;
 317    struct brw_winsys_buffer *reloc_bufs[2];
 318    enum pipe_error ret;
 319
 320    sf_unit_populate_key(brw, &key);
 321
 322    reloc_bufs[0] = brw->sf.prog_bo;
 323    reloc_bufs[1] = brw->sf.vp_bo;
 324
 325    if (brw_search_cache(&brw->cache, BRW_SF_UNIT,
 326                         &key, sizeof(key),
 327                         reloc_bufs, 2,
 328                         NULL,
 329                         &brw->sf.state_bo))
 330       return PIPE_OK;
 331
 332
 333    ret = sf_unit_create_from_key(brw, &key, reloc_bufs,
 334                                  &brw->sf.state_bo);
 335    if (ret)
 336       return ret;
 337
 338    return PIPE_OK;
 339 }
 340
 341 const struct brw_tracked_state brw_sf_unit = {
 342    .dirty = {
 343       .mesa  = (PIPE_NEW_RAST),
 344       .brw   = BRW_NEW_URB_FENCE,
 345       .cache = (CACHE_NEW_SF_VP |
 346                 CACHE_NEW_SF_PROG)
 347    },
 348    .prepare = upload_sf_unit,
 349 };