2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
36 #include "brw_types.h"
38 /** Number of general purpose registers (VS, WM, etc) */
39 #define BRW_MAX_GRF 128
41 /** Number of message register file registers */
42 #define BRW_MAX_MRF 16
65 GLuint notify_enable
:1;
67 GLuint wc_flush_enable
:1;
68 GLuint depth_stall_enable
:1;
76 GLuint dest_addr_type
:1;
85 struct brw_3d_primitive
96 GLuint verts_per_instance
;
97 GLuint start_vert_location
;
98 GLuint instance_count
;
99 GLuint start_instance_location
;
100 GLuint base_vert_location
;
103 /* These seem to be passed around as function args, so it works out
104 * better to keep them as #defines:
106 #define BRW_FLUSH_READ_CACHE 0x1
107 #define BRW_FLUSH_STATE_CACHE 0x2
108 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
109 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
118 struct brw_vf_statistics
120 GLuint statistics_enable
:1;
127 struct brw_binding_table_pointers
129 struct header header
;
138 struct brw_blend_constant_color
140 struct header header
;
141 GLfloat blend_constant_color
[4];
145 struct brw_depthbuffer
147 union header_union header
;
154 GLuint software_tiled_rendering_mode
:2;
155 GLuint depth_offset_disable
:1;
157 GLuint tiled_surface
:1;
159 GLuint surface_type
:3;
164 GLuint dword2_base_addr
;
169 GLuint mipmap_layout
:1;
180 GLuint min_array_element
:11;
187 struct brw_depthbuffer_g4x
189 union header_union header
;
196 GLuint software_tiled_rendering_mode
:2;
197 GLuint depth_offset_disable
:1;
199 GLuint tiled_surface
:1;
201 GLuint surface_type
:3;
206 GLuint dword2_base_addr
;
211 GLuint mipmap_layout
:1;
222 GLuint min_array_element
:11;
234 } dword5
; /* NEW in Integrated Graphics Device */
239 struct header header
;
251 struct brw_global_depth_offset_clamp
253 struct header header
;
254 GLfloat depth_offset_clamp
;
257 struct brw_indexbuffer
263 GLuint index_format
:2;
264 GLuint cut_index_enable
:1;
276 /* NEW in Integrated Graphics Device */
277 struct brw_aa_line_parameters
279 struct header header
;
282 GLuint aa_coverage_slope
:8;
284 GLuint aa_coverage_bias
:8;
289 GLuint aa_coverage_endcap_slope
:8;
291 GLuint aa_coverage_endcap_bias
:8;
296 struct brw_line_stipple
298 struct header header
;
308 GLuint repeat_count
:9;
310 GLuint inverse_repeat_count
:16;
315 struct brw_pipelined_state_pointers
317 struct header header
;
321 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
328 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
335 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
341 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
347 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
353 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */
358 struct brw_polygon_stipple_offset
360 struct header header
;
372 struct brw_polygon_stipple
374 struct header header
;
380 struct brw_pipeline_select
384 GLuint pipeline_select
:1;
391 struct brw_pipe_control
396 GLuint notify_enable
:1;
397 GLuint texture_cache_flush_enable
:1;
398 GLuint indirect_state_pointers_disable
:1;
399 GLuint instruction_state_cache_flush_enable
:1;
400 GLuint write_cache_flush_enable
:1;
401 GLuint depth_stall_enable
:1;
402 GLuint post_sync_operation
:2;
410 GLuint dest_addr_type
:1;
426 GLuint clp_realloc
:1;
428 GLuint vfe_realloc
:1;
451 struct brw_cs_urb_state
453 struct header header
;
457 GLuint nr_urb_entries
:3;
459 GLuint urb_entry_size
:5;
464 struct brw_constant_buffer
476 GLuint buffer_length
:6;
477 GLuint buffer_address
:26;
481 struct brw_state_base_address
483 struct header header
;
487 GLuint modify_enable
:1;
489 GLuint general_state_address
:27;
494 GLuint modify_enable
:1;
496 GLuint surface_state_address
:27;
501 GLuint modify_enable
:1;
503 GLuint indirect_object_state_address
:27;
508 GLuint modify_enable
:1;
510 GLuint general_state_upper_bound
:20;
515 GLuint modify_enable
:1;
517 GLuint indirect_object_state_upper_bound
:20;
521 struct brw_state_prefetch
523 struct header header
;
527 GLuint prefetch_count
:3;
529 GLuint prefetch_pointer
:26;
533 struct brw_system_instruction_pointer
535 struct header header
;
540 GLuint system_instruction_pointer
:28;
547 /* State structs for the various fixed function units:
554 GLuint grf_reg_count
:3;
556 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
561 GLuint ext_halt_exception_enable
:1;
562 GLuint sw_exception_enable
:1;
563 GLuint mask_stack_exception_enable
:1;
564 GLuint timeout_exception_enable
:1;
565 GLuint illegal_op_exception_enable
:1;
567 GLuint depth_coef_urb_read_offset
:6; /* WM only */
569 GLuint floating_point_mode
:1;
570 GLuint thread_priority
:1;
571 GLuint binding_table_entry_count
:8;
573 GLuint single_program_flow
:1;
578 GLuint per_thread_scratch_space
:4;
580 GLuint scratch_space_base_pointer
:22;
586 GLuint dispatch_grf_start_reg
:4;
587 GLuint urb_entry_read_offset
:6;
589 GLuint urb_entry_read_length
:6;
591 GLuint const_urb_entry_read_offset
:6;
593 GLuint const_urb_entry_read_length
:6;
599 struct brw_clip_unit_state
601 struct thread0 thread0
;
605 GLuint sw_exception_enable
:1;
607 GLuint mask_stack_exception_enable
:1;
609 GLuint illegal_op_exception_enable
:1;
611 GLuint floating_point_mode
:1;
612 GLuint thread_priority
:1;
613 GLuint binding_table_entry_count
:8;
615 GLuint single_program_flow
:1;
618 struct thread2 thread2
;
619 struct thread3 thread3
;
624 GLuint gs_output_stats
:1; /* not always */
625 GLuint stats_enable
:1;
626 GLuint nr_urb_entries
:7;
628 GLuint urb_entry_allocation_size
:5;
630 GLuint max_threads
:5; /* may be less */
638 GLuint userclip_enable_flags
:8;
639 GLuint userclip_must_clip
:1;
640 GLuint negative_w_clip_test
:1;
641 GLuint guard_band_enable
:1;
642 GLuint viewport_z_clip_enable
:1;
643 GLuint viewport_xy_clip_enable
:1;
644 GLuint vertex_position_space
:1;
652 GLuint clipper_viewport_state_ptr
:27;
656 GLfloat viewport_xmin
;
657 GLfloat viewport_xmax
;
658 GLfloat viewport_ymin
;
659 GLfloat viewport_ymax
;
662 struct gen6_blend_state
665 GLuint dest_blend_factor
:5;
666 GLuint source_blend_factor
:5;
670 GLuint ia_dest_blend_factor
:5;
671 GLuint ia_source_blend_factor
:5;
673 GLuint ia_blend_func
:3;
675 GLuint ia_blend_enable
:1;
676 GLuint blend_enable
:1;
680 GLuint post_blend_clamp_enable
:1;
681 GLuint pre_blend_clamp_enable
:1;
682 GLuint clamp_range
:2;
684 GLuint x_dither_offset
:2;
685 GLuint y_dither_offset
:2;
686 GLuint dither_enable
:1;
687 GLuint alpha_test_func
:3;
688 GLuint alpha_test_enable
:1;
690 GLuint logic_op_func
:4;
691 GLuint logic_op_enable
:1;
693 GLuint write_disable_b
:1;
694 GLuint write_disable_g
:1;
695 GLuint write_disable_r
:1;
696 GLuint write_disable_a
:1;
698 GLuint alpha_to_coverage_dither
:1;
699 GLuint alpha_to_one
:1;
700 GLuint alpha_to_coverage
:1;
704 struct gen6_color_calc_state
707 GLuint alpha_test_format
:1;
709 GLuint round_disable
:1;
710 GLuint bf_stencil_ref
:8;
711 GLuint stencil_ref
:8;
728 struct gen6_depth_stencil_state
732 GLuint bf_stencil_pass_depth_pass_op
:3;
733 GLuint bf_stencil_pass_depth_fail_op
:3;
734 GLuint bf_stencil_fail_op
:3;
735 GLuint bf_stencil_func
:3;
736 GLuint bf_stencil_enable
:1;
738 GLuint stencil_write_enable
:1;
739 GLuint stencil_pass_depth_pass_op
:3;
740 GLuint stencil_pass_depth_fail_op
:3;
741 GLuint stencil_fail_op
:3;
742 GLuint stencil_func
:3;
743 GLuint stencil_enable
:1;
747 GLuint bf_stencil_write_mask
:8;
748 GLuint bf_stencil_test_mask
:8;
749 GLuint stencil_write_mask
:8;
750 GLuint stencil_test_mask
:8;
755 GLuint depth_write_enable
:1;
756 GLuint depth_test_func
:3;
758 GLuint depth_test_enable
:1;
762 struct brw_cc_unit_state
767 GLuint bf_stencil_pass_depth_pass_op
:3;
768 GLuint bf_stencil_pass_depth_fail_op
:3;
769 GLuint bf_stencil_fail_op
:3;
770 GLuint bf_stencil_func
:3;
771 GLuint bf_stencil_enable
:1;
773 GLuint stencil_write_enable
:1;
774 GLuint stencil_pass_depth_pass_op
:3;
775 GLuint stencil_pass_depth_fail_op
:3;
776 GLuint stencil_fail_op
:3;
777 GLuint stencil_func
:3;
778 GLuint stencil_enable
:1;
784 GLuint bf_stencil_ref
:8;
785 GLuint stencil_write_mask
:8;
786 GLuint stencil_test_mask
:8;
787 GLuint stencil_ref
:8;
793 GLuint logicop_enable
:1;
795 GLuint depth_write_enable
:1;
796 GLuint depth_test_function
:3;
798 GLuint bf_stencil_write_mask
:8;
799 GLuint bf_stencil_test_mask
:8;
806 GLuint alpha_test_func
:3;
808 GLuint blend_enable
:1;
809 GLuint ia_blend_enable
:1;
811 GLuint alpha_test_format
:1;
818 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
824 GLuint ia_dest_blend_factor
:5;
825 GLuint ia_src_blend_factor
:5;
826 GLuint ia_blend_function
:3;
827 GLuint statistics_enable
:1;
828 GLuint logicop_func
:4;
830 GLuint dither_enable
:1;
835 GLuint clamp_post_alpha_blend
:1;
836 GLuint clamp_pre_alpha_blend
:1;
837 GLuint clamp_range
:2;
839 GLuint y_dither_offset
:2;
840 GLuint x_dither_offset
:2;
841 GLuint dest_blend_factor
:5;
842 GLuint src_blend_factor
:5;
843 GLuint blend_function
:3;
856 struct brw_sf_unit_state
858 struct thread0 thread0
;
859 struct thread1 thread1
;
860 struct thread2 thread2
;
861 struct thread3 thread3
;
866 GLuint stats_enable
:1;
867 GLuint nr_urb_entries
:7;
869 GLuint urb_entry_allocation_size
:5;
871 GLuint max_threads
:6;
877 GLuint front_winding
:1;
878 GLuint viewport_transform
:1;
880 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
886 GLuint dest_org_vbias
:4;
887 GLuint dest_org_hbias
:4;
889 GLuint disable_2x2_trifilter
:1;
890 GLuint disable_zero_pix_trifilter
:1;
891 GLuint point_rast_rule
:2;
892 GLuint line_endcap_aa_region_width
:2;
894 GLuint fast_scissor_disable
:1;
901 GLuint point_size
:11;
902 GLuint use_point_size_state
:1;
903 GLuint subpixel_precision
:1;
904 GLuint sprite_point
:1;
906 GLuint aa_line_distance_mode
:1;
908 GLuint linestrip_pv
:2;
909 GLuint tristrip_pv
:2;
910 GLuint line_last_pixel_enable
:1;
915 struct gen6_scissor_rect
923 struct brw_gs_unit_state
925 struct thread0 thread0
;
926 struct thread1 thread1
;
927 struct thread2 thread2
;
928 struct thread3 thread3
;
933 GLuint rendering_enable
:1; /* for Ironlake */
935 GLuint stats_enable
:1;
936 GLuint nr_urb_entries
:7;
938 GLuint urb_entry_allocation_size
:5;
940 GLuint max_threads
:5;
946 GLuint sampler_count
:3;
948 GLuint sampler_state_pointer
:27;
954 GLuint max_vp_index
:4;
956 GLuint svbi_post_inc_value
:10;
958 GLuint svbi_post_inc_enable
:1;
959 GLuint svbi_payload
:1;
960 GLuint discard_adjaceny
:1;
961 GLuint reorder_enable
:1;
967 struct brw_vs_unit_state
969 struct thread0 thread0
;
970 struct thread1 thread1
;
971 struct thread2 thread2
;
972 struct thread3 thread3
;
977 GLuint stats_enable
:1;
978 GLuint nr_urb_entries
:7;
980 GLuint urb_entry_allocation_size
:5;
982 GLuint max_threads
:6;
988 GLuint sampler_count
:3;
990 GLuint sampler_state_pointer
:27;
996 GLuint vert_cache_disable
:1;
1002 struct brw_wm_unit_state
1004 struct thread0 thread0
;
1005 struct thread1 thread1
;
1006 struct thread2 thread2
;
1007 struct thread3 thread3
;
1010 GLuint stats_enable
:1;
1011 GLuint depth_buffer_clear
:1;
1012 GLuint sampler_count
:3;
1013 GLuint sampler_state_pointer
:27;
1018 GLuint enable_8_pix
:1;
1019 GLuint enable_16_pix
:1;
1020 GLuint enable_32_pix
:1;
1021 GLuint enable_con_32_pix
:1;
1022 GLuint enable_con_64_pix
:1;
1024 GLuint legacy_global_depth_bias
:1;
1025 GLuint line_stipple
:1;
1026 GLuint depth_offset
:1;
1027 GLuint polygon_stipple
:1;
1028 GLuint line_aa_region_width
:2;
1029 GLuint line_endcap_aa_region_width
:2;
1030 GLuint early_depth_test
:1;
1031 GLuint thread_dispatch_enable
:1;
1032 GLuint program_uses_depth
:1;
1033 GLuint program_computes_depth
:1;
1034 GLuint program_uses_killpixel
:1;
1035 GLuint legacy_line_rast
: 1;
1036 GLuint transposed_urb_read_enable
:1;
1037 GLuint max_threads
:7;
1040 GLfloat global_depth_offset_constant
;
1041 GLfloat global_depth_offset_scale
;
1043 /* for Ironlake only */
1046 GLuint grf_reg_count_1
:3;
1048 GLuint kernel_start_pointer_1
:26;
1053 GLuint grf_reg_count_2
:3;
1055 GLuint kernel_start_pointer_2
:26;
1060 GLuint grf_reg_count_3
:3;
1062 GLuint kernel_start_pointer_3
:26;
1066 struct brw_sampler_default_color
{
1070 struct gen5_sampler_default_color
{
1079 struct brw_sampler_state
1084 GLuint shadow_function
:3;
1086 GLuint min_filter
:3;
1087 GLuint mag_filter
:3;
1088 GLuint mip_filter
:2;
1089 GLuint base_level
:5;
1090 GLuint min_mag_neq
:1;
1091 GLuint lod_preclamp
:1;
1092 GLuint default_color_mode
:1;
1099 GLuint r_wrap_mode
:3;
1100 GLuint t_wrap_mode
:3;
1101 GLuint s_wrap_mode
:3;
1102 GLuint cube_control_mode
:1;
1112 GLuint default_color_pointer
:27;
1117 GLuint non_normalized_coord
:1;
1119 GLuint address_round
:6;
1121 GLuint chroma_key_mode
:1;
1122 GLuint chroma_key_index
:2;
1123 GLuint chroma_key_enable
:1;
1124 GLuint monochrome_filter_width
:3;
1125 GLuint monochrome_filter_height
:3;
1130 struct brw_clipper_viewport
1138 struct brw_cc_viewport
1144 struct brw_sf_viewport
1155 /* scissor coordinates are inclusive */
1164 struct gen6_sf_viewport
{
1173 /* Documented in the subsystem/shared-functions/sampler chapter...
1175 struct brw_surface_state
1177 struct brw_surf_ss0
{
1178 GLuint cube_pos_z
:1;
1179 GLuint cube_neg_z
:1;
1180 GLuint cube_pos_y
:1;
1181 GLuint cube_neg_y
:1;
1182 GLuint cube_pos_x
:1;
1183 GLuint cube_neg_x
:1;
1185 /* Required on gen6 for surfaces accessed through render cache messages.
1187 GLuint render_cache_read_write
:1;
1188 /* Ironlake and newer: instead of replicating one of the texels */
1189 GLuint cube_corner_average
:1;
1190 GLuint mipmap_layout_mode
:1;
1191 GLuint vert_line_stride_ofs
:1;
1192 GLuint vert_line_stride
:1;
1193 GLuint color_blend
:1;
1194 GLuint writedisable_blue
:1;
1195 GLuint writedisable_green
:1;
1196 GLuint writedisable_red
:1;
1197 GLuint writedisable_alpha
:1;
1198 GLuint surface_format
:9; /**< BRW_SURFACEFORMAT_x */
1199 GLuint data_return_format
:1;
1201 GLuint surface_type
:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
1204 struct brw_surf_ss1
{
1208 struct brw_surf_ss2
{
1215 struct brw_surf_ss3
{
1217 GLuint tiled_surface
:1;
1223 struct brw_surf_ss4
{
1224 GLuint multisample_position_palette_index
:3;
1226 GLuint num_multisamples
:3;
1228 GLuint render_target_view_extent
:9;
1229 GLuint min_array_elt
:11;
1233 struct brw_surf_ss5
{
1235 GLuint llc_mapping
:1;
1236 GLuint mlc_mapping
:1;
1242 } ss5
; /* New in G4X */
1248 struct brw_vertex_buffer_state
1253 GLuint access_type
:1;
1260 GLuint instance_data_step_rate
; /* not included for sequential/random vertices? */
1264 #define BRW_VBP_MAX 17
1266 struct brw_vb_array_state
{
1267 struct header header
;
1268 struct brw_vertex_buffer_state vb
[BRW_VBP_MAX
];
1272 struct brw_vertex_element_state
1276 GLuint src_offset
:11;
1278 GLuint src_format
:9;
1281 GLuint vertex_buffer_index
:5;
1286 GLuint dst_offset
:8;
1288 GLuint vfcomponent3
:4;
1289 GLuint vfcomponent2
:4;
1290 GLuint vfcomponent1
:4;
1291 GLuint vfcomponent0
:4;
1295 #define BRW_VEP_MAX 18
1297 struct brw_vertex_element_packet
{
1298 struct header header
;
1299 struct brw_vertex_element_state ve
[BRW_VEP_MAX
]; /* note: less than _TNL_ATTRIB_MAX */
1303 struct brw_urb_immediate
{
1306 GLuint swizzle_control
:2;
1311 GLuint response_length
:4;
1312 GLuint msg_length
:4;
1313 GLuint msg_target
:4;
1315 GLuint end_of_thread
:1;
1318 /* Instruction format for the execution units:
1321 struct brw_instruction
1327 GLuint access_mode
:1;
1328 GLuint mask_control
:1;
1329 GLuint dependency_control
:2;
1330 GLuint compression_control
:2;
1331 GLuint thread_control
:2;
1332 GLuint predicate_control
:4;
1333 GLuint predicate_inverse
:1;
1334 GLuint execution_size
:3;
1335 GLuint destreg__conditionalmod
:4; /* destreg - send, conditionalmod - others */
1336 GLuint acc_wr_control
:1;
1337 GLuint cmpt_control
:1;
1338 GLuint debug_control
:1;
1345 GLuint dest_reg_file
:2;
1346 GLuint dest_reg_type
:3;
1347 GLuint src0_reg_file
:2;
1348 GLuint src0_reg_type
:3;
1349 GLuint src1_reg_file
:2;
1350 GLuint src1_reg_type
:3;
1352 GLuint dest_subreg_nr
:5;
1353 GLuint dest_reg_nr
:8;
1354 GLuint dest_horiz_stride
:2;
1355 GLuint dest_address_mode
:1;
1360 GLuint dest_reg_file
:2;
1361 GLuint dest_reg_type
:3;
1362 GLuint src0_reg_file
:2;
1363 GLuint src0_reg_type
:3;
1364 GLuint src1_reg_file
:2; /* 0x00000c00 */
1365 GLuint src1_reg_type
:3; /* 0x00007000 */
1367 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
1368 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
1369 GLuint dest_horiz_stride
:2;
1370 GLuint dest_address_mode
:1;
1375 GLuint dest_reg_file
:2;
1376 GLuint dest_reg_type
:3;
1377 GLuint src0_reg_file
:2;
1378 GLuint src0_reg_type
:3;
1379 GLuint src1_reg_file
:2;
1380 GLuint src1_reg_type
:3;
1382 GLuint dest_writemask
:4;
1383 GLuint dest_subreg_nr
:1;
1384 GLuint dest_reg_nr
:8;
1385 GLuint dest_horiz_stride
:2;
1386 GLuint dest_address_mode
:1;
1391 GLuint dest_reg_file
:2;
1392 GLuint dest_reg_type
:3;
1393 GLuint src0_reg_file
:2;
1394 GLuint src0_reg_type
:3;
1396 GLuint dest_writemask
:4;
1397 GLint dest_indirect_offset
:6;
1398 GLuint dest_subreg_nr
:3;
1399 GLuint dest_horiz_stride
:2;
1400 GLuint dest_address_mode
:1;
1404 GLuint dest_reg_file
:2;
1405 GLuint dest_reg_type
:3;
1406 GLuint src0_reg_file
:2;
1407 GLuint src0_reg_type
:3;
1408 GLuint src1_reg_file
:2;
1409 GLuint src1_reg_type
:3;
1412 GLint jump_count
:16;
1420 GLuint src0_subreg_nr
:5;
1421 GLuint src0_reg_nr
:8;
1423 GLuint src0_negate
:1;
1424 GLuint src0_address_mode
:1;
1425 GLuint src0_horiz_stride
:2;
1426 GLuint src0_width
:3;
1427 GLuint src0_vert_stride
:4;
1428 GLuint flag_reg_nr
:1;
1434 GLint src0_indirect_offset
:10;
1435 GLuint src0_subreg_nr
:3;
1437 GLuint src0_negate
:1;
1438 GLuint src0_address_mode
:1;
1439 GLuint src0_horiz_stride
:2;
1440 GLuint src0_width
:3;
1441 GLuint src0_vert_stride
:4;
1442 GLuint flag_reg_nr
:1;
1448 GLuint src0_swz_x
:2;
1449 GLuint src0_swz_y
:2;
1450 GLuint src0_subreg_nr
:1;
1451 GLuint src0_reg_nr
:8;
1453 GLuint src0_negate
:1;
1454 GLuint src0_address_mode
:1;
1455 GLuint src0_swz_z
:2;
1456 GLuint src0_swz_w
:2;
1458 GLuint src0_vert_stride
:4;
1459 GLuint flag_reg_nr
:1;
1465 GLuint src0_swz_x
:2;
1466 GLuint src0_swz_y
:2;
1467 GLint src0_indirect_offset
:6;
1468 GLuint src0_subreg_nr
:3;
1470 GLuint src0_negate
:1;
1471 GLuint src0_address_mode
:1;
1472 GLuint src0_swz_z
:2;
1473 GLuint src0_swz_w
:2;
1475 GLuint src0_vert_stride
:4;
1476 GLuint flag_reg_nr
:1;
1483 GLuint end_of_thread
:1;
1486 } send_gen5
; /* for Ironlake only */
1494 GLuint src1_subreg_nr
:5;
1495 GLuint src1_reg_nr
:8;
1497 GLuint src1_negate
:1;
1498 GLuint src1_address_mode
:1;
1499 GLuint src1_horiz_stride
:2;
1500 GLuint src1_width
:3;
1501 GLuint src1_vert_stride
:4;
1507 GLuint src1_swz_x
:2;
1508 GLuint src1_swz_y
:2;
1509 GLuint src1_subreg_nr
:1;
1510 GLuint src1_reg_nr
:8;
1512 GLuint src1_negate
:1;
1513 GLuint src1_address_mode
:1;
1514 GLuint src1_swz_z
:2;
1515 GLuint src1_swz_w
:2;
1517 GLuint src1_vert_stride
:4;
1523 GLint src1_indirect_offset
:10;
1524 GLuint src1_subreg_nr
:3;
1526 GLuint src1_negate
:1;
1527 GLuint src1_address_mode
:1;
1528 GLuint src1_horiz_stride
:2;
1529 GLuint src1_width
:3;
1530 GLuint src1_vert_stride
:4;
1531 GLuint flag_reg_nr
:1;
1537 GLuint src1_swz_x
:2;
1538 GLuint src1_swz_y
:2;
1539 GLint src1_indirect_offset
:6;
1540 GLuint src1_subreg_nr
:3;
1542 GLuint src1_negate
:1;
1544 GLuint src1_swz_z
:2;
1545 GLuint src1_swz_w
:2;
1547 GLuint src1_vert_stride
:4;
1548 GLuint flag_reg_nr
:1;
1555 GLint jump_count
:16; /* note: signed */
1562 /* Signed jump distance to the ip to jump to if all channels
1563 * are disabled after the break or continue. It should point
1564 * to the end of the innermost control flow block, as that's
1565 * where some channel could get re-enabled.
1569 /* Signed jump distance to the location to resume execution
1570 * of this channel if it's enabled for the break or continue.
1582 GLuint response_length
:4;
1583 GLuint msg_length
:4;
1584 GLuint msg_target
:4;
1586 GLuint end_of_thread
:1;
1597 GLuint header_present
:1;
1598 GLuint response_length
:5;
1599 GLuint msg_length
:4;
1601 GLuint end_of_thread
:1;
1605 GLuint binding_table_index
:8;
1607 GLuint return_format
:2;
1609 GLuint response_length
:4;
1610 GLuint msg_length
:4;
1611 GLuint msg_target
:4;
1613 GLuint end_of_thread
:1;
1617 GLuint binding_table_index
:8;
1620 GLuint response_length
:4;
1621 GLuint msg_length
:4;
1622 GLuint msg_target
:4;
1624 GLuint end_of_thread
:1;
1628 GLuint binding_table_index
:8;
1633 GLuint header_present
:1;
1634 GLuint response_length
:5;
1635 GLuint msg_length
:4;
1637 GLuint end_of_thread
:1;
1640 struct brw_urb_immediate urb
;
1645 GLuint swizzle_control
:2;
1651 GLuint header_present
:1;
1652 GLuint response_length
:5;
1653 GLuint msg_length
:4;
1655 GLuint end_of_thread
:1;
1659 GLuint binding_table_index
:8;
1660 GLuint msg_control
:4;
1662 GLuint target_cache
:2;
1663 GLuint response_length
:4;
1664 GLuint msg_length
:4;
1665 GLuint msg_target
:4;
1667 GLuint end_of_thread
:1;
1671 GLuint binding_table_index
:8;
1672 GLuint msg_control
:3;
1674 GLuint target_cache
:2;
1675 GLuint response_length
:4;
1676 GLuint msg_length
:4;
1677 GLuint msg_target
:4;
1679 GLuint end_of_thread
:1;
1683 GLuint binding_table_index
:8;
1684 GLuint msg_control
:3;
1686 GLuint target_cache
:2;
1688 GLuint header_present
:1;
1689 GLuint response_length
:5;
1690 GLuint msg_length
:4;
1692 GLuint end_of_thread
:1;
1696 GLuint binding_table_index
:8;
1697 GLuint msg_control
:3;
1698 GLuint pixel_scoreboard_clear
:1;
1700 GLuint send_commit_msg
:1;
1701 GLuint response_length
:4;
1702 GLuint msg_length
:4;
1703 GLuint msg_target
:4;
1705 GLuint end_of_thread
:1;
1709 GLuint binding_table_index
:8;
1710 GLuint msg_control
:3;
1711 GLuint pixel_scoreboard_clear
:1;
1713 GLuint send_commit_msg
:1;
1715 GLuint header_present
:1;
1716 GLuint response_length
:5;
1717 GLuint msg_length
:4;
1719 GLuint end_of_thread
:1;
1722 /* Sandybridge DP for sample cache, constant cache, render cache */
1724 GLuint binding_table_index
:8;
1725 GLuint msg_control
:5;
1728 GLuint header_present
:1;
1729 GLuint response_length
:5;
1730 GLuint msg_length
:4;
1732 GLuint end_of_thread
:1;
1733 } dp_sampler_const_cache
;
1736 GLuint binding_table_index
:8;
1737 GLuint msg_control
:3;
1738 GLuint slot_group_select
:1;
1739 GLuint pixel_scoreboard_clear
:1;
1741 GLuint send_commit_msg
:1;
1743 GLuint header_present
:1;
1744 GLuint response_length
:5;
1745 GLuint msg_length
:4;
1747 GLuint end_of_thread
:1;
1751 GLuint function_control
:16;
1752 GLuint response_length
:4;
1753 GLuint msg_length
:4;
1754 GLuint msg_target
:4;
1756 GLuint end_of_thread
:1;
1759 /* Of this struct, only end_of_thread is not present for gen6. */
1761 GLuint function_control
:19;
1762 GLuint header_present
:1;
1763 GLuint response_length
:5;
1764 GLuint msg_length
:4;
1766 GLuint end_of_thread
:1;