src/gallium/drivers/i965/brw_urb.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_batchbuffer.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_debug.h"
  39
  40 #define VS 0
  41 #define GS 1
  42 #define CLP 2
  43 #define SF 3
  44 #define CS 4
  45
  46 /** @file brw_urb.c
  47  *
  48  * Manages the division of the URB space between the various fixed-function
  49  * units.
  50  *
  51  * See the Thread Initiation Management section of the GEN4 B-Spec, and
  52  * the individual *_STATE structures for restrictions on numbers of
  53  * entries and threads.
  54  */
  55
  56 /*
  57  * Generally, a unit requires a min_nr_entries based on how many entries
  58  * it produces before the downstream unit gets unblocked and can use and
  59  * dereference some of its handles.
  60  *
  61  * The SF unit preallocates a PUE at the start of thread dispatch, and only
  62  * uses that one.  So it requires one entry per thread.
  63  *
  64  * For CLIP, the SF unit will hold the previous primitive while the
  65  * next is getting assembled, meaning that linestrips require 3 CLIP VUEs
  66  * (vertices) to ensure continued processing, trifans require 4, and tristrips
  67  * require 5.  There can be 1 or 2 threads, and each has the same requirement.
  68  *
  69  * GS has the same requirement as CLIP, but it never handles tristrips,
  70  * so we can lower the minimum to 4 for the POLYGONs (trifans) it produces.
  71  * We only run it single-threaded.
  72  *
  73  * For VS, the number of entries may be 8, 12, 16, or 32 (or 64 on G4X).
  74  * Each thread processes 2 preallocated VUEs (vertices) at a time, and they
  75  * get streamed down as soon as threads processing earlier vertices get
  76  * theirs accepted.
  77  *
  78  * Each unit will take the number of URB entries we give it (based on the
  79  * entry size calculated in brw_vs_emit.c for VUEs, brw_sf_emit.c for PUEs,
  80  * and brw_curbe.c for the CURBEs) and decide its maximum number of
  81  * threads it can support based on that. in brw_*_state.c.
  82  *
  83  * XXX: Are the min_entry_size numbers useful?
  84  * XXX: Verify min_nr_entries, esp for VS.
  85  * XXX: Verify SF min_entry_size.
  86  */
  87 static const struct urb_limits {
  88    GLuint min_nr_entries;
  89    GLuint preferred_nr_entries;
  90    GLuint min_entry_size;
  91    GLuint max_entry_size;
  92 } limits[CS+1] = {
  93    { 16, 32, 1, 5 },                    /* vs */
  94    { 4, 8,  1, 5 },                     /* gs */
  95    { 5, 10,  1, 5 },                    /* clp */
  96    { 1, 8,  1, 12 },                    /* sf */
  97    { 1, 4,  1, 32 }                     /* cs */
  98 };
  99
 100
 101 static GLboolean check_urb_layout( struct brw_context *brw )
 102 {
 103    brw->urb.vs_start = 0;
 104    brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize;
 105    brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize;
 106    brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize;
 107    brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize;
 108
 109    return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw);
 110 }
 111
 112 /* Most minimal update, forces re-emit of URB fence packet after GS
 113  * unit turned on/off.
 114  */
 115 static int recalculate_urb_fence( struct brw_context *brw )
 116 {
 117    GLuint csize = brw->curbe.total_size;
 118    GLuint vsize = brw->vs.prog_data->urb_entry_size;
 119    GLuint sfsize = brw->sf.prog_data->urb_entry_size;
 120
 121    if (csize < limits[CS].min_entry_size)
 122       csize = limits[CS].min_entry_size;
 123
 124    if (vsize < limits[VS].min_entry_size)
 125       vsize = limits[VS].min_entry_size;
 126
 127    if (sfsize < limits[SF].min_entry_size)
 128       sfsize = limits[SF].min_entry_size;
 129
 130    if (brw->urb.vsize < vsize ||
 131        brw->urb.sfsize < sfsize ||
 132        brw->urb.csize < csize ||
 133        (brw->urb.constrained && (brw->urb.vsize > vsize ||
 134                                  brw->urb.sfsize > sfsize ||
 135                                  brw->urb.csize > csize))) {
 136
 137
 138       brw->urb.csize = csize;
 139       brw->urb.sfsize = sfsize;
 140       brw->urb.vsize = vsize;
 141
 142       brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 143       brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries;
 144       brw->urb.nr_clip_entries = limits[CLP].preferred_nr_entries;
 145       brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
 146       brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries;
 147
 148       brw->urb.constrained = 0;
 149
 150       if (BRW_IS_IGDNG(brw)) {
 151          brw->urb.nr_vs_entries = 128;
 152          brw->urb.nr_sf_entries = 48;
 153          if (check_urb_layout(brw)) {
 154             goto done;
 155          } else {
 156             brw->urb.constrained = 1;
 157             brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 158             brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
 159          }
 160       } else if (BRW_IS_G4X(brw)) {
 161          brw->urb.nr_vs_entries = 64;
 162          if (check_urb_layout(brw)) {
 163             goto done;
 164          } else {
 165             brw->urb.constrained = 1;
 166             brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 167          }
 168       }
 169
 170       if (BRW_DEBUG & DEBUG_MIN_URB) {
 171          brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
 172          brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
 173          brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
 174          brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
 175          brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
 176          brw->urb.constrained = 1;
 177       }
 178
 179       if (!check_urb_layout(brw)) {
 180          brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
 181          brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
 182          brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
 183          brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
 184          brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
 185
 186          /* Mark us as operating with constrained nr_entries, so that next
 187           * time we recalculate we'll resize the fences in the hope of
 188           * escaping constrained mode and getting back to normal performance.
 189           */
 190          brw->urb.constrained = 1;
 191
 192          if (!check_urb_layout(brw)) {
 193             /* This is impossible, given the maximal sizes of urb
 194              * entries and the values for minimum nr of entries
 195              * provided above.
 196              */
 197             debug_printf("couldn't calculate URB layout!\n");
 198             exit(1);
 199          }
 200
 201          if (BRW_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS))
 202             debug_printf("URB CONSTRAINED\n");
 203       }
 204
 205 done:
 206       if (BRW_DEBUG & DEBUG_URB)
 207          debug_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
 208                       brw->urb.vs_start,
 209                       brw->urb.gs_start,
 210                       brw->urb.clip_start,
 211                       brw->urb.sf_start,
 212                       brw->urb.cs_start,
 213                       URB_SIZES(brw));
 214
 215       brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
 216    }
 217
 218    return 0;
 219 }
 220
 221
 222 const struct brw_tracked_state brw_recalculate_urb_fence = {
 223    .dirty = {
 224       .mesa = 0,
 225       .brw = BRW_NEW_CURBE_OFFSETS,
 226       .cache = (CACHE_NEW_VS_PROG |
 227                 CACHE_NEW_SF_PROG)
 228    },
 229    .prepare = recalculate_urb_fence
 230 };
 231
 232
 233
 234
 235
 236 int brw_upload_urb_fence(struct brw_context *brw)
 237 {
 238    struct brw_urb_fence uf;
 239    memset(&uf, 0, sizeof(uf));
 240
 241    uf.header.opcode = CMD_URB_FENCE;
 242    uf.header.length = sizeof(uf)/4-2;
 243    uf.header.vs_realloc = 1;
 244    uf.header.gs_realloc = 1;
 245    uf.header.clp_realloc = 1;
 246    uf.header.sf_realloc = 1;
 247    uf.header.vfe_realloc = 1;
 248    uf.header.cs_realloc = 1;
 249
 250    /* The ordering below is correct, not the layout in the
 251     * instruction.
 252     *
 253     * There are 256/384 urb reg pairs in total.
 254     */
 255    uf.bits0.vs_fence  = brw->urb.gs_start;
 256    uf.bits0.gs_fence  = brw->urb.clip_start;
 257    uf.bits0.clp_fence = brw->urb.sf_start;
 258    uf.bits1.sf_fence  = brw->urb.cs_start;
 259    uf.bits1.cs_fence  = URB_SIZES(brw);
 260
 261    BRW_BATCH_STRUCT(brw, &uf);
 262    return 0;
 263 }